5 years agoARM: tegra11: power: Update core EDP 6A limit table
Alex Frid [Thu, 17 Jan 2013 07:30:35 +0000]
ARM: tegra11: power: Update core EDP 6A limit table

Bug 1200217

Change-Id: I2a6fbcbcaa2a018be27587019a595c0dc7544059
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/192286
(cherry picked from commit 29848156c34aaaf07ed1e28e81dca044a34b2a1e)
Reviewed-on: http://git-master/r/194437
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agomisc: tegra-baseband: fix Coverity forward null issue
Deepak Nibade [Fri, 25 Jan 2013 10:58:48 +0000]
misc: tegra-baseband: fix Coverity forward null issue

Coverity id : 22154

Bug 1046331

Change-Id: I45b051b26c270f000ab3fc5ca939615725550ca6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/194133
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra14: dvfs: Updated with latest tegra11_dvfs
Seshendra Gadagottu [Mon, 21 Jan 2013 22:46:03 +0000]
ARM: tegra14: dvfs: Updated with latest tegra11_dvfs

Disabled Thermal dvfs for bring-up.

Change-Id: Ia5798f67670f01b2cec55b96af78cb67867cd1db
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/192909
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: Add Tegra114 host1x support
Mayuresh Kulkarni [Thu, 13 Dec 2012 10:39:26 +0000]
ARM: tegra: Add Tegra114 host1x support

bug 1041377

Change-Id: I2d8e377b4286c2ccb32edffb9125afcfc361a14a
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/170946
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agovideo: tegra: host: add DT support
Mayuresh Kulkarni [Thu, 3 Jan 2013 15:14:03 +0000]
video: tegra: host: add DT support

- this commit adds the infrastructure to parse and
allocate device from DT
- it also adds support to parse and add resources from DT
into the newly allocated device
- it also matches the device and drivers using .compatible
property
- of_platform_populate() assigns platform_bus as host1x parent, so
condition in nvhost_get_parent() was modified

bug 1041377

Change-Id: Iba99e27cdd67150b7a3853b8a75149fccea9f9ab
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/145937
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra14: Fix build break
Kaz Fukuoka [Fri, 25 Jan 2013 00:46:42 +0000]
ARM: tegra14: Fix build break

Change-Id: I29fab3b08a059089976abdf6d8036ad4d6b959b4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/193981
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: Enable DUAL_CBUS and HAS_CL_DVFS
Kaz Fukuoka [Wed, 23 Jan 2013 03:29:56 +0000]
ARM: tegra14: Enable DUAL_CBUS and HAS_CL_DVFS

Enabled the following CONFIG options.
- CONFIG_TEGRA_DUAL_CBUS
- CONFIG_ARCH_TEGRA_HAS_CL_DVFS

DFLL and DVFS are disabled as follows.
- CONFIG_TEGRA_USE_DFLL_RANGE=0
- CONFIG_TEGRA_CORE_DVFS (not defined)
- CONFIG_TEGRA_CPU_DVFS (not defined)

bug 1213494

Change-Id: Ibe058c2caffdd35f7f9e49d53089186be3a43170
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/193254
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Add support for Audio and BBC1 test
Ravindra Lokhande [Sat, 24 Nov 2012 16:36:34 +0000]
ARM: tegra: Add support for Audio and  BBC1 test

Change-Id: Ie51377735968e289a7d210cc4480d91ec1be223c
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/190244
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoARM: tegra11x: timer save/restore is removed
Bo Yan [Wed, 23 Jan 2013 02:36:33 +0000]
ARM: tegra11x: timer save/restore is removed

The current timer save and restore is unnecessary because it's done
by broadcast mode entry/exit. The clock event using arch timer does
not support the feature "CLOCK_EVT_MODE_PERIODIC", so there is
nothing comparable to tegra30 in which the periodic load has to be
preserved.

Change-Id: Ia1f91be4f7d1f6e827c95ce013502c77a3c389b0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/193239
(cherry picked from commit de701176ec031f68f3f2c6ecab294745d46c1099)
Reviewed-on: http://git-master/r/193979
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: Tegra: Dalmore: Update emc table: T40X
Peter Zu [Sat, 19 Jan 2013 06:36:47 +0000]
ARM: Tegra: Dalmore: Update emc table: T40X

T40X shares the same emc dvfs table as T40T

Change-Id: Ifee2e4b0f93d1e286713e6fb0033ae1564dcec09
Signed-off-by: Peter Zu <pzu@nvidia.com>
Reviewed-on: http://git-master/r/192622
(cherry picked from commit cd0829b4f2894212c40043df830fe05f2d230891)
Reviewed-on: http://git-master/r/193760
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: Tegra: Dalmore: Update emc table: T40S
Graziano Misuraca [Mon, 14 Jan 2013 21:19:35 +0000]
ARM: Tegra: Dalmore: Update emc table: T40S

Add emc dvfs table for 792/408/312/204/102/
40.8/20.4/12.75 MHz support on T40S chips

Change-Id: I5a77cce084b76f049fb2a728cb57f13a756d945b
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/191002
(cherry picked from commit a964502287cb2bdb0f86864865b8848d289f7dcb)
Reviewed-on: http://git-master/r/193759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: Tegra: Dalmore: Update emc dvfs table
Graziano Misuraca [Tue, 8 Jan 2013 21:36:43 +0000]
ARM: Tegra: Dalmore: Update emc dvfs table

Add emc dvfs table for 924/792/624/408/
312/204/102/68/40.8/20.4/12.75 MHz support
on T40T chips

Change-Id: I3c463264589345a21506feb7bd63e2ad41972968
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/190721
(cherry picked from commit 20992e95f04f2d619509cc437133a46b5a11ca7d)
Reviewed-on: http://git-master/r/193758
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoHID: hid-sony: Silence a GCC mixed declarations and code warning
Sami Liedes [Thu, 24 Jan 2013 15:06:15 +0000]
HID: hid-sony: Silence a GCC mixed declarations and code warning

Swap the order of the declaration of led_data and the call to
hid_info() in sixaxis_set_led_bt() to silence a GCC warning.

Change-Id: I62964e6eb530b86d7cae1b80958285803115a460
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/193824
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agogpio: max77663: Check gpiochip_remove() return value.
Sami Liedes [Thu, 24 Jan 2013 14:43:23 +0000]
gpio: max77663: Check gpiochip_remove() return value.

gpiochip_remove() return value is not checked in max77663_gpio_probe()
failure path. However gpiochip_remove() is tagged __must_check, hence
this causes a warning.

Add a check that calls dev_err() on failure.

Change-Id: Ice9af31832c34d4dd4b333f41f13f1417f873f0c
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/193821
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoinput: touch: atmel: Update Ftrace logging.
Vikas Jain [Fri, 18 Jan 2013 06:37:23 +0000]
input: touch: atmel: Update Ftrace logging.

Renamed touchscreen ftrace event to reflect
hardware module it is tracing. With this change,
each touchscreen hardware will have seperate
ftrace events.

Bug 1170830.

Change-Id: I45ffb3a264d958c9732d89bd2b5d4d62a9640267
Signed-off-by: Vikas Jain <vjain@nvidia.com>
Reviewed-on: http://git-master/r/192314
(cherry picked from commit 1293fbcebba2a07f378f6747678864a5ffba017f)
Reviewed-on: http://git-master/r/193664
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: board changes due to thermal_trip_info use in driver
Diwakar Tundlam [Thu, 17 Jan 2013 19:54:37 +0000]
arm: tegra: board changes due to thermal_trip_info use in driver

Bug 1200075

Change-Id: I5feae9296aae7a88585bbfc4a49478bb33602b40
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/192129
(cherry picked from commit 367624c5cebba25671ff8ac2870aa9162ccffac4)
Reviewed-on: http://git-master/r/193897
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: edp changes due to thermal_trip_info use in driver
Diwakar Tundlam [Thu, 17 Jan 2013 19:44:26 +0000]
arm: tegra: edp changes due to thermal_trip_info use in driver

Bug 1200075

Change-Id: I96b01b1caa468c0d376e79b416aeb329e1cb0390
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/190820
(cherry picked from commit bedff5775d6dab5870a777a1b5a1abfc9e23b033)
Reviewed-on: http://git-master/r/193896
Reviewed-by: Automatic_Commit_Validation_User

5 years agomisc: nct1008: use common thermal_trip_info in nct driver
Diwakar Tundlam [Fri, 11 Jan 2013 07:41:38 +0000]
misc: nct1008: use common thermal_trip_info in nct driver

Bug 1200075

Change-Id: I82e5a7ea8dc1e033ebf7d37ab17b39a4217b55e9
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/190574
(cherry picked from commit bf8d7e0d8805ca5a1db1dcd4f396279963d3b235)
Reviewed-on: http://git-master/r/193895
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: imx091: lower max VI clock to 204MHz
Frank Chen [Thu, 17 Jan 2013 00:20:42 +0000]
video: tegra: imx091: lower max VI clock to 204MHz

Lower the max VI clock for imx091 from 250MHz
to 204MHz. This is to match what is currently
specified in the sensor mode table. This is done
by lowering the clock multiplier from 10.41667
to 8.5(24MHz * 8.5 = 204MHz).

On some older T114 platforms, we are not able to
set VI clock to 250MHz due to the slower memory
clock. This will end up slowing our VI_SENSOR
clock and make frame rate lower.

Bug 1207018

Change-Id: Ia8b582c740d57409b28e6aa696c29b85e23dceba
Reviewed-on: http://git-master/r/191825
(cherry picked from commit 7a547b1044ec57bbb5590651a4373ca8cfee7886)

Signed-off-by: Frank Chen <frankc@nvidia.com>
Change-Id: Id566450b6371d06c1ecd22a8824f4ef73bd10b1d
Reviewed-on: http://git-master/r/193496
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Remove Tegra14 lines
Kaz Fukuoka [Wed, 23 Jan 2013 00:10:17 +0000]
ARM: tegra11: clock: Remove Tegra14 lines

Tegra14 is not sharing tegra11_clocks.c any more.

bug 1213494

Change-Id: I2808783817824fe335e76e57603dd9b2d11b561d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/193198
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra14: clock: Change PLLC2/C3 sequence
Kaz Fukuoka [Mon, 21 Jan 2013 23:23:24 +0000]
ARM: tegra14: clock: Change PLLC2/C3 sequence

On Tegra14, PLLC2 and PLLC3 sequence is changed from Tegra11
interms of ENABLE and IDDQ.

bug 1217350
bug 1213494
bug 972379
bug 1213494

Change-Id: Ic523e6b3703bbce1aa2b4da46ad59b2344be010b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/192910
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra14: clock: WARN_ON for PLLX_MISC3_IDDQ
Kaz Fukuoka [Sat, 19 Jan 2013 03:48:31 +0000]
ARM: tegra14: clock: WARN_ON for PLLX_MISC3_IDDQ

Due to bug 1206550, bootloader doesn't handle
PLLX_MISC3_IDDQ at this point. Because this case is
not serious on FPGA, we treat it as warning for now.
Once bug 1206550 is fixed, this should be changed
to BUG_ON.

bug 1213494
bug 1206550

Change-Id: I2219b5e5cdd9a526be32b4ef0eb80e51cf40c56d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/192603
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra14: clock: Fix mux inputs
Kaz Fukuoka [Sat, 19 Jan 2013 02:57:12 +0000]
ARM: tegra14: clock: Fix mux inputs

Change mux inputs to match with the latest Tegra14 spec.

bug 1213494

Change-Id: I75b338a9f831e6ca168233eeceaf7a42e3fd1046
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/192597
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra14: clock: Remove non-existent blocks
Kaz Fukuoka [Fri, 18 Jan 2013 00:14:19 +0000]
ARM: tegra14: clock: Remove non-existent blocks

Removed the following blocks.
- PLLE, XUSB, PLLREFE
- PCIE, PCIEX, AFI

bug 1213494

Change-Id: I2347e567dca1bcc092bf9286eb99b34ce54d6e5c
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/192212
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agowatchdog: max77660: Add support for system watchdog timer
Laxman Dewangan [Sun, 20 Jan 2013 04:39:22 +0000]
watchdog: max77660: Add support for system watchdog timer

Add watchdog timer driver for MAX77660 system watch dog timer.

Change-Id: I2470f90f924d648d12d8303be6524dd5a2401521
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192674
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomfd: max77660: add system watchdog timer as mfd sub devices
Laxman Dewangan [Sun, 20 Jan 2013 03:30:44 +0000]
mfd: max77660: add system watchdog timer as mfd sub devices

Add the system watchdog timer driver as mfd sub device of the max77660.

Change-Id: Ib9ddfbf6a81c1abcc0188e8b83c66bbfd20aa178
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192673
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomfd: max77660: simplify the regmap and i2c client initialisation
Laxman Dewangan [Sun, 20 Jan 2013 03:18:10 +0000]
mfd: max77660: simplify the regmap and i2c client initialisation

Use the loop for initialising the regmap and i2c client for different i2c slave
addresses of the max77660.

Change-Id: I37fdad3f220dbd6152a5f0c56a7740a385e4dd13
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192671
Reviewed-by: Automatic_Commit_Validation_User

5 years agostaging:nvshm: BB logging channel handled as a tty channel
Alexandre Berdery [Wed, 16 Jan 2013 09:08:11 +0000]
staging:nvshm: BB logging channel handled as a tty channel

Bug 1219150

Change-Id: If322f287f1d56a88bfbd6063deaa145ad2ba308e
Signed-off-by: Alexandre Berdery <aberdery@nvidia.com>
Reviewed-on: http://git-master/r/191618
Reviewed-by: Greg Heinrich <gheinrich@nvidia.com>
Reviewed-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra: dalmore: cleanup key support for 1000 and 1001 SKU
Laxman Dewangan [Thu, 24 Jan 2013 08:31:01 +0000]
ARM: tegra: dalmore: cleanup key support for 1000 and 1001 SKU

The 1001 SKU keys are supported with GPIO keys and KBC keys. Looking
at schematics, we do not need to have Tegra KBC based mapping for 1001
SKU. GPIO keys will suffice the requirements.

Clean-up the key registration and add all keys of 1001 SKU as gpio keys

bug 1222030

Change-Id: I83abacd75c38a3c34571eb54687e85cdeb6e7176
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/193693
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>

5 years agoARM: tegra30: Remove arch timer code from cpuidle
Bo Yan [Tue, 22 Jan 2013 23:35:18 +0000]
ARM: tegra30: Remove arch timer code from cpuidle

The cpuidle code for tegra30 now doesn't contain anything specific
to tegra chips with arch timer. tegra30 doesn't have arch timer.

The CONFIG_HAVE_ARM_TWD references are also removed since it is
always defined for tegra30.

Change-Id: If2d977104b4c179d4aa3b5672f808db7a5467e6f
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/193179
(cherry picked from commit 2c635b5e7720d9edf9867657eb3db5b998d64b8a)
Reviewed-on: http://git-master/r/193508
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra11: clock: set IDDQOVERIDE for UTMIPLL
Rakesh Bodla [Tue, 15 Jan 2013 08:17:58 +0000]
ARM: tegra11: clock: set IDDQOVERIDE for UTMIPLL

Setting IDDQ_OVERRIDE for UTMIPLL by default,
otherwise power is consumed on UTMIPLL rail if no
usb device is active. Power is also seen
high once resume from LP0 if it is not set.

Bug 1174123
Bug 1215521

Reviewed-on: http://git-master/r/191177
(cherry picked from commit a0a0ceeeec6a6dbf329e9bd5dcb28b13a9a3b229)

Change-Id: Idb76aa8c5f3f8c722800ef5e1a2493fbc1160cf7
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/193068
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agortc: max77660: Fix usage of max77660 read APIs
Chaitanya Bandi [Sat, 19 Jan 2013 12:04:18 +0000]
rtc: max77660: Fix usage of max77660 read APIs

Bug 1216995

Change-Id: I9052fbd3dab1ac8199854b3fdd2d5471c5061ea1
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/192637
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra_fuse: Add chip revision A02 for T114
Hoang Pham [Sat, 19 Jan 2013 02:31:42 +0000]
ARM: tegra_fuse: Add chip revision A02 for T114

Also correct minor number for T148 A01

Change-Id: If182dc6c7d6c8c6a8407af0b22b9a941184deff7
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/192594
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: clock: PLLP fixed rate is 408MHz
Kaz Fukuoka [Sat, 19 Jan 2013 01:05:28 +0000]
ARM: tegra14: clock: PLLP fixed rate is 408MHz

PLLP fixed rate is changed from 216MHz to 408MHz on Tegra14.
HW automatically sets PLLP to this rate.
SW doensn't have to, and does not override this setup.

bug 1213494

Change-Id: I4abdc1e912e38f1370efa1eefc25d690a3b8d4a8
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/192574
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: roth: add leds-pwm
Hao Tang [Sat, 15 Dec 2012 23:35:07 +0000]
ARM: roth: add leds-pwm

Add leds-pwm on roth platform for notification feature

Bug 1198937

Change-Id: I859befd3ef4a8178668d84f2a539fcc25b776e8f
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/171671
(cherry picked from commit 203bd3192ad68d12674343b175230d8a41bdc890)
Reviewed-on: http://git-master/r/191875
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: config: enable leds-pwm and trigger
Hao Tang [Thu, 17 Jan 2013 03:26:29 +0000]
ARM: config: enable leds-pwm and trigger

Bug 1198937

Change-Id: I772a3c6cc6fee23a8d6b9a899e0379b72a2593d8
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/171672
(cherry picked from commit 1412345f6a19b345c218d2c2aba4e78dba1ddaae)
Reviewed-on: http://git-master/r/191874
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomedia: video: tegra: refactor debugfs support
Wei Chen [Wed, 23 Jan 2013 00:21:35 +0000]
media: video: tegra: refactor debugfs support

refactor camera driver debugfs support and
add support to ov9772 and imx132

bug 1037602

Change-Id: I20bfcd2dce3c21412ee4bfa20ad416a1e8fc4d95
Signed-off-by: Wei Chen <wechen@nvidia.com>
Reviewed-on: http://git-master/r/191793
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Enable -Werror in mach-tegra
Kaz Fukuoka [Tue, 8 Jan 2013 03:49:23 +0000]
ARM: tegra: Enable -Werror in mach-tegra

bug 1213479

Change-Id: Ic9318aee5c37d19668c302bd4ee8d12116f86f30
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/189408
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agothermal: platform_data: define common thermal_trip_info structure
Diwakar Tundlam [Thu, 10 Jan 2013 22:59:25 +0000]
thermal: platform_data: define common thermal_trip_info structure

Add a common platform_data header file to share trip point information
among thermal sensor drivers and platform files.

Bug 1200075

Change-Id: Iee5bb387b352c57362156415c6a73bc99539ee00
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/190823
(cherry picked from commit 6f75cb4af4e20029c2d31faa9f6478f959bd0eab)
Reviewed-on: http://git-master/r/193478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>

5 years agoARM: tegra: clocks: state check in resume
Seshendra Gadagottu [Wed, 23 Jan 2013 03:22:04 +0000]
ARM: tegra: clocks: state check in resume

Check the validity of cl_dvfs state before calling
tegra_cl_dvfs_resume.

Change-Id: I977582b13b7570029b9018b49e8beca98095f469
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/193253
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoregulator: max77660: add regulator enable time
Pradeep Goudagunta [Thu, 17 Jan 2013 14:32:26 +0000]
regulator: max77660: add regulator enable time

Add 500us regulators enable time.

Bug 1058717

Change-Id: I1e8824eac9c597f1bdf0ee14295a1eebcdb3c0d1
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/192068
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoregulator: max77660: Fix FPS_REG configuration
Pradeep Goudagunta [Thu, 17 Jan 2013 06:13:29 +0000]
regulator: max77660: Fix FPS_REG configuration

Bug 1210609

Change-Id: I34ab8893f08d6666e6a52f70979f6c8596566fdc
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/191910
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: tegra_bb: fix ipc memory region sizing
Martin Chabot [Tue, 22 Jan 2013 08:31:59 +0000]
arm: tegra: tegra_bb: fix ipc memory region sizing

ipc size was wrongly taken from private size field

Bug 1217721

Change-Id: I18356c25639dbbd354e68e1d56beecdb3d19509d
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/193001
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Jean-Marc Guiraudet <jguiraudet@nvidia.com>

5 years agocpuquiet: Add GCOV_PROFILE for governors
Juha Tukkinen [Tue, 22 Jan 2013 08:30:28 +0000]
cpuquiet: Add GCOV_PROFILE for governors

Include cpuquiet in GCOV profiling when enabled by defconfig.

Change-Id: Iadac806d4b7efd9e34afa765dbec59f0491b96a8
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/192980
Reviewed-by: Automatic_Commit_Validation_User

5 years agousb: xhci: fix Short Packet handling for isochronous
JC Kuo [Thu, 6 Dec 2012 12:16:19 +0000]
usb: xhci: fix Short Packet handling for isochronous

When Short Packet happens on a multiple-TRBs TD, xHCD needs to
calculate the exact amount of transferred data because upper layer
driver wants it. In order to achieve, xHCD has to:
1. set ISP bit for all TRBs belongs to a IN TD, and
2. set IOC bit for the last TRB of the IN TD.

Once HC detects a Short Transfer, HC will send Short Packet event for
the TRB which encountered Short Packet and also send Short Packet event
fot the last TRB which has IOC bit set.

With those two events, xHCD can calculate the exact amount of bytes which
xHC has completed for the TD. (4.10.1.1)

Bug 1158352

Change-Id: I38f04825ddc3e12f124e12a9abf05a36beb43886
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/192883
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra: pcie: Fix section mismatch warning
Jay Agarwal [Mon, 21 Jan 2013 14:25:56 +0000]
ARM: tegra: pcie: Fix section mismatch warning

Bug 1038578

Change-Id: I854791c9c098e94e7065d9115fa9d515c354cc4a
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/192862
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: t14x: Clear DPD_SAMPLE on LP0 exit
aghuge [Mon, 21 Jan 2013 10:41:36 +0000]
ARM: tegra: t14x: Clear DPD_SAMPLE on LP0 exit

Power management code needs to clear
PMC_DPD_SAMPLE during LP0 exit after pinmux
restoration

Bug 1193188

Change-Id: I40247bace4811fa0db69dfba7e952b32ad22a8fc
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/192782
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agomedia: video: tegra: imx091: Add standard preview mode
Frank Chen [Tue, 8 Jan 2013 18:43:34 +0000]
media: video: tegra: imx091: Add standard preview mode

Add standard preview mode (2104x1560) for imx091.

This standard preview mode replaces the low
quality 1052x780 preview mode. This will
improve the auto focuser accuracy.

Bug 1203989

Change-Id: I3be6d47a699bb543befb19e7462ff5a99b4b81d2
Reviewed-on: http://git-master/r/189594
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/192769
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: T148: ceres: Add pinmux support for t148 ceres
aghuge [Mon, 21 Jan 2013 06:29:44 +0000]
ARM: tegra: T148: ceres: Add pinmux support for t148 ceres

Update T148 pinmux and add support for ceres board pinmux

Bug 1178627

Change-Id: Iaa90a65562e71507c11023e8dd52815e68da535a
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/192388
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: emc: Cleanup clock change sequence
Alex Waterman [Sat, 12 Jan 2013 00:15:20 +0000]
arm: tegra: emc: Cleanup clock change sequence

Remove the DDR3 steps from the EMC's clock setting function.
Since T148 will not support DDR3, these steps are no longer
needed.

Remove t114 style trimmer updating. T148 does not have a dual
channel memory controller so trimmers can be packed into the
burst list.

Change-Id: I3aa54ea31f30329198c7846b41c78d155302d8a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/190808
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra: include guard for header file
Sachin Nikam [Wed, 23 Jan 2013 14:21:41 +0000]
arm: tegra: include guard for header file

Adding include gaurd for header to avoid multiple inclusion.

Change-Id: I57e0eb2ca248bd97e62b1499b98adf7f6850fb04
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/193420
Reviewed-by: Automatic_Commit_Validation_User

5 years agortc: max77660: use platform_get_irq() for getting irq number
Laxman Dewangan [Mon, 21 Jan 2013 06:15:16 +0000]
rtc: max77660: use platform_get_irq() for getting irq number

Use platform_get_irq() for getting irq number in place of directly
accessing irq through platform data.

Also doing some cleanups related to interrupts.

Change-Id: I860939072f227db7ee14b005865c591b08dc9899
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192836
Reviewed-by: Automatic_Commit_Validation_User

5 years agortc: max77660: add wake capabilities and suspend/resume
Laxman Dewangan [Mon, 21 Jan 2013 06:05:35 +0000]
rtc: max77660: add wake capabilities and suspend/resume

Enable wake of from the RTC when enetering into suspend and
disable wake in resume.

Also make wake capable so that wake capabilty can be
enable/disable through user space.

Change-Id: Ibe118a62d13109dd25b5f5d025d8bef68117cf61
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192835
Reviewed-by: Automatic_Commit_Validation_User

5 years agortc: max77660: use devm_* for resource allocation
Laxman Dewangan [Mon, 21 Jan 2013 05:52:44 +0000]
rtc: max77660: use devm_* for resource allocation

This reduces the code for freeing the resources as this allocation
is managed allocation.

Change-Id: I93f6b965467eab5d646f11ab471fd030484bc616
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192834
Reviewed-by: Automatic_Commit_Validation_User

5 years agortc: max77660: use module_platform_driver
Laxman Dewangan [Mon, 21 Jan 2013 05:46:03 +0000]
rtc: max77660: use module_platform_driver

Use module_platform_driver in place of module_init() and
module_exit() for reducing code lines.

Change-Id: I8ccfb403cd6e1dd3a2134577ee1bb9a5568063c5
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/192833
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: actmon: Update for t148
Alex Waterman [Wed, 16 Jan 2013 00:04:09 +0000]
ARM: tegra: actmon: Update for t148

Update the EMC actmon device struct for t148's single channel
EMC. The count weight needs to be the same as T30, not T114, for
T148.

Change-Id: I9aedf274be6b7f93be4f91287c24e536a54a59cd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/191475
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agomisc: nct: re enable suspend/resume with proper power on delay
Sri Krishna chowdary [Tue, 8 Jan 2013 05:44:07 +0000]
misc: nct: re enable suspend/resume with proper power on delay

Bug 1205034
Bug 1219601

Change-Id: I66581a022f42517bb9cd08ca49cdf57a28deb322
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/189429
Reviewed-on: http://git-master/r/193338
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: usb_phy: protect disable PMC and remove delay
Suresh Mangipudi [Mon, 21 Jan 2013 09:11:24 +0000]
ARM: tegra: usb_phy: protect disable PMC and remove delay

Disable the local irq to prevent context switch between disable PMC and
set RUN bit ops in case of remote wakeup.

Operations of disable PMC control and set RUN bit might be interrupted
and scheduled out which would take a long time until RUN bit set, so
device won't see the SOFs within 3ms and go back into suspend again.
Resulting in the ehci controller issuing a reset-resume, to recover.

Bug 1213088

Change-Id: Ia1232ef34ce7df937bcedbb2f294fffb4c8f9a73
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/192794
(cherry picked from commit 3c186ebc4ecc03a0cf085e201cf2ab84e3efcb09)
Reviewed-on: http://git-master/r/193291
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra11x: set cpu_lp2_min_residency to 1000
Richard Zhao [Mon, 21 Jan 2013 01:51:41 +0000]
ARM: tegra11x: set cpu_lp2_min_residency to 1000

cpu_lp2_min_residency set the minimal cpuidle lp2 target residency. It
can tune chances entering to lp2.

It fixes bug that lp2 consumes more power when video playback. If
cpu_lp2_min_residency is zero, it causes higher G cpu residency and
more cluster switch.

Bug 1216668

Change-Id: I7246dda75fea488b75d8f4a0a8446e2efe3b55e0
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/192702
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hunk Lin <hulin@nvidia.com>
Reviewed-by: Soumenkumar Dey <sdey@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: config: tegra11: enable Tskin throttling
Hyungwoo Yang [Sat, 19 Jan 2013 08:13:37 +0000]
ARM: config: tegra11: enable Tskin throttling

Enable Tskin throttling by default for tegra11 platforms.

We enable Tskin throlling by default but Tskin throttling will never
happen due to its default Tskin coefficient values
in skin temperature estimator.

To make it work correctly, a platform should develop and set its own
correct Tskin coefficient values.

Bug 1158323

Change-Id: I0bf68df557a0a92287f0e5a4970aa1662ef7244e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/192559
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoasoc: tegra: aic326x: Fix BT and normal voice call switching
Rahul Mittal [Wed, 16 Jan 2013 09:37:40 +0000]
asoc: tegra: aic326x: Fix BT and normal voice call switching

DAM was getting configured in passthrough mode in normal voice call path
DAM not required in normal voice call, as BB and codec both operate at 16khz
Disabled the DAM from voice path for aic3262 codec, which fixed the switching

Bug 1179798

Change-Id: I85e920f264f93747d1721cb5e76fbb36fd18637a
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/192078
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoASoC: Tegra: fix compile error and use regulator
Seema Khowala [Wed, 16 Jan 2013 19:53:41 +0000]
ASoC: Tegra: fix compile error and use regulator

Bug 1189404

Change-Id: I934e3d1809b50e37485a42a0476d122edbd4fad7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/190277
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm: tegra: roth: Fix TFA device patch header.
Scott Peterson [Fri, 4 Jan 2013 04:18:28 +0000]
arm: tegra: roth: Fix TFA device patch header.

Skip first 6 bytes of the patch file for TFA
speaker amplifier firmware.

Change-Id: I7b214c1f2bdee49d435da898cd1948933a9d8614

Reviewed-on: http://git-master/r/188524
Reviewed-on: http://git-master/r/189355

(cherry picked from commit 854c7ec9f62ffed113dae57a8561c49877639785)

Signed-off-by: Scott Peterson <speterson@nvidia.com>
Change-Id: I9baae6b4bf0253afb28d394f2aea4d70646f5cb6
Reviewed-on: http://git-master/r/192908
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agoarm: tegra: roth: Reduce volume change clicks
Scott Peterson [Fri, 4 Jan 2013 23:51:44 +0000]
arm: tegra: roth: Reduce volume change clicks

Reduce the number of clicks in volume changes
by only writing TFA8997 device presets when a
new preset is detected.

Bug 1211519    Partial fix

Reviewed-on: http://git-master/r/188829
Change-Id: Ib332cd9a99562120dd1092045e883b2c9c97ba90

(cherry picked from commit fe38018d13f9f20402ce2ab929b8fa08795b3a42)

Signed-off-by: Scott Peterson <speterson@nvidia.com>
Change-Id: I3acc8a805aee0fb4987fe275f818801b003dfff2
Reviewed-on: http://git-master/r/192907
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agoroth: audio: Add NULL checks for TFA devices
Scott Peterson [Wed, 2 Jan 2013 17:45:26 +0000]
roth: audio: Add NULL checks for TFA devices

Add checks for valid TFA device instances before
allowing calibration or config changes.

bug 1211900

Change-Id: Ibb5bd6db9ecc93f1320fc6d61f28dbd7ccc394dd
Reviewed-on: http://git-master/r/190027

(cherry picked from commit a2d345820562c3c6e1c3d5944e22b3457dd59efd)

Signed-off-by: Scott Peterson <speterson@nvidia.com>
Change-Id: I79dc7768bc7a65cb0a75c3944aba0de0a7715974
Reviewed-on: http://git-master/r/192906
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agoroth: audio: Improved volume step perf.
Scott Peterson [Thu, 3 Jan 2013 20:43:41 +0000]
roth: audio: Improved volume step perf.

Revert change to mute whils doing volume changes
on the NXP speaker device.

Optimize I2C writes to NXP device.

Verified most recent NXP patch and config files.

Change-Id: I602b30d84c0b0ac00a7e4083dc436bb16c472215
Reviewed-on: http://git-master/r/188399

(cherry picked from commit 4be05d5d4114e2949faab23a57d367bf2238a0dd)

Signed-off-by: Scott Peterson <speterson@nvidia.com>
Change-Id: I0aab264b5cfbdcbcff07757f2bf12c33d77bed40
Reviewed-on: http://git-master/r/192905
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agoARM: tegra: t14x: Clear DPD_ENABLE on LP0 exit
Seshendra Gadagottu [Fri, 18 Jan 2013 01:09:16 +0000]
ARM: tegra: t14x: Clear DPD_ENABLE on LP0 exit

T14X core power management code needs to clear
PMC_DPD_ENABLE during LP0 exit.

Bug 1193188

Change-Id: I852194e3a88cf2b08589affa91ea4710ef8df337
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/192226
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agochar: tegra: Character device interface for tegra gmi bus
Ashutosh Patel [Fri, 18 Jan 2013 05:24:43 +0000]
char: tegra: Character device interface for tegra gmi bus

Tegra gmi bus supports multiple devices to be connected to the bus.
This drivers add character device interface for device connected on the bus.

Change-Id:Ie1de58e5108e55b1e058f4871541c734ee70f4ff
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Signed-off-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-on: http://git-master/r/191632
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: Enable ahub clock in tegra30_dam_show().
Sami Liedes [Tue, 15 Jan 2013 13:41:34 +0000]
arm: tegra: Enable ahub clock in tegra30_dam_show().

The audio hub clock needs to be enabled when reading DAM
registers. This fixes a hang when reading /d/asoc/tegra30-dam.0.

Bug 1210765

Change-Id: I584cf6b3cb49e35f3b937f86f6412cb4a7ed89f8
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/191360
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra11: dvfs: Fix variable name spelling
Alex Frid [Sat, 12 Jan 2013 02:34:10 +0000]
ARM: tegra11: dvfs: Fix variable name spelling

Change-Id: Ib991c78542113aca51f7d34274fde836a715f7aa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190830
(cherry picked from commit 24940eb6f26ff7d42242612f470468b6f7fa4a91)
Reviewed-on: http://git-master/r/192664
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Enable clock on CL-DVFS debugfs access
Alex Frid [Sat, 12 Jan 2013 04:34:31 +0000]
ARM: tegra11: dvfs: Enable clock on CL-DVFS debugfs access

Made sure module clock is enabled during access to CL-DVFS registers
via debugfs interface.

Change-Id: Ieb9a239cd828b68901277ca9fb109d4fec11810e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190829
(cherry picked from commit 094ef721c3b331fc53a325f65e227a7376ed52ce)
Reviewed-on: http://git-master/r/192663
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Re-factor CL-DVFS initialization
Alex Frid [Sat, 12 Jan 2013 03:30:33 +0000]
ARM: tegra11: dvfs: Re-factor CL-DVFS initialization

Moved platform data NULL-pointers validation before CL-DVFS object
is allocated. Removed redundant and added missed NULL-pointers checks.

Change-Id: Iceafe7bb586ff5ae996e72d1331bf9ffa2868681
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190828
(cherry picked from commit 35df2c39be15131404e666b0dcc46b56cba5e8bd)
Reviewed-on: http://git-master/r/192662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Update CL-DVFS output disable procedure
Alex Frid [Wed, 5 Dec 2012 04:56:11 +0000]
ARM: tegra11: dvfs: Update CL-DVFS output disable procedure

Poll for CL-DVFS idle state. When two samples in a row with 2us delay
show no output transaction, disable output. Then check CL-DVFS state
again, and exit if it is still idle. Otherwise, re-enable output, and
continue poll for idle state, until timeout.

The overall idle polling scheme is the same as before, just dual idle
state confirmation with 2us delay is added.

Bug 1159200

Change-Id: Ib4c217a7bc13da3089d065ef33aab37c6f1b4043
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190817
(cherry picked from commit 7663b12a8172477915770277abfcc376e3834476)
Reviewed-on: http://git-master/r/168612
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agousb: xhci: tegra: add delay after PMC_USB_AO_0 program
Ajay Gupta [Wed, 16 Jan 2013 22:23:56 +0000]
usb: xhci: tegra: add delay after PMC_USB_AO_0 program

We have seen LP0 loop when system wake done using FS device connect.
Discussed with hardware team and USB2 team and this delay is needed
for D+/D- value detectors to become stable

BUG 1221008

Change-Id: If755c69013e1124b7edf22eff10f46ee054fe6c1

Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Change-Id: I5b12a2930c718b00c69015386ef8662a7a6fe109
Reviewed-on: http://git-master/r/192890
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Joy Wang <joyw@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoARM: tegra11: dvfs: Replace CL-DVFS constraints mechanism
Alex Frid [Tue, 8 Jan 2013 04:58:07 +0000]
ARM: tegra11: dvfs: Replace CL-DVFS constraints mechanism

CL-DVFS h/w limitations do not allow dynamically change minimum and
maximum output limits in the output configuration register. Instead,
this commit added indirect CL-DVFS constraints mechanism: adjusting
look-up table (maps output values to the regulator voltage settings)
with duplicated minimum settings all the way below minimum entry, and
duplicated maximum settings all the way above maximum entry.

The indirect constraints implementation breaks output values comparison
across look-up table re-load. Hence, we need to make sure that
- after any change in constraints a forced voltage request within new
range is sent - this policy is already in place
- minimum and safe output entries in the table are never throttled down
as a result of table re-loading - done in this commit by adding minimax
output limit (minimum boundary for possible maximum constraints).

Bug 1212891

Change-Id: Icf67842c1c030fe8579e2ac6990b6baa955ad355
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/189447
(cherry picked from commit 78f9e43a3ddc06af257eb46b62c0f9b9ec3b50ba)
Reviewed-on: http://git-master/r/192661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Add clock change delay on LP1 entry
Alex Frid [Tue, 15 Jan 2013 05:11:43 +0000]
ARM: tegra: power: Add clock change delay on LP1 entry

Inserted 2us delay between system and CPU clock changes on LP1
state entry.

Change-Id: I3e8fde0be253a30327c4187de121a0b5e85135f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191110
(cherry picked from commit 50d9ba35309b3d3909559557494a4fb1599b8a4f)
Reviewed-on: http://git-master/r/192660
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Defer switch to 32kHz on LP1 entry
Alex Frid [Tue, 15 Jan 2013 05:20:56 +0000]
ARM: tegra: power: Defer switch to 32kHz on LP1 entry

Deferred switching system clock to 32kHz source after all PLLs are
disabled. There is no need to slow down entry procedure by PLLs
manipulation in 32kHz domain.

Change-Id: I2cfad09f80baa9deda8626ae78cbfcc3326dc7d3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191111
(cherry picked from commit 31615e1677a5e76ca90622cf2756aa09c0e17286)
Reviewed-on: http://git-master/r/192659
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Update PLL configuration in LP1 state
Alex Frid [Fri, 21 Dec 2012 04:34:33 +0000]
ARM: tegra: power: Update PLL configuration in LP1 state

- Put Tegra11 PLLs (PLLM, PLLC, PLLX) in IDDQ mode during LP1 state
- Made sure Tegra30 style PLL lock detect control is not applied to
Tegra11 PLLs (it was overwriting some unrelated Tegra11 bits)
- Added Tegra30 PLL lock detect reset pulse (Bug 1198457)

Change-Id: Ib14a86ffdc24144620f1dc18cf8a0c4c23b6b3e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191097
(cherry picked from commit 2b8d8704295e1aba2328559fa978750505535e49)
Reviewed-on: http://git-master/r/192658
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: power: Don't enable PLLA in LP1 reset exit
Alex Frid [Sun, 13 Jan 2013 00:31:40 +0000]
ARM: tegra11: power: Don't enable PLLA in LP1 reset exit

Current code enables PLLA in LP1 reset exit simultaneously with PLLP
that supplies PLLA reference clock - it is not a valid h/w procedure.
Moreover, PLLA state is always restored later in common clock resume
procedure. This allows to completely remove PLLA restoration form the
LP1 reset exit.

Change-Id: I66e3b7575a5a1b975308880f3990a1f8175aaa18
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190883
(cherry picked from commit 13829a080601f7bec802233c35deee33a27bedf0)
Reviewed-on: http://git-master/r/192657
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Fix SCLK input mux
Alex Frid [Thu, 17 Jan 2013 02:40:11 +0000]
ARM: tegra11: clock: Fix SCLK input mux

Replaced secondary divider PLLP_OUT3 in system clock input mux
definition with main PLLP output to match h/w.

Change-Id: Icdf2de2bf79665bccbe9e68d12386e0b9738960f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191893
(cherry picked from commit c26c8139a29d4fc892deb5c4487486b43e7fac1f)
Reviewed-on: http://git-master/r/192656
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Update PLLD/D2 594MHz rate table
Alex Frid [Thu, 17 Jan 2013 04:38:08 +0000]
ARM: tegra11: clock: Update PLLD/D2 594MHz rate table

Bug 1170010

Change-Id: Ib8a72143c16b136676d1a12d22c0563a838f318c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191894
(cherry picked from commit 2ff7900ba6ba47770708b8da61c96ab6af0dba8c)
Reviewed-on: http://git-master/r/192655
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: dvfs: Update dispaly, sdmmc1,3 dvfs tables
Alex Frid [Thu, 17 Jan 2013 01:55:34 +0000]
ARM: tegra11: dvfs: Update dispaly, sdmmc1,3 dvfs tables

Bug 1161126

Change-Id: I4e8e9f75d8055ef23afcd55e5f75ea1dad50056b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191850
(cherry picked from commit c248f36c86ae54c33ad6e7e15817c3d4cce443a3)
Reviewed-on: http://git-master/r/192654
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Update DSI dvfs table
Alex Frid [Thu, 10 Jan 2013 06:40:28 +0000]
ARM: tegra11: dvfs: Update DSI dvfs table

Bug 1161126

Change-Id: Iff8422a46784beccdaa7a3a22ec72547aa3fbeab
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190211
(cherry picked from commit 704309d5b12ae480378f67d957744a7e90db05e2)
Reviewed-on: http://git-master/r/192653
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: baseband: load host driver by default
Steve Lin [Wed, 9 Jan 2013 23:51:19 +0000]
arm: tegra: baseband: load host driver by default

This is to avoid first enumeration failure by sync with the modem
cold boot gpio. The modem capability will be overwritten after the
first enumeration according to the PID. the driver already handle
the race condition of load_host from user space.

Bug 1197235

Change-Id: I39f3dae118ab0014b4a833b041390cd00e1fdc01
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/190107
(cherry picked from commit a9dbed2975a161596b34a79f27b161e82952aff7)
Reviewed-on: http://git-master/r/191018
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Set xusb pll pad iddq by default
Hunk Lin [Mon, 17 Dec 2012 12:24:11 +0000]
ARM: tegra11: clock: Set xusb pll pad iddq by default

For the boards which don't use PLLE, set xusb pll pad override and iddq for
power saving. The override and iddq will be clear after PLLE is enabled.

Bug 1054317

Change-Id: Ic2da1311058f1033300557f6b0457e940547579e
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/167749
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoinput: misc: cm3217 light sensor driver
Erik Lilliebjerg [Thu, 10 Jan 2013 17:32:42 +0000]
input: misc: cm3217 light sensor driver

Ambient light sensor driver that reports actual lux.

Bug 1167421

Change-Id: Ieda1185a5f33d1df1f03f4a591c2d6398d91ecd4
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/190342
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra: move common edp cdev init to edp code
Diwakar Tundlam [Fri, 11 Jan 2013 23:27:43 +0000]
arm: tegra: move common edp cdev init to edp code

Moved repetitive platform initalization of edp features to common
areas in preparation for handling these cdevs from soc_therm.

Bug 1200075

Change-Id: I8f7fe45d8f0797c72272e5ee1db3707493ec90a5
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/190765
(cherry picked from commit f36a20dd1bce7314a97f48213f2180b0a7440a97)
Reviewed-on: http://git-master/r/192538
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: soctherm: Clean up clock and intrrupts programming
Diwakar Tundlam [Mon, 7 Jan 2013 23:43:37 +0000]
arm: tegra: soctherm: Clean up clock and intrrupts programming

Bug 1200075
Bug 1206311

Change-Id: I116a7efb85b96cf7a47f569d1f3b406c6fb90ce9
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/189398
(cherry picked from commit 7cf3f80a6086161f967dc76085dc57d82349b513)
Reviewed-on: http://git-master/r/192499
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: clock: fix Coverity Null dereference issues
Deepak Nibade [Mon, 21 Jan 2013 11:26:51 +0000]
arm: tegra: clock: fix Coverity Null dereference issues

Coverity id : 22150
Coverity id : 22151
Coverity id : 22171
Coverity id : 22172

Bug 1046331

Change-Id: I0cf22aac7387fa98a4511cb8e10da48adf662e43
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/192822
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra11x: Fix BOND_OUT_L access
Antti P Miettinen [Fri, 18 Jan 2013 13:20:28 +0000]
ARM: tegra11x: Fix BOND_OUT_L access

Fix BOND_OUT_L register access to use the right offset.

Change-Id: I0ccc2adc6aaef7e542436e2c4d65994c59a5a2d3
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/192407
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: defconfig: select max98090 codec
Ravindra Lokhande [Fri, 18 Jan 2013 14:41:05 +0000]
ARM: tegra: defconfig: select max98090 codec

Change-Id: I82161758693ebd46254f49d141b8cadb59a104ca
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/192417
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra14x: Save & restore coresight debug state
Seshendra Gadagottu [Sat, 19 Jan 2013 01:14:41 +0000]
ARM: tegra14x: Save & restore coresight debug state

This preserves debug setup across power gating/ungating sequence.

Change-Id: Ibdecfa3ace740fd7246883090228d3d95501e2f7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/192575
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agodrivers: misc: nct: fix integer overflow in temperature set/get
Lucas Dai [Tue, 15 Jan 2013 08:40:25 +0000]
drivers: misc: nct: fix integer overflow in temperature set/get

change temperature type size from s8 to s16 to support
wider measurement range of −64C to +191C in extended mode

Bug 1217620

Change-Id: I2163d6a0752de7982cf48b987b871e1596f1ee54
Signed-off-by: Lucas Dai <lucasd@nvidia.com>
Reviewed-on: http://git-master/r/190948
(cherry picked from commit f79ce6a5504472b16a5bd159b420da40b6039881)
Reviewed-on: http://git-master/r/192340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agochromeos: Enable PLATFORM_ENABLE_IOMMU
Andrew Chew [Fri, 18 Jan 2013 00:11:38 +0000]
chromeos: Enable PLATFORM_ENABLE_IOMMU

Also renormalized other config options with defaults.

Change-Id: I8fbd1280075f6583b3477fea7d63848e31e06385
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-on: http://git-master/r/192214
Reviewed-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoaudio: update Eq and Volume Profiles.
Vinod Subbarayalu [Wed, 2 Jan 2013 00:06:50 +0000]
audio: update Eq and Volume Profiles.

Change-Id: I27cd72389b01a4436a29f4ee0679281e1f7f2736
Signed-off-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>
(cherry picked from commit cfc618ff6e34279d7126f53276123e7cb07362c6)
Reviewed-on: http://git-master/r/191392
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoarm: tegra: baseband: add EDP support
Neil Patel [Fri, 2 Nov 2012 21:31:29 +0000]
arm: tegra: baseband: add EDP support

Adds support for two different types of EDP clients:
 - edp_modem_boot which will be used when executing the flashless boot sequence
 - edp_modem which will be used when the modem is running the app firmware and
   can be configured through sysfs

Bug 1045672

Change-Id: I1089b3fa3e3725a1cd60d7e475c4fb176e9d77c2
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/191016
(cherry picked from commit 2bf573e13e4ceaa13235241e651dd47890f5a9fe)
Reviewed-on: http://git-master/r/160986
Reviewed-by: Harshada Kale <hkale@nvidia.com>
Tested-by: Harshada Kale <hkale@nvidia.com>

5 years agoARM: tegra14: Enable RAM repair based on fuse bits
Seshendra Gadagottu [Wed, 16 Jan 2013 21:55:30 +0000]
ARM: tegra14: Enable RAM repair based on fuse bits

Check fuse bits spare_10 and spare_11 decide to do RAM repair or not.

Bug 1211371

Change-Id: Ibb572235749753dd52c5202df956b5e4a5465a81
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/191786
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: mm: adding a check for slab objects in flush_dcache_page
Vishal Singh [Thu, 4 Aug 2011 06:29:57 +0000]
ARM: mm: adding a check for slab objects in flush_dcache_page

A page struct obtained via virt_to_page from a slab object may be passed to
the flush_dcache_page function. However, slab allocation is a kernel feature
(can only be done in kernel space) and thus slab objects are never mapped into
user space. However, slab allocators may use the mapping field for their own
purposes and as a result mapping may not be NULL although the page is not
mapped. For this purpose there is a BUG_ON inside page_mapping() to check for
slab objects. So, using NULL for this special case and avoiding calling
page_mapping() on slab objects to avoid the BUG_ON.

Bug 845618.
Bug 1154527.

Reviewed-on: http://git-master/r/45000
(cherry picked from commit 10476ddb84f04bc6c37f8d9ecc15849178a59801)

Reviewed-on: http://git-master/r/189451
(cherry picked from commit 77bfc049878e8c69a36f82a46e32816a72e93214)

Change-Id: If728399cdc6b82be55e4b09f20149e03e196a056
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/190573
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agotegra: efs: m2601: Add EFS driver support for M2601
Ashutosh Patel [Thu, 17 Jan 2013 06:26:18 +0000]
tegra: efs: m2601: Add EFS driver support for M2601

Changes:

- Added EFS driver support for M2601 board

bug 1049391

Change-Id: I0637727136c88480203f9a6d3b437da7215630c1
Signed-off-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-on: http://git-master/r/190267
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarch: arm: configs: t11x: enable CONFIG_SENSORS_MAX44005
Sri Krishna chowdary [Fri, 18 Jan 2013 13:01:54 +0000]
arch: arm: configs: t11x: enable CONFIG_SENSORS_MAX44005

Enable MAX44005 ALS/RGB/TEMP/PROX/IR sensor for ceres

Bug 1190013

Change-Id: I5fcd1aa02ac567c32bd30543ef1ac01fa5d99059
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/188291
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>