5 years agoRevert "clocksource: tegra210: use old timers"
Antti P Miettinen [Wed, 21 May 2014 08:46:31 +0000]
Revert "clocksource: tegra210: use old timers"

This reverts commit b393ed321ddec72fe41796801493377d4e5faf40.

Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Change-Id: I73d7f8b84c17583c947d2e72e9c6e03d3bda0a91
Reviewed-on: http://git-master/r/414720
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>

5 years agodrivers: platform: tegra: camera: shutdown event
Charlie Huang [Fri, 16 May 2014 23:05:04 +0000]
drivers: platform: tegra: camera: shutdown event

implement shutdown/suspend/resume functions to avoid i2c failures.
add atomic cam_ref to prevent the conflict scenario of system
shutdown but the user space still atempt to access the driver.

bug 1503230

Change-Id: I3fe58b49c1391dcc312f096c307a0849b829689a
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/411093
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agogpu: nvgpu: Add gm20b fecs/gpccs bootloader support
Terje Bergstrom [Thu, 22 May 2014 06:53:51 +0000]
gpu: nvgpu: Add gm20b fecs/gpccs bootloader support

Add support for booting FECS and GPCCS via faster bootloader method.
We leave this disabled until the bootloader binaries are checked in.

Change-Id: I39df5d116f7a33486407518c743638b01923970d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/413005

5 years agogpu: nvgpu: Turn off scaling when not powered
Santosh Katvate [Thu, 15 May 2014 19:39:51 +0000]
gpu: nvgpu: Turn off scaling when not powered

This far the scaling has been disabled only when we suspend the
system and therefore we unnecessarily keep gpu workers running even
if the gpu itself would be railgated. This is not proper behaviour
and it causes a race in suspend sequence.

This patch reorders scaling disable to happen always when we turn off
the GPU.

Bug 200004860

Change-Id: Ief0bfd89378d5a7ced26c3ef29094dd5c378b01a
Signed-off-by: Santosh Katvate <skatvate@nvidia.com>
Reviewed-on: http://git-master/r/410443
(cherry picked from commit bcae65bea24be2a1e0abe42522d99ba70c94cbe2)
Reviewed-on: http://git-master/r/413145
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: dsi: call usleep_range in DSI_DLY_MS
Roger Hsieh [Mon, 5 May 2014 06:29:52 +0000]
video: tegra: dsi: call usleep_range in DSI_DLY_MS

DSI_DLY_MS calling mdelay holds cpu for ms level then causes
noticeable latency. Replaced by usleep_range for better task
scheduling and responsiveness.

Bug 200001850

Change-Id: Ib3dcb99fefcfd997f71deadf000029bf63362dd2
Reviewed-on: http://git-master/r/404996
(cherry picked from commit 61934c65cea4d118570c740cb7a839287795b491)
Signed-off-by: Roger Hsieh <rhsieh@nvidia.com>
Reviewed-on: http://git-master/r/411876
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm64: tegra: pm: use ioremap_wc
Rich Wiley [Fri, 23 May 2014 00:45:33 +0000]
arm64: tegra: pm: use ioremap_wc

ioremap_wc maps to what ARMv8 calls Normal_NC and ioremap maps to
Device_nGnRnE.
Device_nGnRnE requires:
1. Reads do not hit in the cache.
2. Writes are written out to the bus before a memory barrier executes
3. No speculative reads
4. No combining reads or writes into a single transaction
5. No reordering reads or writes
6. No early acknowledgement from the bus. Instead wait for the device
on the bus to send an acknowledgement
Normal_NC requires:
1. Reads to not hit in the cache
2. Writes are written out to the bus before a memory barrier executes
The only requirement for the LP0 exit code is that it is written out to
memory instead of being held in cache. So, use ioremap_wc.
Bug 1512416
Change-Id: I4ab33621daa2207490ca17196d2f8805248e76ef
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/407803
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agopstore: use writecombine instead of noncached
Alex Van Brunt [Fri, 9 May 2014 23:04:46 +0000]
pstore: use writecombine instead of noncached

pgprot_noncached implies that memory accesses cannot be cached and that
reads and writes cannot be combined. pgprot_writecombine implies that
accesses are non-cached but that reads and writes can be combined.
Because pstore is memory backed, the fact that reads and writes are
combined does not affect the behavior.

Bug 1512416

Change-Id: I9d1d651b146789d2ae8846ccddee72043b6198ee
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/407802
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Richard Wiley <rwiley@nvidia.com>
Tested-by: Richard Wiley <rwiley@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agotegra: nct: Use wc instead of nocache memory
Rich Wiley [Fri, 23 May 2014 00:42:02 +0000]
tegra: nct: Use wc instead of nocache memory

Write combine memory maps to what ARMv8 calls Normal_NC. nocache maps
to Device_nGnRnE.
Device_nGnRnE requires:
1. Reads do not hit in the cache.
2. Writes are written out to the bus before a memory barrier executes
3. No speculative reads
4. No combining reads or writes into a single transaction
5. No reordering reads or writes
6. No early acknowledgement from the bus. Instead wait for the device
on the bus to send an acknowledgement
Normal_NC requires:
1. Reads to not hit in the cache
2. Writes are written out to the bus before a memory barrier executes
Because the NCT lives in DRAM, other than 1 and 2, NCT does not need
any of the restrictions of Device_nGnRnE. Instead it should use
Normal_NC.
Bug 1512416
Change-Id: Id2fbac699c2a7f224a8f1c60d3fc2d41b7d80e35
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/407801
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Use clean for Denver
Rich Wiley [Wed, 21 May 2014 17:29:42 +0000]
video: tegra: nvmap: Use clean for Denver

On ARMv7 using a full flush was necessary for two reasons. One,
the zeroed pages needed to be written to DRAM or the PoU so that
HW devices could not read the memory out from under the CPU's
cache. And two, the cache lines needed to be invalidated so that
if userspace immediately mapped the memory as something other
than cached they would not get invalid hits in the cache.

However, for denver, the risk of invalid hits in the cache due
to lines being left as valid is no more. Thus we only need to
ensure the zeroed memory is past the PoU. For this a clean will
suffice. Also on denver invalidates are extremely expensive.
Therefor removing any invalidates that are not necessary will
greatly help performance.

Change-Id: Ie952f5db62e1312562ef2ef9c61ba3e37e3efc76
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/407792
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm64: mm: Implement cache clean operation
Alex Waterman [Fri, 9 May 2014 18:39:47 +0000]
arm64: mm: Implement cache clean operation

Cache cleaning is necessary for Denver. To do a cache flush,
which includes an invalidate, when unnecessary is crushingly
bad for Denver.

Change-Id: Ia760ea478d77e7ad18e3f282cec942b24bc0d54c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/407791
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: dc: use ioremap_wc
Alex Van Brunt [Fri, 9 May 2014 23:17:59 +0000]
video: tegra: dc: use ioremap_wc

ioremap_wc maps to what ARMv8 calls Normal_NC and ioremap maps to
Device_nGnRnE.

Device_nGnRnE requires:
1. Reads do not hit in the cache.
2. Writes are written out to the bus before a memory barrier executes
3. No speculative reads
4. No combining reads or writes into a single transaction
5. No reordering reads or writes
6. No early acknowledgement from the bus. Instead wait for the device
   on the bus to send an acknowledgement

Normal_NC requires:
1. Reads to not hit in the cache
2. Writes are written out to the bus before a memory barrier executes
The only requirement for the framebuffer is that it is written out to
memory instead of being held in cache. So, use ioremap_wc.

Bug 1512416

Change-Id: I86230c8dc04a94ab20129cc65115f30d18bff20f
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/407805
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: increase set/ways threshold for denver
Alex Waterman [Fri, 9 May 2014 01:49:37 +0000]
video: tegra: nvmap: increase set/ways threshold for denver

Doing full invalidates (and similarly flushes) causes everything
to be invalidated including the MTS translations. Thus all
translation must be redone/revalidated which is a very expensive
operation.

However, it still makes sense to do full invalidates and flushes
is the buffers are big enough. Thus we just increase the threshold
to 16 MB instead of the previous 2 MB.

Change-Id: I3648dd820051535cbc5e9390a0194b4e2041cff0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/407216
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: tegra: use ioremap_wc for the framebuffer
Rich Wiley [Fri, 23 May 2014 18:24:57 +0000]
arm: tegra: use ioremap_wc for the framebuffer

ioremap_wc maps to what ARMv8 calls Normal_NC and ioremap maps to
Device_nGnRnE.
Device_nGnRnE requires:
1. Reads do not hit in the cache.
2. Writes are written out to the bus before a memory barrier executes
3. No speculative reads
4. No combining reads or writes into a single transaction
5. No reordering reads or writes
6. No early acknowledgement from the bus. Instead wait for the device
on the bus to send an acknowledgement
Normal_NC requires:
1. Reads to not hit in the cache
2. Writes are written out to the bus before a memory barrier executes
The only requirement for the framebuffer is that it is written out to
memory instead of being held in cache. So, use ioremap_wc.
Bug 1512416
Change-Id: Ie655ff2c5c0880a59df61307830643f534f189c7
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/412777
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoRevert "mmc: sdhci: Enable pm domain for eMMC and SD"
Matt Pedro [Fri, 23 May 2014 19:01:56 +0000]
Revert "mmc: sdhci: Enable pm domain for eMMC and SD"

This reverts commit 99f9d6aff97a58b642a29d4e93af056c49cba0ec.

Change-Id: I5e8b1149b94269825cce6bab9570161d0f857dec
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/414234
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: dts: remove low-power-mode entries
shravanid [Fri, 23 May 2014 14:50:24 +0000]
arm: dts: remove low-power-mode entries

remove low-power-mode entries in the dtsi files
for t124-platforms as lpmd bit has been
deprecated in t124

Change-Id: I72cf783d14a6e83832c04fe1fcac48ac2919e228
Signed-off-by: shravanid <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/414165
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: move pinmux dt node before gpio mode
Laxman Dewangan [Wed, 21 May 2014 09:25:27 +0000]
ARM: tegra: move pinmux dt node before gpio mode

Move the pimx DT node before gpio node to make sure that
pinmux get registered before the gpio.

Change-Id: I55d5a5c1a1570c16d8332ba224e0ed9a1f7c257c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/412630
GVS: Gerrit_Virtual_Submit

5 years agogpio: tegra: add gpio range after gpio registration
Laxman Dewangan [Wed, 21 May 2014 09:24:20 +0000]
gpio: tegra: add gpio range after gpio registration

Add gpio range for pins after gpio registartion and getting
the gpio base of the Tegra.

Change-Id: I71033ab0f4b9b24b733d453adf77cc43d2aedff1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/412629
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: tegra: add support to pass gpio base for tegra pincontrol
Laxman Dewangan [Wed, 21 May 2014 09:20:07 +0000]
pinctrl: tegra: add support to pass gpio base for tegra pincontrol

Add support to pass the gpiobase for tegra gpio and add tegra pins
on that gpio range.

Change-Id: I024efd49bf9209399210f8ab6881fae7d37ccd52
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/412628
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: remove low power mode configuration for drive
Laxman Dewangan [Fri, 23 May 2014 11:23:49 +0000]
ARM: tegra: remove low power mode configuration for drive

Low power mode is not supported on T124 and hence removing this
configuration from DT node of pinmix for Norrin.

Change-Id: I0f8de8bcd7b39af4be36b60bced45cecf7082cdc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/414121
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: tegra: fix indexing of pinmux group
Laxman Dewangan [Fri, 23 May 2014 11:21:11 +0000]
pinctrl: tegra: fix indexing of pinmux group

Pinmux group index was wrong accessed when setting the
default configuration of the driver strength.

Fixing this.

Change-Id: I5bc722671ce13e451076c7e5312d173368a29393
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/414120
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoRevert "media: ad5823: Back to default position on exit"
Frank Chen [Thu, 22 May 2014 21:04:07 +0000]
Revert "media: ad5823: Back to default position on exit"

Revert this change since it caused camera close KPI
regression.

Bug 200000851

This reverts commit 14629c6a2221973c768678b8f6f7e42be959c4be.

Change-Id: I0354605311124b06db88dd039a58ad6e04585f72
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/413393
Reviewed-by: Joshua Widen <jwiden@nvidia.com>
Reviewed-by: Gary Zhang <garyz@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shiva Dubey <sdubey@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra: dvfs: Defer calibration on force value
Alex Frid [Thu, 24 Apr 2014 00:14:00 +0000]
ARM: tegra: dvfs: Defer calibration on force value

Deferred DFLL calibration if last sent voltage is at the initially
forced request output level. It is needed to avoid false interpretation
of high voltage when power management micro-controller re-sends DFLL
request underneath CLDVFS driver running on CPU.

Bug 1492902

Change-Id: I0757469ff432818d1aadb616accba01136345257
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402659
(cherry picked from commit b5adc8efaad051a87df67fa701076bd12ff2c9aa)
Reviewed-on: http://git-master/r/413379
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra13: dvfs: Update CPU DVFS table to P4v8
Alex Frid [Thu, 17 Apr 2014 05:04:55 +0000]
ARM: tegra13: dvfs: Update CPU DVFS table to P4v8

Bug 1492902
Bug 1442659

Change-Id: Id9e6114fa05e38d21f59fd34e1804abdb456f193
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402658
(cherry picked from commit 48293ae83aa61c1b0633977729b23e0379bf16b5)
Reviewed-on: http://git-master/r/397533
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra13: dvfs: Add CPU Vmin data
Alex Frid [Wed, 16 Apr 2014 02:31:20 +0000]
ARM: tegra13: dvfs: Add CPU Vmin data

Added CVB coefficients to account CPU Vmin dependency on speedo and
temperature. Implemented CVB equations to calculate Vmin thermal
profile.

Bug 1492902
Bug 1442659

Change-Id: Ib039df6807880d1714550bd6b770d2c4e46e8ac0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402657
(cherry picked from commit 0c7447ce5938d8d560eae91a58aaf52f82fe2fe1)
Reviewed-on: http://git-master/r/397532
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra13: dvfs: Set CPU DFLL tuning parameters
Alex Frid [Wed, 9 Apr 2014 07:05:27 +0000]
ARM: tegra13: dvfs: Set CPU DFLL tuning parameters

On Tegra13 A02 silicon set CPU DFLL tuning parameters as a function
of chip speed.

Bug 1492902
Bug 1442659

Change-Id: I03a5a419c60ffa86a360c58222b93279f25e3145
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/402656
(cherry picked from commit c8b72a7db9388f70864852f4a2fea75a47d92116)
Reviewed-on: http://git-master/r/394399
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoclock: tegra21: Use PLL set rate during init
Alex Frid [Tue, 20 May 2014 21:59:22 +0000]
clock: tegra21: Use PLL set rate during init

When setting initial dividers for disabled PLL call set rate operation
instead of direct dividers calculation.

Bug 1413190

Change-Id: Idcc88f9c2246c6f3a7998c47b541b288b180860a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/412869
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agoclock: tegra21: Make PLLCX init procedure generic
Alex Frid [Tue, 20 May 2014 18:54:35 +0000]
clock: tegra21: Make PLLCX init procedure generic

Since PLLCX initialization procedure can be (and, in fact, is) applied
to other PLLs, made it generic with the appropriate name changes.

Bug 1413190

Change-Id: Iea4be5483232bec85f834ba674164bad963abb80
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/412868
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agoclock: tegra21: Re-implement Tegra21 PLLD support
Alex Frid [Tue, 20 May 2014 00:23:28 +0000]
clock: tegra21: Re-implement Tegra21 PLLD support

Re-defined PLLD object, and re-implemented PLLD operations to match
Tegra21 specification including SDM fractional feedback divider.

Bug 1413190

Change-Id: Ia8ee74a945228993163ffbc7b019938b2d7fd625
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/412867
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agoclock: tegra21: Update Tegra21 PLLD2/DP support
Alex Frid [Tue, 20 May 2014 00:36:41 +0000]
clock: tegra21: Update Tegra21 PLLD2/DP support

Renamed PLLD2/DP frequency tables for consistency with other PLLs.
Removed obsolete PLLD2 resume operations.

Bug 1413190

Change-Id: I2be6f6b02a9de5ac7799215d7440aee6412a0f4a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/412866
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agoclock: tegra21: Update mux host1x clock
Hoang Pham [Thu, 22 May 2014 18:40:57 +0000]
clock: tegra21: Update mux host1x clock

Change-Id: Ida4d28c2cf6f96380e16a571b0e7897276599d23
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/413356
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra13: edp: package based EDP safety caps
Diwakar Tundlam [Tue, 13 May 2014 22:34:51 +0000]
arm: tegra13: edp: package based EDP safety caps

Implemented package based EDP safety caps.
Updated dynamic parameters for T132 specific core offlining.
Adjusted leakage parameter scaling to avoid overflow in calculation.

Bug 1434482

Change-Id: I2d783e15e238e60cce4b97661749abcd7a54a11b
Reviewed-on: http://git-master/r/409052
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/406127

5 years agoPM QoS: Fix pmqos notifiers in pm_qos_enabled_set
Sai Gurrappadi [Thu, 22 May 2014 22:06:06 +0000]
PM QoS: Fix pmqos notifiers in pm_qos_enabled_set

Send out the notifiers if the enabled flag has been changed. This will
ensure that the notifier fires in all cases.

Bug 1516219

Change-Id: Ie97422f61a9ad56f0ce194a99ce69193d429eadc
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/413435
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM64: tegra: mc: Add intr info for t210
Alex Waterman [Tue, 29 Apr 2014 18:11:03 +0000]
ARM64: tegra: mc: Add intr info for t210

Add the new interrupt for T210's MC.

Change-Id: Ic4c0ff704025e9ba043d9322abeb8e5a3005bd46
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/403065
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agofixup! net: ipv6: Add IPv6 support to the ping socket.
Dan Willemsen [Thu, 15 May 2014 03:34:32 +0000]
fixup! net: ipv6: Add IPv6 support to the ping socket.

During the integration of this change to 3.10, this error check was
commented out.

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I7e2fa114b0efbe58134f7acc60ec4d18b1bbee0e
Reviewed-on: http://git-master/r/409994
Reviewed-on: http://git-master/r/413586
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra: bonaire: removing this platform
Alex Waterman [Thu, 22 May 2014 01:14:39 +0000]
ARM: tegra: bonaire: removing this platform

This platform has long since been EOL'ed.

Change-Id: I23f08bce1696248823c2bd71407387cd9b72838a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/412896
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: dc: Add HDCP ioctl for recv capable
Lael Jones [Mon, 19 May 2014 22:18:43 +0000]
video: tegra: dc: Add HDCP ioctl for recv capable

Change-Id: I76f6d87b16d139de9f3a8178a75b8b0f896ad406
Signed-off-by: Lael Jones <lajones@nvidia.com>
Reviewed-on: http://git-master/r/412687
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: initialize cursor registers
Jon Mayo [Fri, 9 May 2014 18:07:17 +0000]
video: tegra: dc: initialize cursor registers

Cursor registers have no default state. Initialize to useful defaults.

Bug 1486452
Bug 200006001

Change-Id: Iaf07bdd2c8d40ef1bae881da68a809d335a0377f
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/407682
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dc: remove low latency cursor support
Jon Mayo [Tue, 29 Apr 2014 19:47:21 +0000]
video: tegra: dc: remove low latency cursor support

There is no difference in latency.

Bug 1333484

Change-Id: I6abbad50b4dea3e7041ca63c60210b166f5e1036
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/413373
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: fix panic from tegra_powergate_debugfs_init
Nitin Kumbhar [Fri, 23 May 2014 11:57:37 +0000]
arm: tegra: fix panic from tegra_powergate_debugfs_init

Fix kernel panic seen during kernel boot up.

[    0.153216] Unable to handle kernel NULL pointer dereference at virtual
address 00000008
[    0.153219] pgd = ffffffc00007d000
[    0.153222] [00000008] *pgd=00000000c7408003, *pmd=00000000c7409003,
*pte=00e0000050041407
[    0.153227] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[    0.153230] Modules linked in:
[    0.153233] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W
3.10.33-g670a12f #13
[    0.153238] task: ffffffc0474ab2c0 ti: ffffffc0474ac000 task.ti:
ffffffc0474ac000
[    0.153242] PC is at tegra_powergate_debugfs_init+0xcc/0x118
[    0.153245] LR is at tegra_powergate_debugfs_init+0x4c/0x118
[    0.153248] pc : [<ffffffc00083af30>] lr : [<ffffffc00083aeb0>] pstate:
20000305

Change-Id: Ic3a4a0725eaf2f264c839d08b289c6f4f5d2d4fb
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/414125
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agommc: sdhci: Enable pm domain for eMMC and SD
venkatajagadish [Tue, 20 May 2014 08:57:26 +0000]
mmc: sdhci: Enable pm domain for eMMC and SD

Bug 1384366

Change-Id: I0de26cf3387a465bbc05454fb174998012bb25d7
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/361888
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM64: tegra210: Add support for RAID
R Raj Kumar [Mon, 19 May 2014 09:35:49 +0000]
ARM64: tegra210: Add support for RAID

Added RAID support in T210 platform for supporting
dual eMMC

Bug 1501458

Change-Id: I254dc5fefdbf26feddb7c468391005f214002f8e
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/411403
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agodrivers: video: tegra: fix build warnings
Sumit Singh [Wed, 14 May 2014 17:28:36 +0000]
drivers: video: tegra: fix build warnings

- Makefile: enable Werror flag to treat compile time warnings as errors
- fb.c: rectify invalid pointer assignment

bug 1211919

Change-Id: I920e4f8052573293dda86191915fba0b5298a112
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/409671
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agovideo: tegra: nvmap: Do not set DMA addr on carveout
Terje Bergstrom [Fri, 9 May 2014 12:13:08 +0000]
video: tegra: nvmap: Do not set DMA addr on carveout

Do not set DMA address on allocations from carveout.

Bug 1500983

Change-Id: Ic9620d09a2084104b7ca246a987252769b94650e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/412107
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Tested-by: Sami Kiminki <skiminki@nvidia.com>

5 years agovideo: tegra: host: Fix postponed timeout
Arto Merilainen [Thu, 22 May 2014 08:57:21 +0000]
video: tegra: host: Fix postponed timeout

Postponed timeout is triggered if the submit currently waits for
a syncpoint that is not related to the current job.

Due to bad cbstat check we usually treated also other cbstat
conditions as waits and therefore triggered postponed wait too
easily. This patch fixes the check.

Change-Id: Ia87e4f8600d3000ef02a7a0b09acfc2dedfb4034
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/413139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agosync: Dump fence information on timeout
Arto Merilainen [Thu, 22 May 2014 09:00:04 +0000]
sync: Dump fence information on timeout

Currently we print only the fence memory address if the fence
times out. This is not enough for debugging *why* the fence timed
out.

This patch modifies timeout routine so that we print the syncpoints
that relate to the current fence.

Bug 200006324

Change-Id: Iae103d4a4ba65584333e46de72240190699a0cef
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/413138
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoregulator: as3722: add enable_time for regulators
Bibek Basu [Wed, 14 May 2014 09:21:27 +0000]
regulator: as3722: add enable_time for regulators

Add enable time of sd2/3,sd4,sd5 regulator

Bug 1481642

Change-Id: I73e8ff5c34e9db9f13a181e01a268c740ccfb410
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/409334
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm64: tegra: enable Werror flag
Sumit Singh [Wed, 21 May 2014 09:48:10 +0000]
arm64: tegra: enable Werror flag

Enable Werror flag to treat compilation warnings as error

Bug 1211919

Change-Id: I8db3910386cf4693c679dc70d013e01873822a23
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/412573
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm64: tegra: fix build warning for hotplug driver
Sumit Singh [Mon, 19 May 2014 14:15:32 +0000]
arm64: tegra: fix build warning for hotplug driver

-tegra_suspend_in_progress(): function declaration
 isn't a prototype
-cast from pointer to integer of different size

Bug 1211919

Change-Id: I31124a376e3cb034ba24252f8e3ee437c42c4fb9
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/411539
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm64: tegra: fix build warnings
Sumit Singh [Mon, 19 May 2014 13:36:39 +0000]
arm64: tegra: fix build warnings

Following functions defined but not used:
-e1735_suspend_dfll_bypass
-e1735_resume_dfll_bypass
-e1767_configure_dvfs_pwm_tristate
-e1767_suspend_dfll_bypass
-e1767_resume_dfll_bypass

Bug 1211919

Change-Id: I2a966c3b45fba4d5ad9cd2cd75a5e8f922309f82
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/411527
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: tegra: pm375: disable usb device mode
Preetham Chandru R [Tue, 15 Apr 2014 10:03:45 +0000]
ARM: tegra: pm375: disable usb device mode

Disable usb device mode for pm375 rev A-D

Bug 1495952

Change-Id: I553d3c05f9a8421ff4900999d9d6e5c21dc5e596
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/404679
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agotegra: vcm30t124: Add defconfig and DT for VM
Nitin Sehgal [Wed, 23 Apr 2014 17:13:07 +0000]
tegra: vcm30t124: Add defconfig and DT for VM

This change add defconfig and device tree dupport for
vcm30t124 based linux virtual instances.

bug 1503589

Change-Id: Iad3c8fcb80ff2fbdfd499a5dc1432b2ed6645eb5
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Signed-off-by: Vlad Buzov <vbuzov@nvidia.com>
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/400444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: tegra12: config: Disable modem configs
Preetham Chandru R [Thu, 15 May 2014 09:37:25 +0000]
ARM: tegra12: config: Disable modem configs

Bug 200004850

Change-Id: I4b3131addcf09cc044d2305f733272ab23f37392
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/410159
(cherry picked from commit efc8e7d4a20deca5d6a38c907587d8fece29445f)
Reviewed-on: http://git-master/r/411863
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agogpu: nvgpu: Disable pm runtime on shutdown
Arto Merilainen [Tue, 20 May 2014 09:47:20 +0000]
gpu: nvgpu: Disable pm runtime on shutdown

In some cases the gpu has still work pending while the device is
being suspended. This patch forces pm runtime to be disabled for
the device to avoid powering up the gpu unnecessarily.

Bug 1515437

Change-Id: I4b57d72eb34e794f0457d7a074d26c9d096a13b3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/411968
(cherry picked from commit ef6e80d5cd9268848a3dd82664577f17f4d9ab71)
Reviewed-on: http://git-master/r/413240
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agortc: max77620: devm_* allocated resource need not to free expliclty
Laxman Dewangan [Thu, 22 May 2014 11:26:33 +0000]
rtc: max77620: devm_* allocated resource need not to free expliclty

Do not free the devm_* based allocation/registration.

Change-Id: Idad997b8a212871f6fa4c9927d03861ec8a28f50
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/413188
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>

5 years agortc: max77620: implement suspend/resume
Laxman Dewangan [Thu, 22 May 2014 11:22:08 +0000]
rtc: max77620: implement suspend/resume

Implement suspend/resume and prints alarm time on suspend and
wakeup time on resume for better debugging.

Change-Id: I320c124b33b00b9ecf80b0c5ed839a63472bf4de
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/413187
Reviewed-by: Automatic_Commit_Validation_User

5 years agortc: max77620: use module_platform_driver() macro
Laxman Dewangan [Thu, 22 May 2014 11:15:23 +0000]
rtc: max77620: use module_platform_driver() macro

use module_platform_driver() macro and remove boilerplate code.
Correct copyright and remove of table also as this is not required.

Change-Id: I52ada3de912a1d77abf445732b50d48c74687a32
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/413186
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>

5 years agotegra: enable auto-dvfs on vdd-core related clocks
dmitry pervushin [Tue, 20 May 2014 10:41:01 +0000]
tegra: enable auto-dvfs on vdd-core related clocks

Setting auto_dvfs on clocks that have vdd_core rail shows the correct
vdd_core voltage even if the power rail is "disabled scaling"

Bug 1461662

Change-Id: I584487b6e4f9e566b03574914616c16dc2b8955f
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Reviewed-on: http://git-master/r/411991
Reviewed-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yousuf Aboobaker Sait <yousufa@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agotegra: dvfs: suppress warning on disabled rails
dmitry pervushin [Mon, 12 May 2014 11:51:01 +0000]
tegra: dvfs: suppress warning on disabled rails

In case of disabled scaling on the rail and requested voltage == 0,
dvfs_update_rail should print no warning

Bug 1461662

Change-Id: I0c2c262a68c4ddaeea4700e7676a0b731376b543
Signed-off-by: dmitry pervushin <dpervushin@nvidia.com>
Reviewed-on: http://git-master/r/408196
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: dts: vcm30t124: Enable USH-1 mode for SDMMC3
Seshagir.H [Tue, 13 May 2014 04:28:54 +0000]
arm: dts: vcm30t124: Enable USH-1 mode for SDMMC3

bug 1367536
bug 1454378

Change-Id: Ice3703a24be0e2a668f6ee4c5fb7565a0ceb3b55
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/408195
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: dts: vcm30t124: Enable HS200 mode for SDMMC4
Seshagir.H [Tue, 20 May 2014 09:15:10 +0000]
arm: dts: vcm30t124: Enable HS200 mode for SDMMC4

bug 1367536

Change-Id: I8e66c4080d1f1a4484a64cffdbac548c1798a27c
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/406912
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoARM: tegra: configure UART properly for early prints
Laxman Dewangan [Wed, 21 May 2014 09:54:13 +0000]
ARM: tegra: configure UART properly for early prints

For Tegra124, configure debug UART properly for early prints
to avoid junk data on console due to misconfiguration.

Change-Id: I727a9056793bb2dcff5e2562f05064c9bab897b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/412631
GVS: Gerrit_Virtual_Submit

5 years agotegra: mc: Add missing mc error description
Sami Kiminki [Tue, 20 May 2014 15:15:54 +0000]
tegra: mc: Add missing mc error description

Add MC error description for combination INVALID_SMMU_PAGE +
DECERR_VPR + DECERR_EMEM.

Bug 1500983

Change-Id: I37158c843ff534ab22f9ada0c66ae1d3d76bf650
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/412102
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoplatform: tegra210: no power gating on asim
Chien-Yu Chen [Thu, 15 May 2014 23:50:59 +0000]
platform: tegra210: no power gating on asim

Do not power gating on asim.

bug 1482370

Change-Id: Id02e2ee4d9d74aec92d067ead5d7e79630088aa6
Signed-off-by: Chien-Yu Chen <chichen@nvidia.com>
Reviewed-on: http://git-master/r/411032
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm: tegra: loki: add missing break statement
Deepak Nibade [Thu, 22 May 2014 07:05:55 +0000]
arm: tegra: loki: add missing break statement

Fix Coverity issue of missing break in a switch
Coverity id : 26480

Bug 1416640

Change-Id: Iae74fae2083651f57835ee64ea8664819d297ff0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/411413
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm: tegra: sysedp: 2nd update of AP+DRAM table for T132
Timo Alho [Thu, 22 May 2014 09:08:00 +0000]
arm: tegra: sysedp: 2nd update of AP+DRAM table for T132

Bug 1469388

Change-Id: I1342e6a0cfdde83ee98163a0cc1080e5cf2e564a
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/413157
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: improve nvhost_fence doc
Antoine Chauveau [Thu, 22 May 2014 10:17:28 +0000]
video: tegra: host: improve nvhost_fence doc

Fix typos and better document how the interface can
be used with either raw syncpoints or sync fence fds.

Bug 1356557

Change-Id: Id69053d77c7b10cfd7fc90f4fec3e635765354c4
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: http://git-master/r/413148
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: dts: have 64bit address and size
Min-wuk Lee [Thu, 22 May 2014 07:28:34 +0000]
arm: dts: have 64bit address and size

address-cells and size-cells are set to 2
in parent node, therefore, it needs to have
64-bit address and size values.

Bug 1371533

Change-Id: I81159b4f9bd30ee014d6d49af2eecf3c56902a56
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/400637
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: fuse: added chip revision for T124
Jeetesh Burman [Wed, 14 May 2014 08:45:12 +0000]
ARM: tegra: fuse: added chip revision for T124

Chip revision for T124 was not present in struct chip_revision,
hence T124 chip revision added.

Bug 1486361

Change-Id: Icad37ed895b84bf94e6e868a38e4af1f5c115ee8
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/409312
(cherry picked from commit b76ac1b25e1f31aeeabf3361be4e2782afddb4b2)
Reviewed-on: http://git-master/r/411859
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: dts: remove tegra-panel.dtsi
Min-wuk Lee [Thu, 24 Apr 2014 01:59:42 +0000]
arm: dts: remove tegra-panel.dtsi

tegra-panel.dtsi was added as a common panel dtsi, that
includes all available panels' dtsi, however, considering
DTB size limit, it is necessary to include required
panel dtsi only in target platform dtsi:
If tegra-panel.dtsi is maintained, new panel dtsi will be
included additionally and DTB size may become bulky later.

Bug 1371533

Change-Id: I06017b264dd642a005b653bf017d0ef25c0bb460
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/400614
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: dts: tn8-e1922: display system device tree
Min-wuk Lee [Fri, 18 Apr 2014 06:13:25 +0000]
arm: dts: tn8-e1922: display system device tree

display system device tree for tn8-e1922.

Bug 1371533
Change-Id: I771085af445df5099ab223cc80aedd8f0533420d
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/398105
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: dts: tn8-e1784: display system device tree
Min-wuk Lee [Fri, 18 Apr 2014 05:44:56 +0000]
arm: dts: tn8-e1784: display system device tree

display system device tree for tn8-e1874.

Bug 1371533

Change-Id: I05af5aff192ba0aece26734da39ef91c05d4b734
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/398089
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: dts: tn8-p1761: display system device tree
Min-wuk Lee [Thu, 17 Apr 2014 11:25:38 +0000]
arm: dts: tn8-p1761: display system device tree

display system device tree for tn8-p1761.

Bug 1371533

Change-Id: I136ee3e8f7836abcc5a330459323362a0325244e
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/400598
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agovideo: tegra: dc: vblank short cmd club in DT
Min-wuk Lee [Tue, 13 May 2014 06:49:31 +0000]
video: tegra: dc: vblank short cmd club in DT

With this change, club option of short packet
VBLANK commands can be specified in device
tree.

Bug 1371533

Change-Id: I31bf3e92de253829fddea914ad0a0efa024428dc
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/408650
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: tegra: panel-a-1200-800-8: remove sd code
Min-wuk Lee [Fri, 18 Apr 2014 01:50:51 +0000]
arm: tegra: panel-a-1200-800-8: remove sd code

Current code does not have smartdimmer calibration data
and does not enable smartdimmer, hence, remove redundant
smartdimmer code.

Bug 1371533
Change-Id: I1d78a82c2adcb56a9446eab7a7addf58adef1c29
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/398003
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: tegra: panel-a-1200-800-8: fix active area
Min-wuk Lee [Fri, 18 Apr 2014 01:41:09 +0000]
arm: tegra: panel-a-1200-800-8: fix active area

According to the data-sheet, this panels' active area
is 107[mm](H) X 172[mm](V).

Bug 1371533
Change-Id: I32106ac32c6b2361b916cea76537f97e8485975b
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/398000
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: tegra: tn8-ffd: DT support for display system
Min-wuk Lee [Thu, 17 Apr 2014 08:12:51 +0000]
arm: tegra: tn8-ffd: DT support for display system

This includes board-panel and panel code changes
to support device tree for tn8-ffd's panels, which
are auo wuxga 8" panel and auo wxga 8" one.

Bug 1371533
Change-Id: Iceeae8fd3235344f030814fd38a8759063fce876
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/397580
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agommc: tegra: Add support for HS200 mode
Seshagir.H [Tue, 20 May 2014 09:16:33 +0000]
mmc: tegra: Add support for HS200 mode

- Update coeffs values for 198Mhz t124
- update soc speedo value using function
tegra_soc_speedo_0_value

bug 1367536

Change-Id: I49df96cf72c6737fef538754ccbde06a3efb71f7
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/411954
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agommc: tegra: Ignore err if dvfs overrides are disabled
Pavan Kunapuli [Tue, 13 May 2014 11:22:42 +0000]
mmc: tegra: Ignore err if dvfs overrides are disabled

If dvfs overrides are disabled, continue tuning execution by
treating the dvfs override API return values as expected.

Change-Id: I8d27969029ce7b318d23c227e8dfb19793282fea
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/408784
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agovideo: tegra: nvmap: Consolidate zeroed mem config
Alex Waterman [Mon, 28 Apr 2014 18:27:17 +0000]
video: tegra: nvmap: Consolidate zeroed mem config

Consilidate the NVMAP_FORCE_ZEROED_USER_PAGES config to only
two locations. Both are in nvmap_handle.c and ensure that
the module param zero_memory is enabled and unchangable when
NVMAP_FORCE_ZEROED_USER_PAGES is set.

Change-Id: Ied1c6ffb57b427bb2c7f8e9270ecea6c8bc34ec6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/403038
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Fix build error for cache maint
Alex Waterman [Thu, 24 Apr 2014 23:24:44 +0000]
video: tegra: nvmap: Fix build error for cache maint

When CONFIG_NVMAP_CACHE_MAINT_BY_SET_WAYS is not defined some
code in nvmap's cache flush code references undefined variables.

Change-Id: I0971c56cff7df4bedaea0cca5372774e6c50fc8d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/401114
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: ardbeg: tn8: add tn8 a03 raydium touch
Vincent Chen [Wed, 2 Apr 2014 03:13:54 +0000]
arm: ardbeg: tn8: add tn8 a03 raydium touch

bug 1482112

Change-Id: I794d925eaed88fffa56c98a252b72a713f345684
Signed-off-by: Vincent Chen <zochen@nvidia.com>
Signed-off-by: Robert Collins <rcollins@nvidia.com>
Reviewed-on: http://git-master/r/401083
(cherry picked from commit 089f379cddfcaa60234649f99da29fa5b899f28e)
Reviewed-on: http://git-master/r/404578
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoinput: touchscreen: raydium: update driver to 62.3
Vincent Chen [Wed, 2 Apr 2014 03:13:20 +0000]
input: touchscreen: raydium: update driver to 62.3

62.2 changes:
[1] fix error/warning from checkpatch
[2] add keybit
[3] Device tree support
[4] All the sysfs nodes are moved to 'sys/devices/virtual/misc/touch'
    and also rename the device as 'touch'
[5] Using default path to loading all libraries instead of absolute path
[6] Remove PM suspend/resume operations to prevent from LP0 resume
    failure due to race condition
[7] Touch performance refine (palm, stylus, ......)
[8] fix slowscan issue
[9] Add TLK support
[10] Add TN8 support

62.3 changes:
[1] fix checkpatch error.
[2] improve TN8 stylus performance.
[3] improve TN8 finger performance.
[4] add error code in selftest function.
[5] add TN8 noise hopping function.
[6] add codes for x64 system."

Bug 1446493
Bug 1482112
Bug 1469135
Bug 1468629
Bug 1465587
Bug 1453371
Bug 1437076
Bug 1405258

Change-Id: I633cddb8b65a9c7fe741f6a782d4a4f5fd792c58
Signed-off-by: Vincent Chen <zochen@nvidia.com>
Signed-off-by: Robert Collins <rcollins@nvidia.com>
Reviewed-on: http://git-master/r/401082
(cherry picked from commit 37d7fa65b3f8471e65cbe3ea8ed05419bcdf2342)
Reviewed-on: http://git-master/r/404576
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm64: optimize el0_sync branch prediction
Rohit Khanna [Wed, 14 May 2014 21:24:18 +0000]
arm64: optimize el0_sync branch prediction

el0_sync manually sets the link register(lr) with ret_from_exception. This
is not recommended since it causes branch misprediction on RET. This patch
makes use of bl and adds an extra branch to tradeoff for the branch
misprediction.

Bug 1488764

Change-Id: I378754cb5fef46aacea42e3fe6c8db327e2a7a96
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/410430
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: Tegra: add debugfs node for cluster switch
Peter De Schrijver [Fri, 9 May 2014 14:59:49 +0000]
ARM: Tegra: add debugfs node for cluster switch

Change-Id: Ib9e617c69a37aeaa6989f6fa0139daafbdd05979
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/407636
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>

5 years agoclock: tegra21: Update max freq for dmic
Hoang Pham [Sat, 17 May 2014 06:28:05 +0000]
clock: tegra21: Update max freq for dmic

Change-Id: I186018d1d27ecf6cc2ca8fec020733bdc2c3aa4f
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/411154
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoclock: tegra21: Fix merge issue
Hoang Pham [Tue, 20 May 2014 19:12:44 +0000]
clock: tegra21: Fix merge issue

For some reason the CL 407561
removed some part of CL 408052.
Restoring it back.

Change-Id: I17602baceff805eb8c68f5507931771a6933e422
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/412206
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: nvmap: Make page pool params modifiable
Alex Waterman [Tue, 29 Apr 2014 17:03:53 +0000]
video: tegra: nvmap: Make page pool params modifiable

Export several sysfs nodes to dynamically control the following
configuration variables:

  NVMAP_PP_DEF_FILL_THRESH
  NVMAP_PP_DEF_ZERO_MEM_FILL_MIN
  NVMAP_PP_DEF_MIN_AVAILABLE_MB

They have defaults but such defaults may be necessary to change.

Change-Id: I236fa4b9cbd40db9008b20cd4c5c726b68ba4185
Signed-off-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: nvmap: Fix misleading comment
Alex Waterman [Mon, 28 Apr 2014 21:31:09 +0000]
video: tegra: nvmap: Fix misleading comment

The comment would have led one to believe that the
NVMAP_PP_ZERO_MEM_FILL_MIN define would disable the page pools
entirely but that is not the case, instead it essentially
disables the background allocator. This is due to the fact that
without zero'ed pages memory is inserted right back into the
page pools instead of being freed to the system.

Change-Id: Id6e7664609f4a6d776febcfc9b9d751755806ac0
Signed-off-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: nvmap: Add get func for pool size
Alex Waterman [Thu, 24 Apr 2014 23:33:23 +0000]
video: tegra: nvmap: Add get func for pool size

Add a function to get the page pool's size without requiring
users to traverse the nvmap structs.

Change-Id: I40e633a1454d696a3602352b2c708ba56f8e2bb3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/401169
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agommc: core: add null pointer check before dumping info.
Prafull Suryawanshi [Thu, 8 May 2014 06:02:43 +0000]
mmc: core: add null pointer check before dumping info.

While trying to dump all sdmmc files debug data, on TN8,
card is not present on few sdmmc controllers resulting in
null pointer access. This change fixes this by adding check.

bug 1508535

Change-Id: I4ce6ff7b95b81e53684aed2602f932d6214f1221
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
(cherry picked from commit 6a17f1ac0f24e6d9e2218d4ea3f32db784ffd1e5)
Reviewed-on: http://git-master/r/406766
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/410891
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoata: Skip ahci dump call if module probe not ivoked.
Prafull Suryawanshi [Tue, 6 May 2014 13:26:21 +0000]
ata: Skip ahci dump call if module probe not ivoked.

Bug 1508535

Change-Id: I208ce8765d86d8f35b1f9c6fc9519c159de5522a
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
(cherry picked from commit 1ce382c5f334408da85ba314e46a999a3aa420a7)
Reviewed-on: http://git-master/r/405845
Reviewed-on: http://git-master/r/410889
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: T132: add sku fuses to cpu/gpu speedo_id 1
Ishwarya Balaji Gururajan [Mon, 5 May 2014 19:12:20 +0000]
ARM: T132: add sku fuses to cpu/gpu speedo_id 1

add sku fuses 0x0f and 0x83 to cpu/gpu speedo id 1

Bug 1442659

Change-Id: Ie6f8aa080cdf736633b3a9595b8bb3144060b097
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/405371
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: T132: update DVFS tables for E1971
Ishwarya Balaji Gururajan [Tue, 20 May 2014 00:55:56 +0000]
ARM: T132: update DVFS tables for E1971

update emc DVFS and derated tables for E1971

Bug 1434354

Change-Id: I91a35ad71be7022bd2b24f6b964096004271443f
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/411742
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoclock: tegra21: Decouple bus limits from bus state
Hoang Pham [Fri, 16 May 2014 20:49:57 +0000]
clock: tegra21: Decouple bus limits from bus state

Select BUS_RATE_LIMIT flag for cap, and floor users of Tegra12 shared
buses: c2bus, c3bus, gbus, and host1x bus. Hence, applying/removing
(enabling/disabling) the limits won't affect bus enable/disable state.
Made sure that bus rate is retained in case when only limit clocks are
enabled (for gbus that supports rate retention).

Note that bus caps were already initialized as always on clocks, and
that effectively decoupled caps from the parent bus state; floors,
however, are decoupled by this commit.

Also add gbus edp capping clock

Ported from tegra12: Change-Id: I905e9fbeafd9c2afe10f0e417477a0551d598bcb
Ported from tegra12: Change-Id: I2e2cbd0582f1051d7c78aa367df427565f3c70f0

Change-Id: I6dacc0f2878820b3767ecf0993290318d83065fb
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/411029
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agomutex: save power with better cpu_relax
Alex Van Brunt [Fri, 16 May 2014 19:37:06 +0000]
mutex: save power with better cpu_relax

Use cpu_relaxed_read and cpu_read_relax to allow more architectures to be able
to "relax" instead of busy spinning.

Bug 1440421

Change-Id: I48e36d7b3c953fe43ebb23ea814de7738c91e394
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/410997
Reviewed-by: Sumit Singh <sumsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: configure battery thermal charging for TN8-DVT2 more precisely
Laxman Dewangan [Fri, 18 Apr 2014 06:51:55 +0000]
ARM: tegra: configure battery thermal charging for TN8-DVT2 more precisely

Configuring the charger for foowing profile:

T <= 0: Charging disabled by charger.
 0 < T <= 10: 1040mA/4352mV
10 < T <= 15: 1040mA/4352mV
15 < T <= 25: 2600mA/4352mV
25 < T <= 45: 5200mA/4352mV
45 < T <= 60: 2600mA/4200mV
60 < T : Charging disabled by charger.

bug 1435980
bug 1472161

Change-Id: I90a5f0e9ccff6b8e95ed52b1d12376762c393d84
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/398119

5 years agoARM: tegra: add thermal voltage/current profiling for charger on P1761-A03
Laxman Dewangan [Tue, 15 Apr 2014 13:26:49 +0000]
ARM: tegra: add thermal voltage/current profiling for charger on P1761-A03

Configure the voltage/current thermal profiling of battery for charging:
T<= 10 deg C:       1024mA/4350mV
10 < T <= 15 deg C: 2048mA/4350mV
15 < T <= 45 deg C: 5200mA/4350mV
45 < T <= 60 deg C: 2600mA/4200mV

The SoC adjustment is 2 to 100% of FG -> 0 to 100%.

bug 1472161

Change-Id: If77ccadfee3f05fbc704a54e8a4c89119cc23221
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/396452
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/409173

5 years agomedia: tegra: nvavp: Handle missing DMA address
Sami Kiminki [Tue, 20 May 2014 15:37:50 +0000]
media: tegra: nvavp: Handle missing DMA address

If DMA address is not defined, use the physical address.

Bug 1500983

Change-Id: Ib2ceea2c910f3dbb9ea61580669dd4ae52ddba29
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/412106
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: select MAX98090 codec for MACH_LAGUNA
Shreshtha Sahu [Mon, 3 Feb 2014 14:02:30 +0000]
arm: tegra: select MAX98090 codec for MACH_LAGUNA

Bug 1377308

Change-Id: I77b2fca9d6f9a75b1688c21950ecfc46bddde704
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/362917
(cherry picked from commit 422b6d15ed922dae79cd6885f6ba42dbb9daba72)
Reviewed-on: http://git-master/r/402738
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agommc: core: export trace points symbols for module
Shreshtha Sahu [Tue, 29 Apr 2014 10:52:55 +0000]
mmc: core: export trace points symbols for module

This patch exports trace point symbols so that it
is defined for mmc as a module.

Bug 1499809

Change-Id: I36a7a1d1644ef1a0ba6f334db41b04bb50ec57d6
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/402918
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>