arm: tegra: ardbeg: E1731/E1735: fix boot issue

-Issue caused due to change 242505
-Display is not up for E1731
-Display and touch are up but adb is not for E1735

Bug 1300619
Bug 1306376

Change-Id: Icb65f933b9d99b96dcf0acdad31f49744bdaa7e1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/243076

ARM: tegra: ardbeg: t12x: update aux data table

Bug 1297408

Change-Id: I4c164a4d07dc675c1a193e4b15950d3267cbf4f7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/243049
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: ardbeg: t12x: set backlight and touch gpio

-GPIO_PH2 is set to 1 to enable backlight
-GPIO_PK4 is set to 1 to reset touch

Change-Id: I28ecb469f7a5233c8101f8a4a7c9d565aa735343
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/243036

arm: tegra: ardbeg: Fixed Touch not working

-Add (dvdd, spi0.0) regulator to as3722_sd5

Change-Id: I45bd9e73c82234387b5115f8a19585d39282dd33
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/243030

video: tegra: Clear IDDQ of GPCPLL

bug 1313713

Change-Id: I93da0fffe07bbb4deca6ff52e087dff6e7401ba6
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/242672
Reviewed-by: Chao Xu <cxu@nvidia.com>

arch: arm: tegra: ardbeg: Add GPIO keys

Change-Id: I1703266be322b9a72e2093e0ad3b2fb08fdb6264
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/242091
Reviewed-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: ardbeg: Enable 32k AMS RTC OSC clock

AMS doesnt assert XRST_OUT if the 32KHz clock from the RTC oscillator
is off

Change-Id: I1ad7babea51abcb452ecac37317cdd3749ccc07c
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/242090
Reviewed-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: ardbeg: Add AMS external rail control

Add support to individually enable external rail control for all the
rails in the E1733 power tree

Bug 1284096

Change-Id: If904d83bbf16b14598399169df043012952bc7b2
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/242088
Reviewed-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra12: fix MC latency allowance programming

Unlike T3 and T114, MC latency allowance registers on T124+ are
not in a contiguous MMIO range anymore, which is fixed by this
change. This change also updated the latency allowance register
definitions based on T124's HW spec.

Bug 1289211

Change-Id: I225d1956f669c1efcebce0442856a8d28a692bef
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/242508
Reviewed-by: Adeel Raza <araza@nvidia.com>
Tested-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra12: clock: Enable GPU PLL reference clock

GK20a GPCPLL uses OSC_DIV_CLK as a reference clock.
This change enables the refence clock to go to GPCPLL.
GPCPLL is started by host1x driver later.

Change-Id: Icf30c582eeaf4138dbd532c0ef0a3c6e22e6c686
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/242641
Reviewed-by: Chao Xu <cxu@nvidia.com>

tegra: video: dc: program blend depth for overlay

bug 1306011

Change-Id: I5d9dab0edb78414e349a1c1f4121fcf2884b399a
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/242129
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

video: tegra: Fix GK20a specific parameters

bug 1313712

Change-Id: Iafee0b4129bad124a4c43cee046055f1104fc689
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/242663
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

arm: tegra12: add t12x cpuidle support

Use T11x cpuidle driver for T12x.

Change-Id: Id7bafe6649da03ba86300f9563266ca4ce74a094
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/242117
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

ARM: tegra: pci: Parse odmbits to config lanes

1. Parse odm bits[28:30] passed by boot loader to
kernel.
2. Program XBAR config based on above odm bits
3. Program Lane ownership to PCIe based on odm bits
4. Program GPIOs based on odmdata to enable PCIe
x1 slot for ERS-S board

Bug 1305915
Bug 1299907

Change-Id: I5a252df0577098c8b42dfe3eb745100fad964592
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/241767
Reviewed-by: Seema Khowala <seemaj@nvidia.com>

mfd: as3722: add gpio irq support

Bug 1294707

Change-Id: Ice8eb1e94ac7971d61ba20c1e8aef04a57f8733f
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/242443
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: pcie: Add laguna board support

1. Add pcie probe for laguna boards
2. Add T124 specific regulator get & enable calls
in driver

Bug 1299907

Change-Id: I36ccc3e75db77a5247bf64029ed6e2feecf60f91
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/241766
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: t124: Add SPI DT support

Bug 1297408

Change-Id: Ie7cdd7002132f8205af2fc033f6b63d603fbbefe
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/242412
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: t124: ardbeg: Add SPI support

Bug 1271900

Change-Id: I3d7269c4aa1ffffb4a59deb8554c845db8adf79f
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/242743
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: pcie: Organize memory space

1. Organize mameory allocations to enhance compati-
   bility between all chips
2. Correct setup translations to avoid unecessary
   config space BAR configuration.

Bug 1210832

Change-Id: Ie0cc8c553e7df7403bba2a6839db2d701dd32164
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/241765
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM: tegra: ardbeg: Mask HS200,SDR104,SDR50 modes

Masking HS200, SDR104, SDR50 modes. These modes will be enabled once
the validation on silicon is done.
Remove default pm_flags settings for SDMMC1. The Wifi client driver
would set the required flags during suspend.
Pass card detect pin for SDMMC3 through platform data.
Updating SDIO1, SDIO3 drive strengths

Change-Id: I8a776b7f5f4e448e5f2b751ecda965e4bd01bf21
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/242428
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

video: tegra: nvavp: Change IOVA load address for AVP OS

SMMU IOVA range has moved from lower 1GB to (2GB-4GB), due
to which AVP OS is linked and built to be loaded at new
IOVA address 0x8ff00000 which falls within the new range

Bug 1287223

Change-Id: I276c51f478eb2831085a46ca09acf121a8675e9c
Signed-off-by: Somasundaram S <somasundaram@nvidia.com>
Reviewed-on: http://git-master/r/241815
GVS: Gerrit_Virtual_Submit
Tested-by: Somu Sundaram <somasundarams@nvidia.com>
Reviewed-by: Soumenkumar Dey <sdey@nvidia.com>
Reviewed-by: Somu Sundaram <somasundarams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: tegra: t124: Add DMA DT support

Bug 1297408

Change-Id: I480e6d086cc4c653c73b093089f1b6c21840c44d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/241907
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: usb: add range for CPU frequency boost

Add the range for CPU frequency boost needed
for USB.

Change-Id: Ibae86ccc7d4bb7fe14ad8867be88e43b24f0aa45
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/242488
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM: configs: tegra-bonaire: Enable serial-tegra

Bug 1295540

Change-Id: Ia61e5f44886d8f1d4acb2384b8058bcdea770adc
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242719
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: configs: tegra12: Enable serial-tegra

Bug 1297408

Change-Id: I6e2b43417cab2a2bf6a17327441eb40d33263c35
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242718
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra12: Enable serial uart

-Add alias for serial-uart.
-Enable it for Laguna and Ardbeg.
-Set earlyprintk console baud to 115200.

Bug 1297408

Change-Id: I929a9c1732a599373e3402ebb0785cc2bb1991f6
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242336
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: ardbeg: Add uart init

-Add uart initialization.
-Correct DMA mask for T12x.

Bug 1297408

Change-Id: I8620094819a2a6733aadf1657f264a5ac138ec7d
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242335
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: ardbeg: E1733: Update power rails

-Correct 1v8 entries.
-Correct sdmmc entries.
-Correct vbus entries.
-Enable full constraints.

Bug 1300619
Bug 1306376

Change-Id: I65e5e368a5c385fdaf4ee028f58455f4443ca6ab
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242505
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

regulator: as3722: Fix interrupt mask setting

Set the appropriate Interrupt mask register for the external rail
controls based on the correct control enable values

Bug 1284096

Change-Id: I06522f3f3d4686b85fdc785468b6e7359ba1937a
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/242089
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

video: tegra: use correct params in edp code

Use correct number of params for tegra_dc_sor_set_dp_linkctl(...).

Bug 1306371

Change-Id: Ib065176ff8b5d418c5f07b6ace1402d8aacfb15b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/242608
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

ARM: tegra: laguna: Fix fixed regulator init

Bug 1306376

Change-Id: I653392690f7665eadd236ef5b1d0a7b481f1f9ea
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/242708
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arm: tegra: ardbeg: support E1735 pmu module

Bug 1310396
Bug 1309984

Change-Id: I7e1af6da7a9521afbadeabf1b3cd66188dfdb188
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/242616

ARM: config: Add mods ardbeg defconfig

Add t124 mods defconfig, currently a duplicate of android defconfig

Change-Id: If1e3ac237e187f39940ce9a1980650dc103d21ea
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-on: http://git-master/r/242565
Reviewed-by: Chao Xu <cxu@nvidia.com>

video: tegra: dc: Add panel depth value

eDP cacluation needs bpp value for the panel. Add it to the board file
so we can do the right calculations.

Change-Id: I0ec7e1aa46c57d6cfacd809828e9af153e4c2eb5
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242520

video: tegra: dc: Add DP/LVDS support to dc/ext

Change-Id: I49617eedb7f5dd65fb032f9c9972612a75d01523
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242519

ARM: mach-tegra: Add LVDS panel support to bonaire

Change-Id: I74b8536f152f1f8d9f1e37e3e21570cda30c028a
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242518

video: tegra: dc: Update LVDS support

Bug 1253161.

Change-Id: Ib46517424944f7b57a116387422c41a2bd0ac732
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242517

ARM: tegra: Check NULL pointer to avoid crash

This is just a workaround. Ideally any access of the tegra_dc_feature_xxx
function needs to check if the window exists.

Change-Id: Ib15e618412e03038b08579b57aef1ff32592b6d8
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242516

ARM: tegra: bonaire: increase FB memory size reservation

to support higher resolutions.

Change-Id: I5018ac64e9e0c71ab4318b033745b1b106725b3a
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242515

ARM: tegra: Support second head for bonaire

eDP was put in displayB on FPGA so add the second head support for bonaire.

Change-Id: Ibd69ab68063fe3014aa40e5765fe233fc83b4a7c
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242514

video: tegra: dc: Update eDP code

Verified on FPGA (bug 1258447).

Change-Id: Ie95880b99f453d57d659579e6f3b9e6aed393190
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/242513

ARM: tegra: add emc clk set sequence for T124

bug 1171013

Change-Id: Iaad24b9326e78fdd19c26f655c0412407d2368de
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/242139
Reviewed-by: Chao Xu <cxu@nvidia.com>

usb: phy: tegra: add avdd_pll_utmip regulator

For tegra124 avdd_pll_utmip is the regulator pin
name for powering up utmip pll.

Bug 1313825

Change-Id: Ic845b1ea5f188ac173ba9737c2dbfe191e6b34b9
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/242004
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM; tegra: ardbeg: Update SDMMC3/SDMMC4 settings.

-Update tap/trim settings for SDMMC3 and SDMMC4
The Values are as per T124 SDMMC IAS V5.
-Update ARDBEG SDMMC3_CD GPIO Number.

Bug 1297408

Change-Id: I1cf54dbbdb5621871911b489d1ee7c88d983d6a0
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/242350
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM: tegra: ardbeg: Update SDMMC3/4 drive strengths

-Update SDMMC3/4 drive strengths
-Values are as per T124 SDMMC IAS V5

Bug 1297408

Change-Id: I1772834e32ce300368e94003853401d562ea77b0
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/242364
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM: tegra12: config: disable CONFIG_TEGRA_USE_SECURE_KERNEL

Change-Id: I3fc6160804ff8cbe43c7037e1f1ecdec421ac07c
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/242290
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra: t12x: Set SDMMC3_CLK to INPUT

Set SDMMC3_CLK to INPUT

Bug 1297408

Change-Id: I6959d1b72f163171a9b2c3fa0d4d0cdb84a1d472
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/242339
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

ARM: tegra12: clock: Updating DVFS table to Safe value

Updating the DVFS table to safe value provided from the silicon validation team. These will be used for initial bringup.

Change-Id: Ia7f8e0a3724fdd5217c89d0c9a707bf88f807ce8
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/241878
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: tegra: enable rt5639/45 for ardbeg/laguna

enable RT5639 and RT5645 audio codec for
ardbeg and laguna

Change-Id: I51295db7f9327046fc8c3e2189d25314aac0ea4b
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/241789

arm: configs: t12x: Enable USB configs

Enabling the OTG wakelock and CPU
frequency boost configs for USB host,device
modes.

Bug 1306371

Change-Id: Ia4648d8497f43b416e0d524d2014acaa7d0eefc2
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/242000
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

mfd: as3722: add Power off functionality

Add power off support in as2722 PMIC.

bug 1294690

Conflicts:
drivers/mfd/as3722-core.c

Change-Id: I1f0b007601c6eedf7bb036cd34ec93907c0a3127
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/241884
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

asoc: tegra: enable HS/HP detection for RT5639

1. HP must be powered down when routing to speaker
   else we can get spurious interrupts for HP detection
2. Increase the current threshold to 1500uA for HS/HP
   detection

Change-Id: I81560e07ea00d03da9fc7de0586fd1e759f6dde9
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241788
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

arm: tegra12: clock: add duplicate clocks for audio

Change-Id: Iec87f8c1345329b7c5915bbac5f7c1112d2f1390
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/242304
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
Tested-by: Manoj Gangwal <mgangwal@nvidia.com>

ARM: tegra: config: Add AVP Audio support

Add the config for enabling avp audio.

Bug 1294654

Change-Id: I383cf76d61da3b252bbe80ae10f483bf7903ad9d
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Reviewed-on: http://git-master/r/241903
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Tested-by: Nikesh Oswal <noswal@nvidia.com>

video: tegra: host: adapt gk20a and vic03 as per tot

commit 55e0dbc & 9f0d0e3 changed the way host1x and its
modules use runtime pm and pm domains

this commit adapts gk20a and vic03 inline with above
commits

Change-Id: I8f497976f68bd7c80c56d88b3fe001e95e00c0cc
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/241958
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Fix vic and gk20a runtime pm

nvhost pm support was refactored to reduce duplicated code. Adjust
VIC and gk20a code to work again.

Change-Id: Ie4708c6d28b07445cc6b3176f35d2da1de5010f5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241909
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12: Add second ISP clock to VE domain

Add ispb clock to the reset list of VE domain.

Change-Id: I2a69b691c15456ec40fa5d228ea22cab81a134d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241906
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Add ISP & VI power gating

ISP and VI are both in VE domain, so they have to have a common
power domain. nvhost_module_add_domain() will not first try to add
to an existing domain with the same name, and if that doesn't work,
creates a new one.

Use this mechanism to put VI and ISP devices in the common VE domain.

Conflicts:
drivers/video/tegra/host/isp/isp.c
drivers/video/tegra/host/nvhost_acm.c

Change-Id: Ib630a81ed514c88d9342579655ed80540c7b3c9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241905
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Add gpfifo tracing

Add gpfifo tracing. This needs decoding of the gpfifo, so adds also
PBDMA entry constants to hardware headers, and takes them into use.

Also changes submit event to be called before sending to hw, and a new
submitted event that indicates we've written submit.

Change-Id: I546a2ba770fe803795f660a2ff7aabc506f2004c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241894
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12: host1x DT support

Bug 1297408

Change-Id: Ifd446986ff3a8e3513378589db003de8dfeb3a74
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241890
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra: Assign gk20a to an own ASID

Move gk20a to its own ASID, and give it full 4GB of IOVA space.

Bug 1306715

Conflicts:
arch/arm/mach-tegra/devices.c

Change-Id: Idd6b408e9d8228eebbc3957d349cd591ecaeb3d2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241883
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: dts: Add host1x and gk20a for Tegra12

Bug 1297408

Change-Id: I9ec50a22c7b66885c7f9c63d1daa33c5017bcca7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241882
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: DT support for Tegra12

Implement DT support for Tegra12.

Bug 1307269

Change-Id: I54d5ea0ee9b3eedd73e1e1aae1fe2fc2b5129631
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241881
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Check error from channel finish

gk20a_channel_finish() returns an error code. Check the error code.
Currently only unmap can deal with error by refusing to unmap a buffer
when channel refuses to finish.

Bug 1304227

Change-Id: I0d377277cc139cac72636a7da67c80397877ffcc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241877
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Increase preempt timeout in sim

Increase preemption timeout in simulation.

Bug 1304227

Change-Id: Ibd1985ef2fde87b52e465a11b6c56a6aaf0fe980
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241876
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: host: Use non-interruptible wait

Introduce a non-interruptible variant of nvhost_syncpt_wait_timeout().
As we're not capable of dealing with signals when closing a channel,
take that into use when unbinding a channel.

Bug 1304227

Change-Id: Ieab60bf3e6a71a9da42f6503ff292092fa4d1f70
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/241875
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

crypto: tegra-se: Remove condition to enable SE clock

Enable SE clock even if it is fpga platform

Bug 1271895

Change-Id: I461dbf44a597eeda3fe940c775f0f131b55da52a
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/241873
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12x: Add FC programming for enter_sleep

Add config to include flow controller programming
to enter_sleep routine.

Bug 1271462

Change-Id: Ie6e56766eedf64435f00dc594be20babc576eca0
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/241911
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12: clock: Suspend and resume for PLLSS

- Add suspend and resume for PLLC4, PLLD2, PLLDP

bug 1164664

Change-Id: I7e29367d4d1bbe05b44d196b67e6f1eceb52229d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/241872
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12: pm: Update self-refresh code

Update a few configs in the self-refresh code
to support T12x.

Bug 1271462

Change-Id: I42f2d4028338298b42e22c92488f22c1547fe128
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/241910
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra12: clock: Update XUSB plls configuration

- set PLLE spread spectrum coefficients
- added possible PLLE configuration with 12MHz input clock
- increased PLLREFE maximum rate to 672MHz

Ported from http://git-master/r/196805 (change for Tegra11)
bug 1164664

Change-Id: I351424b74e43e4de86584e5cd112f6f951f71508
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/241871
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

usb: xhci: tegra: don't shutdown BIAS PD

This should be done in common PMC code.

Bug 1268244
Bug 1301052

Change-Id: I9ca4efe6634b3a3397de2304ec5a5e43cbd66069
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242032
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

usb: xhci: tegra: cleanup regulator init method

Cleaned up regulator init to print error message if a regulator
is not found. Enable a regulator only if after successful
regulator_get

Change-Id: I538ca553eff65d3e3cffce7ef164e87788ce83e8
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242031
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: ardbeg: add support for xusb

Bug 1301052

Change-Id: I91a876fce3801de0221dc1abaefbdb82fb9d0b60
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242030
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

usb: tegra: Use common api for shared access

Bug 1286074

Change-Id: Iff4016a470a2b27ec4270262f01508c89f5bda3d
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242029
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: xusb: fix build errors

Change-Id: I2a4421eeac34f737c8852fa34abe258efa04062a
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242168
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

usb: xhci: tegra: set SNPS owner only if no hs connected

Commit "usb: xhci: tegra: set SNPS as owner to save power"
cause reset error when SS hub is connected as bus_suspend is
called while HS part of hub is connected.

Fixing by checking if any HS device connected before setting
port owner as SNPS

Bug 1275290

Change-Id: Id02ed5cf514c16c9bbba5f695a3f1a06758d80a9
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242028
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra11: clock: Rearrange XUSB clocks for 11x and 12x

We need different HS clock sources in 11x for HS disconnect
SW WAR. The clock source table is incorrect for 11x and 12x
so fixing same.

Change-Id: I87d13534b5a573b62ee06d5cbf10774ff899d426
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242026
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: ardbeg: add regulator entries for xusb

Added below xusb regulators
1) vddio_hsic
2) avddio_usb
3) avdd_usb_pll
4) usb_vbus
5) hvdd_usb

Bug 1301052

Change-Id: Id4602edfbb9bfea53c2587c4177119f95416932b
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242025
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: add xusb as IOMMUable

Bug 1305462

Change-Id: Ia176542d31082c434649220e97c1ed6b5c63b2fd
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242021
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: configs: t12x: enable BCM43241 and SD8897

Enable BCM43241 and SD8897 Wifi drivers

bug 1306371
Change-Id: Ie97aaadccd18eb5d4ae38650e69c3afee4e4e4ba
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/241902
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

asoc: tegra: power optimisations for ardbeg/laguna

1. Add dynamic enabling/tristating of DAP
2. Turn codec clock off/on in suspend/resume
3. disable/enable headphone detcetion interrupts
in suspend/resume

Bug 1256430

Change-Id: Id37dd4819ed34f65ece06da89ea258fa3cf20536
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241918
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

arch: arm: tegra: set audio pinmux for T12x

set audio pinmux for T12x platforms - ardbeg
and laguna. Increase the drive strength of DAP2
required for Codec Master Mode.

Change-Id: I65f523f917a250b502caad82ec51448206769d02
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241917
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

asoc: tegra: add regulators and RT5639 on Laguna

1. Add support for RT5639 on Laguna
2. Use proper Regulator names in RT5639 and RT5645
   machine driver
3. avdd, dbvdd, micvdd and ldoen are always on
   regulators
4. dmicvdd and spkvdd can be turned on/off on
   need basis

Change-Id: I2dd77b6d91abf3ed41899d213122527398ad0d3a
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241916
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

asoc: tegra: add support for rt5639 on ardbeg

Change-Id: Ice099d066868e986424cffd1c9fa057a9b7dbb9d
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241915
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: Add dummy device to t12 specific fixup table

Change-Id: I9b22ac51fe76355c9e72e1333f4568005fb91f9a
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241914
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

asoc: tegra: rt5645: set clk for 24 bit audio

Change-Id: Iffccb194ca75699f305cfe59493c2a3c71e79456
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/241913
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>

ARM: tegra: dalmore: Add camera power rails

Add missing camera power rails definitions for palmas
regulator driver, which is being used for dalmore A05.

Bug 1287827

Change-Id: I8d2de4564e3f4860072bd8d0894f29a11a86f26a
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/237560
(cherry picked from commit 39e1f1b1c4cfa2531afe960c84e1c4c88d7b240a)
Reviewed-on: http://git-master/r/241747
(cherry picked from commit 322f48d4e77c1b803fabce1121ac7929f614868e)
Reviewed-on: http://git-master/r/247622
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

usb: host: tegra: disable pmc before going to LP0

Disable pmc before going to LP0 irrespective of
whether it is otg port or not.

Bug 934024

Change-Id: I53aa18f5c3f6492d0fe97d2d7a0b969392bcdb71
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/239342
(cherry picked from commit 833d8333a11abba3ba0ddce658ff1b97a2ff98bc)
Reviewed-on: http://git-master/r/247152
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

usb: otg: tegra: add vbus control in otg driver

If USB port has OTG support, allow the OTG driver
to control the vbus.

Bug 934024

Change-Id: Ib129ee2d1f60c18ae17afa146421cab0acca7141
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/239341
(cherry picked from commit d15f126d9568ddbceb808078440c6030574212c3)
Reviewed-on: http://git-master/r/247151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: add usb_vbus entry for OTG driver

If USB port has OTG support, allow the OTG driver
to control the vbus. Adding the usb_vbus entry
for OTG driver.

Bug 934024

Change-Id: I86253d145a6ff966e7a4e50deee695efe8545b88
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/239340
(cherry picked from commit 1e550fe0c2df52668af16b5b1fcff0a83d1f2466)
Reviewed-on: http://git-master/r/247150
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: tegra3: PCIe PLL Reset

Workaround of PLL Setup.

Bug 1302133
Bug 1313433

Change-Id: I718e8a355cd0e8c86c1930c5fd036cb06e9f6f89
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Reviewed-on: http://git-master/r/241227
(cherry picked from commit 86b877e7604e28c6c4621048ac9c0f6943dd7221)
Signed-off-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-on: http://git-master/r/245007
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Ashutosh Patel <ashutoshp@nvidia.com>

fs: proc: meminfo: add nvmap stats to meminfo

Change-Id: Ida9011d45abbd097dd09d2b42f67df17e05252a2
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/240289
(cherry picked from commit a21680615f6ee5fe36f29601ecd3d16060258aaf)
Reviewed-on: http://git-master/r/247373
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: fix compilation error

Fix compilation error when ARM_DMA_MEM_BUFFERABLE is disabled

Change-Id: I9f12d9ca3428ca24762e54482997024a96534a3f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/240261
(cherry picked from commit d682b1857c6952e9c38147523429518d432b4e42)
Reviewed-on: http://git-master/r/247372
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: boards: define variables as static type

Define the file local variable to static type to avoid export and
multiple declaration on other file.

Also remove initdata keyword from variable data.

Change-Id: I74cce98e2eb14551444b7aa76cc1b2a479955b99
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/247101
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

misc: issp: add support for force update

This change adds support for the firmware to be
force updated. This flag can be used to downgrade the
firmware.

Bug 1270341

Change-Id: I2c7eee9029cce38fdb902b211fb2800071579ff9
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
(cherry picked from commit 7e506cd5b9af34b0f86956193d8bd8ad910ac0b0)
(cherry picked from commit 90b6a9378c0b3050ca43f8a75b55d1e266d6c592)
Reviewed-on: http://git-master/r/246781
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: chip-specific power detect cells

T14x specific power detect cells only must be used. The
implementation needs all supported power detect cells
specific to chip. If extra entries are declared for a
chip the initialization fails.

bug 1231612
bug 1236429
bug 1231668

Change-Id: Iffe8271c77f1b382972f29f20dc0a4094b270490
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/242233
(cherry picked from commit 11d6341368449513f9ba56ab868cf05ff0002300)
Reviewed-on: http://git-master/r/247140
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: wake table update

Wake table for T14x updated to enable tested wake sources

bug 1313181

Change-Id: I0c1679d704c981f9876280166957a863d7f6d960
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/241440
(cherry picked from commit da08d926eaab177bb8a52968096c71f26b5e87e4)
Reviewed-on: http://git-master/r/247136
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: T114 wake source table update

Disable wake sources that are not known to be tested with T114

bug 1286802

Change-Id: I259b066fbc498378b1fbb4b1577c4bf973cc10b1
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/231926
(cherry picked from commit 8dea4c43dd30049e43ec620a2117db8a85dc3565)
Reviewed-on: http://git-master/r/241041
(cherry picked from commit 21bd9d5356d6805042a02855bc3c552e8cc6a4fc)
Reviewed-on: http://git-master/r/247135
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: allow 1-to-many irq to wake mapping

Problem:
Current Tegra wake table does not allow same USB irq to be used
for multiple wake sources.

Fix:
Changed tegra_irq_to_wake API to return multiple wake table indices

bug 1286802

Change-Id: I72e6d83cb71de76e23ea9623b6fcae34091171bb
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/231921
(cherry picked from commit b96d7c7db56bb49cd4f81190e25cf55b58794ab7)
Reviewed-on: http://git-master/r/241037
(cherry picked from commit 0e715b8054e22764e76c4f746287ba1c7c166501)
Reviewed-on: http://git-master/r/247134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>