5 years agoARM: tegra14: dvfs: Update switch between DFLL and PLL
Alex Frid [Sun, 24 Feb 2013 02:20:40 +0000]
ARM: tegra14: dvfs: Update switch between DFLL and PLL

Ported from Tegra11 commit 4a0c6ef45d3f806835c27fc492a09e2eb254b0a6

Change-Id: I265daf029fb51508eb047882aac2e4106931015f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/203614
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Update switch between DFLL and PLL
Alex Frid [Tue, 12 Feb 2013 19:04:40 +0000]
ARM: tegra11: dvfs: Update switch between DFLL and PLL

Modified procedures for auto-switching between PLL and DFLL CPU clock
sources.

- On switch from PLL to DFLL do not allow legacy DVFS to set voltage
for target rate in one shot. Limit setting to minimum DFLL voltage,
and let DFLL to complete voltage ramp after the switch.

- Similarly on switch from DFLL to PLL, first use DFLL mode to lower
cpu voltage to DFLL minimum, leaving only delta down to target for
legacy DVFS.

This modifications speed up the transitions and make them safer, since
major change of voltage, rate, and consumed current happens in DFLL
mode.

Change-Id: I42eee166510bd74d046bc6b3cb232ca10233ead9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/200382
(cherry picked from commit 4a0c6ef45d3f806835c27fc492a09e2eb254b0a6)
Reviewed-on: http://git-master/r/203613
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: pismo: Fix build warnings
Kaz Fukuoka [Thu, 21 Feb 2013 03:02:54 +0000]
ARM: tegra: pismo: Fix build warnings

Change-Id: I64ae7095504b0d250334f0c603e1b151f0a2154a
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/202792
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agodrivers: misc: Hysteresis support in fan est
Anshul Jain [Sat, 22 Dec 2012 01:09:24 +0000]
drivers: misc: Hysteresis support in fan est

This driver now can support hysteresis in trip
temps. It now allows different cdev states for
rising and falling trend in thermal framework.

Bug 1200196
Bug 1201225

Change-Id: I9559eefdb1f2313e1d06f8945fdc1b68f62c6934
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/#change,173927
(cherry picked from commit 44330da37f6c45a1215df26c10ef55fd0828b8fd)
Reviewed-on: http://git-master/r/173066
(cherry picked from commit a3f396a68ecf540fa0c6b4c86babdc24c89bfd5b)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/201620
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra: Enable -Werror in mach-tegra
Kaz Fukuoka [Thu, 21 Feb 2013 02:52:19 +0000]
ARM: tegra: Enable -Werror in mach-tegra

Change-Id: Ifc0b400ec7488282546cde106810b082c7ec8b0e
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/200938
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agocdc_ncm: changing Icera Nemo modem PID to 0x1007
Steve Lin [Tue, 5 Feb 2013 01:06:19 +0000]
cdc_ncm: changing Icera Nemo modem PID to 0x1007

Bug 1176649

Change-Id: I6222f28e1a323333a324745a764b8384795ce5d1
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/197220
(cherry picked from commit 477b3112d297ff3948a86c08fc5dd8e2d512c6e1)
Reviewed-on: http://git-master/r/203520
Reviewed-by: Automatic_Commit_Validation_User

5 years agoPM / Domains: Add debug fs to display domains status
Prashant Gaikwad [Wed, 20 Feb 2013 11:24:18 +0000]
PM / Domains: Add debug fs to display domains status

Add debug fs entry to show the domain and device status.

/sys/kernel/debug/pm_domains/domain_summary

Bug 1010971

Change-Id: I4eb821f8bf825e83b72778f30e05d22fc885eb72
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/202504
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: sata: set SATA clock to 272MHz
sreenivasulu velpula [Thu, 7 Feb 2013 09:13:43 +0000]
arm: tegra: sata: set SATA clock to 272MHz

Bug 1221686
Bug 1170169

Reviewed-on: http://git-master/r/198306
(cherry picked from commit 02f85c2a866df1ae47a7f51707dba88b214b9b83)

Change-Id: I90470d7f11436671db7f7f2af85fbf9de85adaf7
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/201614
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomisc: nct1008: modify shutdown functionality
Sri Krishna chowdary [Tue, 22 Jan 2013 14:03:14 +0000]
misc: nct1008: modify shutdown functionality

i2c transation can happen through means other than
work_func. Wait for any ongoing i2c transaction and
then shutdown.

Bug 1202277

Change-Id: I8e89ee5aec170cae3897e45ddd7379e8d12eace2
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/193058
(cherry picked from commit 87458dcf18aa894243e67bb8ac0b02abeededa51)
Reviewed-on: http://git-master/r/195913
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: teagr11: power: Don't put PLLC in IDDQ on LP1 entry
Alex Frid [Fri, 15 Feb 2013 07:57:50 +0000]
ARM: teagr11: power: Don't put PLLC in IDDQ on LP1 entry

Change-Id: I5cfc4cb611b2610cfb84e64937c09cc5b994ad18
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201058
(cherry picked from commit ba91a5d2026e6736d6b6819899272fc883950b19)
Reviewed-on: http://git-master/r/203622
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra: isomgr: add api to allow bw margining.
Krishna Reddy [Thu, 14 Feb 2013 01:15:35 +0000]
arm: tegra: isomgr: add api to allow bw margining.

few code optimizations as well.

Change-Id: I7b436fe18cf76238c823274e1a092d8025d8ed8a
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/200614
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agoARM: tegra: roth: Change default fan cap
Anshul Jain [Mon, 24 Dec 2012 00:52:50 +0000]
ARM: tegra: roth: Change default fan cap

Bug 1200202
Bug 1200196
Bug 1200075

This is for 8k fans, default cap is for normal mode

Change-Id: Ica358a16ad8597785644d48addd994bd3633d4df
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/#change,174013
(cherry picked from commit 1199eeb30f50f6ea94fea0137dc1139e75b88d9a)
Reviewed-on: http://git-master/r/189760
(cherry picked from commit da6141e57d8e40347ad4102571a6c6b7167f4fe0)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/202446
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: la: restore la and ptsa during resume
Krishna Reddy [Fri, 15 Feb 2013 19:50:55 +0000]
arm: tegra: la: restore la and ptsa during resume

resore la and ptsa to boot values during resume.
remove unnecessary code.

Change-Id: Ib7c3e9b0627572620fa4df08967da18d7473baa8
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/201250
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoarm: tegra: isomgr: update iso bw percentage for t148
Krishna Reddy [Wed, 13 Feb 2013 00:50:55 +0000]
arm: tegra: isomgr: update iso bw percentage for t148

update comments and iso percentage for t148
validate args for correct usage during tegra_isomgr_register.
add magic validation to detect invalid handles passed.

Change-Id: I41cadde7595be3f88171cfc8dabeef70918050bf
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/200274
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: dalmore: Reduce display wakeup time
Animesh Kishore [Wed, 20 Feb 2013 09:01:35 +0000]
arm: tegra: dalmore: Reduce display wakeup time

Change-Id: I15b881b89fa01d819f5db859eaaf2d0d65e545bb
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/202544
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: host: Debug dump to use trylock
Terje Bergstrom [Tue, 19 Feb 2013 08:34:34 +0000]
video: tegra: host: Debug dump to use trylock

Use mutex_trylock() instead of mutex_lock() in debug dump. Debug dump
is not safety critical, so it's ok to sometimes dump state of a
channel that has been torn down.

This fixes a deadlock when channel close waits on queue to clear up
with reflock acquired, submit in queue times out, and timeout code
tries to acquire reflock at debug dump.

Change-Id: Ice9bd3c617808d0b3178912358d7c90f30765be4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/201974
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yury Gribov <ygribov@nvidia.com>
Tested-by: Yury Gribov <ygribov@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agohwmon: ina3221: implement shutdown
Deepak Nibade [Tue, 29 Jan 2013 08:20:53 +0000]
hwmon: ina3221: implement shutdown

Bug 1225028

Change-Id: I252cfc136f5fe2c2118ae4d24d5c2ba64fb94437
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/195027
(cherry picked from commit 14fb9a6d7716c436481621d2a382d1be4b931032)
Reviewed-on: http://git-master/r/201925
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agohwmon: ina3221: Support for turning off ina
Anshul Jain [Thu, 24 Jan 2013 02:05:56 +0000]
hwmon: ina3221: Support for turning off ina

This is an optimization to turn off INA device based on number of cores
online. Also, this change removes support for turning on/off INA at runtime
using sysfs node. Additionaly, this change creates a new API power2_*,
which return 0 if ina device is turned off.

Bug 1223376
Bug 1207777

Change-Id: I0beedffa10d7e11e280e96c2c58c4dd191b87819
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/193580
(cherry picked from commit 1b530bd6b64363214580f6717b53888613cf7d4e)
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/201924
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Init 3d scaling on probe
Arto Merilainen [Sat, 2 Feb 2013 08:48:40 +0000]
video: tegra: host: Init 3d scaling on probe

sysfs control nodes are created during 3d scaling initialization.
This change reorders 3d scaling initialization to occur during device
probe so that sysfs nodes are always available.

Bug 1223355
Bug 1229151

Change-Id: I626f18c5cd409050e51f51dacfd6b36bfbcf788c
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/196736
(cherry picked from commit 5aad1f18b8d0b725e3a96bd062a565abdb5c15dc)
Reviewed-on: http://git-master/r/201782
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: camera: fix out-of-bounds read
Deepak Nibade [Mon, 18 Feb 2013 08:20:35 +0000]
video: tegra: camera: fix out-of-bounds read

fix Coverity issue
Coverity id : 22383

Bug 1046331

Change-Id: I8802e4d499b42f6c0ced28779cdebff819acf0f5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/201687
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agonetlink: remove return value check for netlink_broadcast()
Amit Kamath [Fri, 14 Dec 2012 12:19:26 +0000]
netlink: remove return value check for netlink_broadcast()

Based on commit to change return value for netlink_broadcast
commit ff491a7334acfd74e515c896632e37e401f52676
Author: Pablo Neira Ayuso <pablo@netfilter.org>
Date:   Thu Feb 5 23:56:36 2009 -0800

Change-Id: I2adcfcb9f877effa2b04db74c8e90af36604e885
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/171416
(cherry picked from commit 643a087c659273d4f138404819079125a374c405)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/201682
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: tegra: dvfs: Add sysfs entry for rail stats
Amit Kamath [Fri, 4 Jan 2013 06:31:05 +0000]
ARM: tegra: dvfs: Add sysfs entry for rail stats

bug 1042409

Change-Id: I12948a46242eb167a940b05e95d8457ff66ab2ef
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/188561
(cherry picked from commit 9d3f6767c3837facf7ed2052efbd1bbe2a0cd89b)
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/201647
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: tegra: power: Add voltage to freq convertion interface.
Amit Kamath [Mon, 17 Dec 2012 07:22:30 +0000]
ARM: tegra: power: Add voltage to freq convertion interface.

Use EDP generated tables to calculate the frequency supported at
a specified voltage

bug 1042409

Reviewed-on: http://git-master/r/171819
(cherry picked from commit b15b288083e02f0caa7644a2e01f0703b501187f)

Change-Id: Id2aa6ac61023b9c9de1810fe6a46e4a1bc70eed0
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/199964
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: ceres: enable avdd_lcd_ext for LG panel
Vineel Kumar Reddy Kovvuri [Tue, 19 Feb 2013 09:36:11 +0000]
ARM: tegra: ceres: enable avdd_lcd_ext for LG panel

Enable avdd_lcd_ext regulator for LG dsi panel.

Bug 1235181

Change-Id: I75b3aabaac084eae59108af4b1bdef9f307707e7
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/202004
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra14x: Do not put any pads into DPD
Seshendra Gadagottu [Sat, 16 Feb 2013 00:43:05 +0000]
ARM: tegra14x: Do not put any pads into DPD

Change-Id: Ia472efe1915c0ab6d378fef83f390d40c8eaae34
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/201369
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: Add CPA to t148
Alex Waterman [Tue, 19 Feb 2013 19:44:22 +0000]
ARM: tegra: Add CPA to t148

Enable changing of page attributes for t148.

Change-Id: Ib1ed3a07891961807dcdcdc84e1f2de620f05eb4
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/202096
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: Fix EMC register list
Alex Waterman [Thu, 14 Feb 2013 22:42:20 +0000]
ARM: tegra: Fix EMC register list

Fix the EMC burst register list used during the clock change. An
register was being incorrectly updated and could cause some boards
and builds to crash right after the clock change sequence.

Change-Id: I5dabcad9eb5e4b54fdbae3427a3cf67b8b2aa7b6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/200904
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Change PLLX VCO max to 2.6GHz
Kaz Fukuoka [Thu, 14 Feb 2013 20:09:13 +0000]
ARM: tegra14: clock: Change PLLX VCO max to 2.6GHz

Change-Id: Iba1f2b96862dddb05b4dc30aa14dc19a67085b6e
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/200874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dsi: Convert TE gpio to spio
Animesh Kishore [Mon, 11 Feb 2013 15:32:26 +0000]
video: tegra: dsi: Convert TE gpio to spio

- TE pin should always be spio
- Remove one-shot hacks

Bug 1232203

Change-Id: I9108bfdc0683185c280428cddd1b380fe3895910
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/199456
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: tegra: ceres: Pass TE gpio to driver
Animesh Kishore [Mon, 11 Feb 2013 15:32:01 +0000]
arm: tegra: ceres: Pass TE gpio to driver

Add TE gpio field in platform data.

Bug 1232203

Change-Id: I5e27dec40f77e8ca99337a97cb7f9b33f5bd12c1
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/199455
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agodrivers: staging: nvshm: change cache invalidation macro
Martin Chabot [Tue, 12 Feb 2013 03:59:19 +0000]
drivers: staging: nvshm: change cache invalidation macro

Reverse order of L1/L2 cache invalidation to avoid
corruption seen with low latency change on BBC

Bug 1234867

Change-Id: Id85fae3b9048952ca49658caa06d48ccad521d8f
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/199845
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoasoc:tegra: fix dam cif programming
Dara Ramesh [Mon, 11 Feb 2013 08:23:14 +0000]
asoc:tegra: fix dam cif programming

Change-Id: Ifb838ea81cd0b0f0864494b7a70e36569d934d15

Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Change-Id: I144c9994447affdca6a2b7ef8145d37826559895
Reviewed-on: http://git-master/r/200630
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoARM: tegra14: Enable CPUFREQ and CPUQUIET
Seshendra Gadagottu [Tue, 12 Feb 2013 21:44:11 +0000]
ARM: tegra14: Enable CPUFREQ and CPUQUIET

Bug 1233218

Change-Id: I52fa6f79fef119559f7ac318beabc359b2a91a99
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/200175
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoASoC: Tegra: Remove spdif device for t14x
Ravindra Lokhande [Wed, 13 Feb 2013 23:37:19 +0000]
ASoC: Tegra: Remove spdif device for t14x

Change-Id: I702275cee7485d98e4982cf86314c1726d4a6dfe
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/200577
Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoarm: tegra: la: fix fdcdwr2 offset in t148 la table
Krishna Reddy [Wed, 13 Feb 2013 22:53:37 +0000]
arm: tegra: la: fix fdcdwr2 offset in t148 la table

Change-Id: Ibcfa339446f253b7a93c0f94137734d42dabb84d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/200549
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: Correct cpu power gating stats
Seshendra Gadagottu [Wed, 13 Feb 2013 01:41:08 +0000]
ARM: tegra14: Correct cpu power gating stats

CPU0 power gating time should include corresponding
noncpu and rail(for fast cluster only) power gating time.

Bug 1215708

Change-Id: I3d562613cecd84c9261df7c343662bf35b36206d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/200305
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: clock: Initialize pll_c
Kaz Fukuoka [Tue, 12 Feb 2013 22:45:51 +0000]
ARM: tegra14: clock: Initialize pll_c

Initialize pllc and pll_c_out1 in the same way as Tegra11.

Change-Id: I63c203f04ca6cbf5ddc07c2d296ecfb7ff9ec8fa
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/200219
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Clean up
Hoang Pham [Wed, 13 Feb 2013 04:14:42 +0000]
ARM: tegra14: clock: Clean up

- Remove extra debug prints for bringup
- Change WARN_ON() to BUG_ON()

Change-Id: If7628491a2c714f27c0081863c328fc43275b606
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/200070
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Fix up PLLC IDDQ
Kaz Fukuoka [Tue, 12 Feb 2013 20:10:08 +0000]
ARM: tegra14: clock: Fix up PLLC IDDQ

Until bug 1235180 is fixed, fix PLLC IDDQ in kernel.

bug 1235180

Change-Id: Iadd3f39eaf540011a54de58301031c9eb16a00f5
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/200110
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Remove obsolete modules
Hoang Pham [Tue, 12 Feb 2013 01:36:27 +0000]
ARM: tegra14: clock: Remove obsolete modules

Change-Id: If40a437cc9a5e1d8d8e0211de966099ce73e5110
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/197264
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoregulator: max77660: Keep max77660 BUCK3/5 FPWM
Pradeep Goudagunta [Thu, 7 Feb 2013 16:35:31 +0000]
regulator: max77660: Keep max77660 BUCK3/5 FPWM

As per ES 1.0 errata BUCK3 and BUCK5 should be kept
in Force PWM mode.

Bug 1232422

Change-Id: Ia37a6cb4be4ea2e48fbf28b64116f0f02a5b192d
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/198301
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agodrivers: staging: nvshm: abort irq when BBC is crashed
Martin Chabot [Sun, 10 Feb 2013 01:24:08 +0000]
drivers: staging: nvshm: abort irq when BBC is crashed

Now irq request is aborted after 1s if not cleared

Bug 1234170

Change-Id: I10fb354f08813ee38c700f86c174ff931b64315c
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/199158
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: enable L1 prefetch
Bo Yan [Thu, 7 Feb 2013 03:10:02 +0000]
ARM: tegra14: enable L1 prefetch

Bug 1234168

Change-Id: I61d968955972f129a1be8fdccbdcdf01041d8043
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/199718
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agovideo: dc: hdmi: Fix the tdms values.
Kevin Huang [Mon, 11 Feb 2013 21:35:47 +0000]
video: dc: hdmi: Fix the tdms values.

Bug 1232412

Change-Id: I69ffc8b7c490e8886be7b068caf79352b5159541
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/199699
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoarm: tegra: Low freq EMC DFS and tables
Alex Waterman [Fri, 8 Feb 2013 07:35:59 +0000]
arm: tegra: Low freq EMC DFS and tables

This adds preliminary support for EMC DFS at low frequencies.
Frequencies supported at the moment: 12.75, 102, and 204 MHz.

This is disabled by default; however, it can be enabled at run
time through sysfs.

Change-Id: Ieb2fe2c0e0bac6acd39ce90d51a22684d9048f7c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/198682
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: kconfig: Enable TEGRA_CPU_DVFS
Seshendra Gadagottu [Mon, 11 Feb 2013 01:05:59 +0000]
ARM: tegra14: kconfig: Enable TEGRA_CPU_DVFS

Change-Id: I1203faeec8e0b9ebd28e3d58c3b53fbfc5902418
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/199237
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoARM: tegra14: clock: Add Audio dmic clocks
Hoang Pham [Sun, 10 Feb 2013 19:16:26 +0000]
ARM: tegra14: clock: Add Audio dmic clocks

Change-Id: Idaf88d74f0ba9b6dc040385b857bbef715ada9e6
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/199217
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14x: cache: Enable L2 double line fill
Seshendra Gadagottu [Sat, 9 Feb 2013 21:45:10 +0000]
ARM: tegra14x: cache: Enable L2 double line fill

Bug 1233329

Change-Id: I3cade3c1c2dea594a230b6ff28ece3576d0c388e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/199133
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agomisc: nct1008: cancel work before suspend
Bitan Biswas [Mon, 11 Feb 2013 10:42:12 +0000]
misc: nct1008: cancel work before suspend

bug 1227548

Change-Id: Ia03a335560642ae5065ea7173bb6cd22a5bdb90d
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/199392
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomipi_bif: tegra: Fix command sequence for INT_READ
Chaitanya Bandi [Mon, 11 Feb 2013 08:35:33 +0000]
mipi_bif: tegra: Fix command sequence for INT_READ

Bug 1022139

Change-Id: I924862423cdabad798973c524f74562e88dd4625
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/199307
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomipi_bif: Export mipi_bif_unregister_device
Chaitanya Bandi [Mon, 11 Feb 2013 08:28:00 +0000]
mipi_bif: Export mipi_bif_unregister_device

Bug 1022139

Change-Id: I8e2918bcebbc576b39a5d6ffac453a74c20a4e63
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/199306
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Fix FPS_SRC configuration
Pradeep Goudagunta [Wed, 6 Feb 2013 15:36:12 +0000]
regulator: max77660: Fix FPS_SRC configuration

As per datasheet if FPS_SRC is NONE then program
FPS_CNFG register 0x7f.

Bug 1233454

Change-Id: I1feffbb32d4a31ed5fbd4793cc910ddcbd228e23
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/197991
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agodrivers: staging: nvshm: protect nvshm_queue_put
Martin Chabot [Sun, 10 Feb 2013 19:39:49 +0000]
drivers: staging: nvshm: protect nvshm_queue_put

nvshm_queue_put can be called from nvshm_write
and nvshm_iobuf_free concurently on net interface
This lead to queue corruption

Bug 1234436

Change-Id: I04414f187441a00310d46c3eef83cbfa1dcb468b
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/199218
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Greg Heinrich <gheinrich@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14x: Add POR_PAD_CTRL programming
Prashant Malani [Fri, 1 Feb 2013 02:43:48 +0000]
ARM: tegra14x: Add POR_PAD_CTRL programming

Need to program PMC_POR_PAD_CTRL register during
LP0 entry as required by H/W

Bug 978296

Change-Id: Id7b8b0df9b5782af8da7c2581a32717e94776e16
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/196235
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agohwmon: ina230: add support for HPA01112
Laxman Dewangan [Tue, 5 Feb 2013 15:54:59 +0000]
hwmon: ina230: add support for HPA01112

TI HPA01112 is sw compatible with ina230. Add the module id for HPA01112.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/197499

Cherrypicked commit 8342786e71889935b6e1d4b4e467db9aa9e07b1d

Change-Id: If9c054d09c1fd8a2d29b363062a021ad0e99bb97
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/199105

5 years agohwmon: ina230: add support for HPA02149
Laxman Dewangan [Fri, 1 Feb 2013 10:57:16 +0000]
hwmon: ina230: add support for HPA02149

The TI current/power monitor device INA230 is compatible with the
HAP02149. Add module ID for the HPA02149.

This device is also compatible with INA226 and hence adding ina226
as module-id.

In this way, this driver can regsitered with the name as "ina226" or
"ina230" or "hpa02149".

bug 1218687

(CherrChange-Id: Ic67227bc6d415fd559d804f4bd97e4ea4018d872)

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196411

Change-Id: Ic67227bc6d415fd559d804f4bd97e4ea4018d872
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/199104

5 years agoARM: tegra14: clock: Fix USB clock programming
Rakesh Bodla [Fri, 8 Feb 2013 17:41:35 +0000]
ARM: tegra14: clock: Fix USB clock programming

UTMIP PLL bringup is currently not calculated based
on divided reference clock frequency. Adding the entry
for the 38.4Mhz. Also fixing the UTMIP, PLLU clock
programming.

Bug 1233108

Change-Id: I523f15f8c615ec080b888b22b165daf2e4de9bef
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/198812
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: clock: Remove requirement for boot on PLLM
Alex Frid [Wed, 6 Feb 2013 08:10:14 +0000]
ARM: tegra14: clock: Remove requirement for boot on PLLM

Changed parsing of EMC scaling table so that EMC DFS can be enabled
in case when boot EMC clock source is other than PLLM.

Change-Id: Ibb762a54b131b52498b0212c585d37d917f43922
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/197810
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoarm: tegra: la: la and ptsa updates for t14x.
Krishna Reddy [Tue, 5 Feb 2013 17:50:35 +0000]
arm: tegra: la: la and ptsa updates for t14x.

Change-Id: I31ede6f4f3e98b26f1ac1d96068cb6c0c6d0ad15
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/197530
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: T14x: Use wfi for CPU power gating
Seshendra Gadagottu [Wed, 9 Jan 2013 20:39:51 +0000]
ARM: tegra: T14x: Use wfi for CPU power gating

For T14x, use wfi instead of wfe for CPU power gating
and CPU hot un-plug.

Change-Id: Ib55832112d8eceb57f5a3035c9fbd5fb76d5359c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198587
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: clock: Initialize soc_therm clock
Kaz Fukuoka [Thu, 7 Feb 2013 01:49:22 +0000]
ARM: tegra14: clock: Initialize soc_therm clock

Initialize soc_therm clock in the same way as Tegra11.

Change-Id: Icca77970c22fac5c7b7222f435d65e20d7cdb972
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/198214
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoASoC: Tegra: Add voice call support for ceres
Ravindra Lokhande [Mon, 28 Jan 2013 16:52:30 +0000]
ASoC: Tegra: Add voice call support for ceres

Change-Id: I00739695e81ed076e963e361288e1462b49d0cde
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/194737
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stefano Sarghini <ssarghini@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agommc: core: Set HS timing if host support HS mode
rrajk [Thu, 7 Feb 2013 19:33:32 +0000]
mmc: core: Set HS timing if host support HS mode

Set high spped mode and HS timing for the card and host only when
both card and host supports high speed mode.

Change-Id: Ia9459383e9a6c6e5b3dfc1a67663534ae1ef7930
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/198462
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: tegra: clocks: Correct the se_dev name passed
Shravani Dingari [Thu, 7 Feb 2013 14:40:15 +0000]
arm: tegra: clocks: Correct the se_dev name passed

Change-Id: I87f4c99afeb8c8bdaa3199e4bdec9ac94374db85
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/198402
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomisc: tegra-cryptodev: Extend DRBG support to t148
Shravani Dingari [Thu, 7 Feb 2013 15:54:49 +0000]
misc: tegra-cryptodev: Extend DRBG support to t148

Change-Id: If8f6a47d961cdba36c8f1275a06bc6a2bf759c54
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/198422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: ceres: change csi/cilcd clock
Jihoon Bang [Fri, 8 Feb 2013 00:06:37 +0000]
ARM: tegra: ceres: change csi/cilcd clock

Remove cilcd clock in T148.
Change max clock for csi to 102MHz from 100MHz.

Bug 1180011

Change-Id: Id12ec0039477c6cf1f4cedd34b54382e1578a39b
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198572
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agomedia: video: tegra_camera: remove cilcd
Jihoon Bang [Fri, 8 Feb 2013 00:05:10 +0000]
media: video: tegra_camera: remove cilcd

Remove cilcd clock.
T148 doesn't need cilcd.

Bug 1180011

Change-Id: I25815170538671a0ab89577e61422c70c89be6e9
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198571
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: max77660: add set sim config
shawn joo [Thu, 7 Feb 2013 09:04:06 +0000]
regulator: max77660: add set sim config

initialize sim1, sim2 config.
BAT_REMOVED is ignored and it should be enabled if requried.
if BAT_REMOVED is enabled, e1680' sim does not work correctly.
SIM detect debounce is calculated with count 16.

Bug 1177376

Change-Id: I118f711abc073044f976aac9f2c493d8cb30fae3
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/198304
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14x: kconfig: Remove relic ARM_SMP_TWD
Seshendra Gadagottu [Thu, 7 Feb 2013 22:01:11 +0000]
ARM:  tegra14x: kconfig: Remove relic ARM_SMP_TWD

Change-Id: I4aff4b9a1e96f8d0c59a34b4ddc1954891df6733
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198522
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: cldvfs: Update tune parameters
Seshendra Gadagottu [Thu, 7 Feb 2013 21:58:23 +0000]
ARM: tegra14: cldvfs: Update tune parameters

Updated new safe tune0 parameter for cldvfs

Change-Id: Ia07974d6d56d07119718709260e33ec7dd63710f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoARM: tegra14: clock: Fix max rate
Hoang Pham [Thu, 7 Feb 2013 20:31:01 +0000]
ARM: tegra14: clock: Fix max rate

Fix max rate for clocks: owr, clk_out_1, clk_out_3 and clk72mhz

Change-Id: I247de8d993673c99e539d7a5ecd688c1b3c3afe3
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/198194
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: remove PHERIPH_NO_ENB in vi_sensor2
Jihoon Bang [Thu, 7 Feb 2013 02:52:39 +0000]
ARM: tegra: remove PHERIPH_NO_ENB in vi_sensor2

Bug 1180011

Change-Id: I4f02f668d763b3cd91ff21f9748327eb2348c85f
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198231
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agomedia: video: tegra: enable t14x config
Sudhir Vyas [Mon, 4 Feb 2013 19:53:19 +0000]
media: video: tegra: enable t14x config

Bug 1180011

Change-Id: Ide51c3927f8699b8d186f6f3eda87609c1d872a1
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197082
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra: ceres: Enable vim2_clk for camera
Sudhir Vyas [Tue, 5 Feb 2013 13:25:19 +0000]
ARM: tegra: ceres: Enable vim2_clk for camera

Sensor input clock (cam_mclk) is sourced from vi_sensor2
on ceres, which needs vim2_clk enable.

Bug 1180011
Bug 1180015

Change-Id: I061d43926eaa378e44cbdd00f93fff6b8210a2ec
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197467
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: dvfs: Add core dvfs safe entries
Prashant Malani [Thu, 7 Feb 2013 05:03:00 +0000]
ARM: tegra14: dvfs: Add core dvfs safe entries

Add safe entries for camera and display modules.

Bug 1217326

Change-Id: Id0c25d1f4070f7ff13d040c951259b22ca524180
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/198251
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agommc: core: don't modify ext csd raw fields
rrajk [Thu, 7 Feb 2013 16:45:55 +0000]
mmc: core: don't modify ext csd raw fields

Not touching raw fields in ext csd register in order to not break
the raw ext csd comparison check

Change-Id: I7ab01cd280288c5e7ea319d0e87b4acd1fd1fdf0
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/198429
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomfd: max77660: Remove Global LPM config
Pradeep Goudagunta [Thu, 7 Feb 2013 06:45:13 +0000]
mfd: max77660: Remove Global LPM config

Max77660 doesn't support Global low power mode configuration.

Change-Id: Ife3211d6843b21f2b126d5bbe9fd17baed55eca6
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/198266
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopinctrl: max77660: add init flag for pins which is configured as gpio
Laxman Dewangan [Thu, 7 Feb 2013 13:15:23 +0000]
pinctrl: max77660: add init flag for pins which is configured as gpio

If any pin is configured as gpio and if it is require in gpio output
mode then provide provision to set the initial state of the pins.

bug 1232806

Change-Id: Ibdf34518a22c3d6b3c02d86f10186fc4be89bab4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198371

5 years agoregulator: fix disable_dvfs for buck
shawn joo [Wed, 6 Feb 2013 09:11:52 +0000]
regulator: fix disable_dvfs for buck

fix Disable DVFS for buck, POR is enable.
this feature will be set on board power.

Bug 1231220
Bug 1230814

Change-Id: I25176d733a38b84ec32d43734bfec5aee2e4e50f
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/197826
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm: tegra: tegra_bb: clock enable
shawn joo [Tue, 5 Feb 2013 06:25:05 +0000]
arm: tegra: tegra_bb: clock enable

BBC clock enables on tegra_bb.
remove BBC clock setting from clk init table.

Change-Id: I002cc2e4408a03a1065dcd6dd563628e7c6a096c
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/197324
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: max77660: fix voltage range for buck4
shawn joo [Thu, 7 Feb 2013 00:13:04 +0000]
regulator: max77660: fix voltage range for buck4

buck4 voltage range is 0.6 ~ 1.5v.
fix min voltage from 0.8 to 0.6.

Bug 1177376

Change-Id: I7ded8fbfe46d3e749e04008becee3d56f7f0d2f4
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/198178
Reviewed-by: Neil Patel <neilp@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: dvfs: Fix voltage resolution issue
Seshendra Gadagottu [Wed, 6 Feb 2013 22:05:44 +0000]
ARM: tegra: dvfs: Fix voltage resolution  issue

Maximum volatage should be in steps of PMIC
voltage resolution.

Change-Id: I78bc8d7665b417e924895816eafc0d1ffe1eb1c2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198135
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoASoC: Change codec_name in dai_link
Ravindra Lokhande [Wed, 6 Feb 2013 08:38:16 +0000]
ASoC: Change codec_name in dai_link

For T14x codec_name in dai_link is changed.

Change-Id: I7addef240355b2170f23a5447df83d23ee5c5ce4
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/197813
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agomfd: max77660: do not write invalid bits in GLBLCNFG0
Laxman Dewangan [Wed, 6 Feb 2013 19:27:01 +0000]
mfd: max77660: do not write invalid bits in GLBLCNFG0

As per ES1.0 errata, do not write any invalid bits/value in the
GLBLCNFG0 register.

bug 1228630

Change-Id: Ib4442ce9f89cce984c58039a6f26aa4fd53b1493
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198068
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Disable auto discharge of LDO1 in normal mode
Laxman Dewangan [Wed, 6 Feb 2013 19:25:44 +0000]
regulator: max77660: Disable auto discharge of LDO1 in normal mode

As per ES1.0 errata, disable the auto discharge of LDO1 when LDO1 in
normal mode.

bug 1228630

Change-Id: I92006c77d9c6dd97b3a2865027cb89b6a46a8247
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198067

5 years agogpio: max77660: do not implement debaunce for GPIO1 for ES1.0
Laxman Dewangan [Wed, 6 Feb 2013 19:24:16 +0000]
gpio: max77660: do not implement debaunce for GPIO1  for ES1.0

As per ES1.0 errata, debaunce of GPIO1 does not work. Returning the error
in this case.

bug 1228630

Change-Id: I836951d6e9cf7d11679226abb2b4add7f4f03268
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198066

5 years agostaging: iio: adc: max77660: ignore ADC0 channel for ES1.0
Laxman Dewangan [Wed, 6 Feb 2013 19:21:46 +0000]
staging: iio: adc: max77660: ignore ADC0 channel for ES1.0

As per ES1.0 errata, do not do ADC conversion for ADC0 channel.

bug 1228630

Change-Id: I7602ce0fdbef9acbd2c3ecd7da770126c7571212
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198065

5 years agomfd: max77660: reflect correct ES minor version
Laxman Dewangan [Wed, 6 Feb 2013 17:42:47 +0000]
mfd: max77660: reflect correct ES minor version

CID5 Register tells direct ES minor version and so no need to
add any value in this minor version.

ES1.0 is device revision 1.
ES1.1 is device revision 2.
ES1.2 is device revision 3.

Also prints all CIDs register and add api to direct check whether device is
ES1.0 or not to implement the ES1.0 erratas.

Change-Id: Ie1bddfe936cafd20213bdc72f8238c15fc39607c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198064

5 years agoarm: tegra: ceres: Fix backlight for smart panel
rrajk [Wed, 6 Feb 2013 15:29:22 +0000]
arm: tegra: ceres: Fix backlight for smart panel

pinmux and platform data changes

Change-Id: I86c29cf47b4cc2f1ad667cee38a97b1ba26aef37
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/197989
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dc: WAR of SHIFT_CLK_DIV update.
Kevin Huang [Tue, 29 Jan 2013 23:12:52 +0000]
video: tegra: dc: WAR of SHIFT_CLK_DIV update.

Bug 1225291
Bug 1161019

Change-Id: I699e64a1f6464eeddae5275a55cd2b285badc698
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/195272
(cherry picked from commit 880d4dc1ce348e66509f6cb50fcd1683856e0f26)
(updated cherry-pick to correct build failure)
Reviewed-on: http://git-master/r/196541
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agomfd: max77660: add api for getting version
Laxman Dewangan [Wed, 6 Feb 2013 16:17:54 +0000]
mfd: max77660: add api for getting version

Read CID5 register for getting device Revision and API to get
revision number which can be used by different sub modules of
this device.

Change-Id: Ie9394d4e36b4b8e6e15fa4af7cbebaafc3fb7e42
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198013

5 years agoARM: tegra: Enable cl_dvfs clocks by default
Chaitanya Bandi [Wed, 6 Feb 2013 14:49:01 +0000]
ARM: tegra: Enable cl_dvfs clocks by default

cl_dvfs clock is required on for PWR_I2C

Bug 1230603
Bug 1231822

Change-Id: Ic1e41e7204b583640fb0ef782e6efb583a21aa03
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/197982
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomedia: video: tegra: Enable vim2_clk for cam_mclk
Sudhir Vyas [Tue, 5 Feb 2013 13:13:18 +0000]
media: video: tegra: Enable vim2_clk for cam_mclk

Program vim2_clk, which is needed to enable cam_mclk on
t148 ceres.

Bug 1180011
Bug 1180015

Change-Id: I2593a35fc0ab9c8ab4ff8ea1f5d0e259ec2da0db
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197466
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: clock: Fix vi_sendor and cam_mclk
Hoang Pham [Wed, 6 Feb 2013 06:43:24 +0000]
ARM: tegra14: clock: Fix vi_sendor and cam_mclk

- cam_mclk is enable bit of vi_sensor
- cam-mclk2 is enable bit of vi_sensor2

Change-Id: I2cb483d2651e09129c29160ef4ca1bcdee86cfb4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/197759
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Fix order in clk_init_table
Kaz Fukuoka [Tue, 5 Feb 2013 02:58:06 +0000]
ARM: tegra14: clock: Fix order in clk_init_table

Change-Id: I511bfe90acd919a0184069eff91180f032607c4d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/197246
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: dvfs: Add safe dvfs table for isp
Kaz Fukuoka [Tue, 5 Feb 2013 03:13:50 +0000]
ARM: tegra14: dvfs: Add safe dvfs table for isp

On Tegra14, isp became independent from vi.

Change-Id: I16346fb70ee709f0534b1d7b0cf79f509ef4556d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/197252
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agodrivers: staging: nvshm: Add flow control on TX
Martin Chabot [Tue, 29 Jan 2013 12:49:04 +0000]
drivers: staging: nvshm: Add flow control on TX

Flow control on TX
Change spin lock in iobuf alloc/free for irq use

Bug 1226213
Bug 1227082

Change-Id: Ic5fa063bc43689b1d543b8cbd81207b5aee1f04f
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/195115
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Greg Heinrich <gheinrich@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoregulator: max77660: register all regulators
Laxman Dewangan [Sat, 2 Feb 2013 08:23:14 +0000]
regulator: max77660: register all regulators

Whether the regulator plaform data is available or not for max77660 regulators,
register all regulator of max77660.

Change-Id: Id71411a6d7909720e1c0c2070c9a636a89604b56
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196735
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Pass regulator platform data pointers in array
Laxman Dewangan [Sat, 2 Feb 2013 08:06:38 +0000]
regulator: max77660: Pass regulator platform data pointers in array

In place of passing the limited regulator platform data and number
of platform data, pass platform data of all regulators in array. The
regulator id will direct relate to index of array. If any regulator is
unused in the given platform then NULL can be passed in place of valid
pointer.

Change-Id: Ib9f896e0b2f71c120da3a0348c00bfd8eb41862e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196734

5 years agomfd: max77660: move regulator and battery charger platform data to core
Laxman Dewangan [Tue, 5 Feb 2013 12:53:50 +0000]
mfd: max77660: move regulator and battery charger platform data to core

It is require to reference the definition from regulator header
to core header, it is better to keep all definition in one place
in place of scattering informations.

Change-Id: Ia418a40d75c408887ea96f0efa7445e929c88b00
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196733