5 years agoALC5639: Combining all Realtek tweaks
Rene Houle [Wed, 30 Jul 2014 08:40:18 +0000]
ALC5639: Combining all Realtek tweaks

Cache sync optimization
Fix for pop on speaker
Class-D Amplifier tuning
Update provided by Realtek

Change-Id: Ic445ecbd7398d03a9b9bc59f46b5d75d921ced77
Signed-off-by: Rene Houle <rhoule@nvidia.com>
Reviewed-on: http://git-master/r/453165
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manoj Gangwal <mgangwal@nvidia.com>
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoplatform: tegra: padctl: fix usb_calib fuse
Joy Wang [Thu, 18 Sep 2014 02:41:19 +0000]
platform: tegra: padctl: fix usb_calib fuse

Need to use USB_CALIB[28:22] to program utmi port2
HS_CURR_LEVEL.

Change-Id: If5abcbe4f81418a6a65efcea5b96870ce67f21a0
Signed-off-by: Joy Wang <joyw@nvidia.com>
Reviewed-on: http://git-master/r/500101
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agomtd: ubi: Remove incorrect assertion in ubi
Manoj Chourasia [Thu, 24 Apr 2014 12:07:50 +0000]
mtd: ubi: Remove incorrect assertion in ubi

mtd->writesize varies w.r.t NOR flash, the assert in ubi/build.c is incorrect.
Remove the meaningless assert in ubi layer.

bug 1492724
bug 1528224

Change-Id: Ibf658e02a021823a10825f0c2903ee75d2b99140
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Signed-off-by: Bharath H S <bhs@nvidia.com>
Reviewed-on: http://git-master/r/400870
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoata: ahci: do not set PLLE_ENABLE_T210 bit
Sang-Hun Lee [Thu, 18 Sep 2014 01:40:55 +0000]
ata: ahci: do not set PLLE_ENABLE_T210 bit

 - Do not set PLLE_ENABLE_T210 bit as it causes a Foster boot failure
   until the issue is root caused

Bug 1555570

Change-Id: I30ec813dfdc0abcb522f6219815aa5fe401bfef8
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/500070
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoata: ahci: do not use 7bit align detection
Sang-Hun Lee [Mon, 15 Sep 2014 22:47:59 +0000]
ata: ahci: do not use 7bit align detection

Bug 200035882

Change-Id: I9db4e416a65710a6411918addd7a4d82009007fd
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/499024
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tao Xie <txie@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agogpu: nvgpu: gm20b: Require rework for DVFS and rg
Arto Merilainen [Thu, 18 Sep 2014 08:38:08 +0000]
gpu: nvgpu: gm20b: Require rework for DVFS and rg

Boards require a rework to make railgating and DVFS work realiably.
The information whether the board has been reworked or not will be
available on DTS.

This patch adds a DTS check to the GPU driver initialisation. If the
rework information is not available (or the rework has been marked as
disabled), railgating and DVFS are disabled.

Bug 1555485

Change-Id: Ie86fe35fb94377403472faffcbcaec645b6e40d9
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/500218
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoASoC: tegra-alt: don't init ADSP at boot
Viraj Karandikar [Tue, 16 Sep 2014 11:23:31 +0000]
ASoC: tegra-alt: don't init ADSP at boot

Do not initialize ADSP using work queue. Initialization will be
done from userspace by setting mixer control "ADSP init" to 1.

Bug 1552863

Change-Id: I0fd435b581a4fb9e851e8505e451c52cf0746df2
Signed-off-by: Viraj Karandikar <vkarandikar@nvidia.com>
Reviewed-on: http://git-master/r/499313
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

5 years agogpu: nvgpu: Clear invalid method
Terje Bergstrom [Thu, 18 Sep 2014 11:55:21 +0000]
gpu: nvgpu: Clear invalid method

Invalid method needs to be cleared in gm20b to prevent getting same
interrupt again.

Change-Id: I4d83d1a27e5c711b5d82b95552be84d5f16a13e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500286

5 years agoARM64: Tegra: Add PowerMon DT node for E2220
Darren Sun [Wed, 17 Sep 2014 12:36:00 +0000]
ARM64: Tegra: Add PowerMon DT node for E2220

Bug 200030812
Change-Id: I07f4de6f0d8f0f6eb8290b36fa3d64f63da3fcb8
Signed-off-by: Darren Sun <darrens@nvidia.com>
Reviewed-on: http://git-master/r/499789
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Deepak Nibade <dnibade@nvidia.com>

5 years agoARM: tegra: usb_phy: update offsets for calib setup
Rakesh Bodla [Fri, 11 Jan 2013 04:34:50 +0000]
ARM: tegra: usb_phy: update offsets for calib setup

Update calibration setup offsets. This is different
for different controllers.

Bug 1216168

Change-Id: Ice55cc62672dce4097ce7caf60d5572af60877a6
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/500178
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agogpu: nvgpu: FE object table has 4 elements
Terje Bergstrom [Thu, 31 Jul 2014 11:33:32 +0000]
gpu: nvgpu: FE object table has 4 elements

Restrict reading of FE object table to the number of entries
available.

Change-Id: I11275ecd14e53f0b763d00d65042adb4b1e8ae6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/449306

5 years agogpu: nvgpu: Use polling to detect runlist switch
Terje Bergstrom [Thu, 18 Sep 2014 09:01:18 +0000]
gpu: nvgpu: Use polling to detect runlist switch

Runlist event is not sent in gm20b for updated runlist. Polling is
the preferred way also for gk20a.

Bug 1555239

Change-Id: I60de084db69f848f63451f1f3078f183ca51ba50
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500241

5 years agoasoc: codec: audience: update HPL and HPL_CTRL reg
Dara Ramesh [Thu, 18 Sep 2014 11:34:07 +0000]
asoc: codec: audience: update HPL and HPL_CTRL reg

- update cached HP_L gain and HPL_CTRL to HW,
 firmware resets this register space to detecting
 wired accessory.

Change-Id: I2a0db5699785bad2a5727ab14e6dbd794410dfd0
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/500281
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>
Tested-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agoasoc: codec: audience: Don't clear cachedcmd_list
Dara Ramesh [Thu, 18 Sep 2014 06:13:50 +0000]
asoc: codec: audience: Don't clear cachedcmd_list

Don't clear cachedcmd_list from Algorithm kcontrol

The cachedcmd_list now holds the refcount information for each MUX which
is set twice. If it is cleared from the Algorithm kcontrol when it is
set to Off, it would erase the refcount information as well which is
required to update the power state of DAPM widgets when refcount reaches
to zero.

Added an extra check for skipping the power state update for DAPM
widget. In case of dragon board XML, if the playback is running and the
capture is started via Sound Recorder app, the MUXes are not set twice
as they are already set. But the disable sequence of playback gets
executed. In this case, the refcount of all the MUXes would be
decremented in disable sequence, and that would break the DAPM route
even if the TX (capture) stream is still active. The extra check of
active streams before updating the power state of DAPM widget will keep
the DAPM route as it is.

bug 200037978

Change-Id: I397a22e59d95fb4474d93aaf8e5a7def0d24c222
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/500174
Reviewed-by: Viraj Karandikar <vkarandikar@nvidia.com>
Tested-by: Viraj Karandikar <vkarandikar@nvidia.com>
Reviewed-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>
Tested-by: Vinod Subbarayalu <vsubbarayalu@nvidia.com>

5 years agogpu: nvgpu: implement poll() for semaphores
Konsta Holtta [Wed, 10 Sep 2014 14:23:31 +0000]
gpu: nvgpu: implement poll() for semaphores

Add poll interface and control ioctls for waiting for GPU job completion
via semaphores.

Poll on a gk20a channel file waits for events from pending semaphore
interrupts (stalling) of that channel. New ioctls enable and disable the
events, and clear a single interrupt event so that next poll doesn't
wake up for it again.

Bug 1528781

Change-Id: I5c6238966b5d0900c8ab263c6a7f8f2611901f33
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/497750
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoRevert "[mods] Window bandwidth check w/o ISO mgr support"
Terje Bergstrom [Fri, 19 Sep 2014 05:09:21 +0000]
Revert "[mods] Window bandwidth check w/o ISO mgr support"

This reverts commit d494a770aec5e0420129c2668621f63d2486463f. It causes build failure.

Change-Id: I072001eb52c81df85e957f25a638fca761c7c5b3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500555

5 years agoRevert "[TEMP] arm:tegra:t210: SDMMC3 fix for power detect"
Arto Merilainen [Thu, 18 Sep 2014 10:39:54 +0000]
Revert "[TEMP] arm:tegra:t210: SDMMC3 fix for power detect"

This reverts commit 2e9d2712f8062373d282718108f62f6f41c2a73c.

Bug 1555652
Bug 200038778

Change-Id: I898f18b9e975ba0dcf43f00b760c0a162c9b1ad8
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/500265
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm64: config: tegra21: enable vi-i2c support
Charlie Huang [Wed, 17 Sep 2014 22:08:50 +0000]
arm64: config: tegra21: enable vi-i2c support

the CONFIG flags were wiped out by other team, re-enable them.

bug 1546954

Change-Id: Id19e7bcfafd5c2378e86c6bca694ed3d2e3b16a1
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/499966
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM64: dts: tegra: enable y cable on loki
Rakesh Babu Bodla [Wed, 17 Sep 2014 15:43:58 +0000]
ARM64: dts: tegra: enable y cable on loki

Enable y cable on loki.

Bug 200034528

Change-Id: I96efd324611b984c5a20a27256ff3bc13fc59860
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/499845
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agogpu: nvgpu: ioctl support flags in gpu characteristics
Konsta Holtta [Fri, 5 Sep 2014 07:59:05 +0000]
gpu: nvgpu: ioctl support flags in gpu characteristics

Expose supported nvgpu ioctls to userspace via bits in the flags field
of nvhost_gpu_characteristics; currently define two bits for special
memory allocation support.

Bug 1539747

Change-Id: I1bc9333b12825d07a00b7a4136ae9d35816a5855
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/495942
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agousb: otg: tegra: support y cable through extcon
Rakesh Babu Bodla [Wed, 17 Sep 2014 15:15:38 +0000]
usb: otg: tegra: support y cable through extcon

Add support for y cable through extcon device
notifications.

Bug 200034528

Change-Id: Ibb225154c9b1ab55e53a1c6c2f3a910dbb5b3bfc
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/499844
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agovideo: tegra: host: Move actmon init to acm
Arto Merilainen [Wed, 17 Sep 2014 07:08:38 +0000]
video: tegra: host: Move actmon init to acm

This patch removes unnecessary code duplication from Falcon drivers
by moving the actmon hw initialisation inside nvhost_acm.c

Bug 200006528

Change-Id: I5587f89378433a2a62445d5d389390f28efe55f4
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/499695

5 years agovideo: tegra: host: Re-use callbacks
Arto Merilainen [Wed, 17 Sep 2014 06:43:21 +0000]
video: tegra: host: Re-use callbacks

This patch removes nvhost_module_resume() function and modifies
the callbacks to use nvhost_module_finalize_poweron() instead. The
functions are doing the same thing in practise. In addition, this
patch modifies nvhost_module_suspend() to use
nvhost_module_preparep_poweroff() to avoid code duplication.

Change-Id: Ic4ce948ce2fd87f86e3e487a5a615a21d972c3af
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/499694
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM64: dts: tegra: Enable ACA cables detection
Mallikarjun Kasoju [Wed, 17 Sep 2014 14:07:19 +0000]
ARM64: dts: tegra: Enable ACA cables detection

Enable ACA RID-A, RID-B, RID-C cable detection.

Bug 200035165

Change-Id: Ide492110b9c2c3c11abd9dc38889284a4c91dfd4
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/499829
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: t210: Serialize VIC
Arto Merilainen [Mon, 15 Sep 2014 13:42:28 +0000]
video: tegra: host: t210: Serialize VIC

VIC is not handling correctly cases where we queue huge amount of
work on VIC. Therefore, serialize VIC until the issue has been
root caused.

Bug 200036888

Change-Id: I514d65e180eca58f44078863fa870d6706da4672
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/498873

5 years agoextcon: cable-xlate: prints the cable name
Laxman Dewangan [Wed, 17 Sep 2014 13:34:12 +0000]
extcon: cable-xlate: prints the cable name

Print the name of the cable which is attached for good
debug prints.

bug 200038344

Change-Id: I424ee65843643f910b23a8265eb2897eded1884d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/499809
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agogpu: nvgpu: Allow skipping regops addr validation
Terje Bergstrom [Tue, 16 Sep 2014 08:27:59 +0000]
gpu: nvgpu: Allow skipping regops addr validation

If allow_all is set, skip regops address validation.

Change-Id: I42d6c9f1a5d2c8d9bc6783adff5f6048c45350f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/499221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

5 years agogpu: nvgpu: Fix L2 bypass to work in gm20b
Terje Bergstrom [Mon, 15 Sep 2014 10:22:04 +0000]
gpu: nvgpu: Fix L2 bypass to work in gm20b

L2 bypass registers have moved in gm20b. Move the code to
ltc_common.c, which gets compiled once per chip version.

Change-Id: I0ab4dd03c78b8ad8abc7a7b18c094b6002827587
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/499220
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

5 years agovideo: tegra: host: Coverity fixes
Pavitrakumar [Tue, 16 Sep 2014 05:13:40 +0000]
video: tegra: host: Coverity fixes

Freed fw_name before returning from nvdec_get_fw_name
if the platform is qt or linsim

Coverity ID 27970
Coverity ID 27968

Bug 200020218

Change-Id: Ib504b0baf05c891354536fd50c2585113160b854
Signed-off-by: Pavitrakumar <pavitrak@nvidia.com>
Reviewed-on: http://git-master/r/499150
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agothermal: Fixed return expression in void function
Amit Sharma [Wed, 17 Sep 2014 14:08:35 +0000]
thermal: Fixed return expression in void function

Remove return expression from the following function:
- void fan_update_target_pwm(struct fan_dev_data *fan_data, int val)

Bug 200032218

Change-Id: Id89f2f3fdb29847fc6f38019dd9a8ee1ab4a02d0
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/499828
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM64: config: Enable SELinux on Tegra21
Graziano Misuraca [Mon, 8 Sep 2014 23:41:03 +0000]
ARM64: config: Enable SELinux on Tegra21

Bug 200034182

Change-Id: I7e131ef51103b48720edb88daf3e789be10ee0c5
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/496705
Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Tested-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agommc: sdhci: Fix enabling interrupts
Naveen Kumar Arepalli [Tue, 16 Sep 2014 12:05:18 +0000]
mmc: sdhci: Fix enabling interrupts

-Fix enabling interrupts.
-After tuning only SDHCI_INT_DATA_AVAIL is being enabled
as host->ier is updated to SDHCI_INT_DATA_AVAIL.
-Use a local varible to read the SDHCI_INT_ENABLE.

Bug 200037833

Change-Id: I893de7816b855518b7d3c407faa7edfadf34e998
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/499295
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Andy Sobczyk <asobczyk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: tegra: vcm30t124: correct UHS mask property name
Joshua Cha [Wed, 17 Sep 2014 07:28:27 +0000]
arm: tegra: vcm30t124: correct UHS mask property name

UHS mask DT property is uhs-mask.

Bug 1527003

Change-Id: I5182a0e63e943c47b1c5d1f903f35a619c8e71b2
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/499677
Reviewed-by: Seshagiri Holi <sholi@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agotegra: adsp : actmon: fix adsp actmon device for dfs
Puneet Saxena [Sat, 13 Sep 2014 11:15:31 +0000]
tegra: adsp : actmon: fix adsp actmon device for dfs

It tunes adsp actmon parameteres to scale adsp freq
performance side.

Adds "adsp_actmon" debugfs node under "/d/tegra_ape"
to tune actmon parameters

bug 200007507

Change-Id: Id1f47015655f6ee1e1e19f793923fd7047f8b4e2
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/498618
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years ago[TEMP] arm:tegra:t210: SDMMC3 fix for power detect
David Dastous [Sat, 30 Aug 2014 00:05:42 +0000]
[TEMP] arm:tegra:t210: SDMMC3 fix for power detect

Bug 1531762
Bug 1548669

Change-Id: I1c8056e0736f03fa259c8c9d02e7dd23e3d46706
Signed-off-by: David Dastous <ddastoussthi@nvidia.com>
Reviewed-on: http://git-master/r/494144
(cherry picked from commit fb8064dbfe33230d1841869bd487ad993351180b)
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/496305
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>

5 years agoclock: tegra21: Update PLLDP settings
Alex Frid [Wed, 17 Sep 2014 05:03:43 +0000]
clock: tegra21: Update PLLDP settings

Updated characterized PLLDP dividers configuration and spread spectrum
settings.

Bug 1548117

Change-Id: I360d8090970790d40bcf3f2be674212acb5b7780
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499629
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years ago[mods] Window bandwidth check w/o ISO mgr support
Rohan Sreeram [Mon, 15 Sep 2014 23:21:08 +0000]
[mods] Window bandwidth check w/o ISO mgr support

MODS kernel driver queries DC and EMC driver to
figure if a window configuration is possible at
the current EMC clock

Change-Id: I5012094c70597b5151a00c2fcce7511bfd8f9330
Signed-off-by: Rohan Sreeram <rsreeram@nvidia.com>
Reviewed-on: http://git-master/r/498577
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agotegra: ivc: fix many races and vulnerabilities
Peter Newman [Tue, 12 Aug 2014 20:38:38 +0000]
tegra: ivc: fix many races and vulnerabilities

The contents of any data structure placed in shared memory that can be
written by an untrusted peer must be carefully validated before they can
be used. This change adds a minimal set of checks needed to prevent
accesses from being made outside of the cbuf area.

Use the ACCESS_ONCE() macro to enforce precise access to shared data
structures. We can only validate a data structure copied out of shared
memory, otherwise the compiler will incorrectly assume that valid data
will stay valid.  This should also prevent any unexpected merging or
re-ordering of accesses to the cbuf structure which could allow the
other side to briefly see the cbuf structure in a non-sequentially
consistent state.

To further ensure atomic accesses to counters, add alignment checks when
placing the cbuf data structures, because misaligned accesses are not
guaranteed to be performed atomically on ARM.

Finally, add several missing barriers and remove many that were not
necessary. Also, add comments explaining the purpose of all barriers, as
is required by the Linux kernel commit guidelines.

Bug 1539562
Bug 1535083

Change-Id: Icb1c8f27cc67125be9060bfe4a280b2b63323b5d
Signed-off-by: Peter Newman <pnewman@nvidia.com>
Reviewed-on: http://git-master/r/489063
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bahadir Balban <bbalban@nvidia.com>
Tested-by: Bahadir Balban <bbalban@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoarm64: t210: dts: make vii2c's reg entry 64bit
Tom Cherry [Sat, 13 Sep 2014 00:54:43 +0000]
arm64: t210: dts: make vii2c's reg entry 64bit

Change-Id: Ic18866baf7449d6a62d5578b5fe8fd9f03155e3b
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/498575
Tested-by: Eric Werness <ewerness@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Tested-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agotegra: thermal: specify fuse war as signed 32b
Diwakar Tundlam [Sat, 13 Sep 2014 00:56:18 +0000]
tegra: thermal: specify fuse war as signed 32b

Specify fuse correction coefficients as signed 32b values to
support +ve and -ve correction coefficients.

Also changed code to use a loop to iterate over individual tsoscs.

Change-Id: I046e6471e135fa7b402f533d53730e35ae450098
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/498578

5 years agodvfs: tegra21: Check speedo revision
Alex Frid [Sun, 14 Sep 2014 01:55:46 +0000]
dvfs: tegra21: Check speedo revision

Read speedo revision from spare fuses. Use fused speedo values only
for revisions 2 and above; otherwise use hard-coded values.

Change-Id: I05770b859bb844d7f17d1ce6111eb5e9c7341226
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499171
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agogpu: nvgpu: Add GM20B GPCPLL h/w definitions
Alex Frid [Fri, 12 Sep 2014 04:05:29 +0000]
gpu: nvgpu: Add GM20B GPCPLL h/w definitions

Expanded GM20B GPCPLL definitions of DVFS registers.

Bug 1450787

Change-Id: I51d049be70badfedd8c451019b10770b4fb31e80
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499487
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agotegra: fuse: Add GPCPLL ADC calibration interface
Alex Frid [Tue, 16 Sep 2014 03:55:43 +0000]
tegra: fuse: Add GPCPLL ADC calibration interface

Added interface to read GPCPLL ADC calibration parameters on Tegra21
platform.

Change-Id: I33f162d3cfb0f5939a774314e72540cb6e91bf11
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499486
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoclock: tegra21: Enable PLLE SS configuration
Alex Frid [Wed, 17 Sep 2014 04:33:56 +0000]
clock: tegra21: Enable PLLE SS configuration

Enabled PLLE spread spectrum configuration with characterized settings.

Bug 1548117

Change-Id: I303016123a130e1dc79ac3f59cb051b5afc7b6a9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499615
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm64: tegra: Fix USB/ETH regulator for Foster
Aly Hirani [Mon, 15 Sep 2014 17:33:09 +0000]
arm64: tegra: Fix USB/ETH regulator for Foster

The enable pins for the usb1/usb2/usb3 are meant to be driven in an
open-drain configuration. Not putting the pin in an open configuration
meant that on 50% of the boards, we won't be able to enable the
regulator given the VGS of the FET > 1.8 V

Bug 1550714

Change-Id: Ibc355efd363c1c97ea56facddabca174250cc8d0
Signed-off-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-on: http://git-master/r/497086
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>

5 years agogpu: nvgpu: gm20b: enable elpg
Seshendra Gadagottu [Tue, 16 Sep 2014 22:04:45 +0000]
gpu: nvgpu: gm20b: enable elpg

Enable Engine Level Power Gating power
feature for gm20b.

Bug 1552466

Change-Id: Ief9cf648270412f7a9f6f5b28a1fce08effdd670
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/499541
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: gm20b: enable slcg
Seshendra Gadagottu [Tue, 16 Sep 2014 22:01:39 +0000]
gpu: nvgpu: gm20b: enable slcg

Enable Second Level Clock Gating power
feature for gm20b.

Bug 1552466

Change-Id: I34a3d93a98f7b784ab26fb7940d50db262b35f57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/499540
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: gm20b: enable elcg
Seshendra Gadagottu [Tue, 16 Sep 2014 21:59:08 +0000]
gpu: nvgpu: gm20b: enable elcg

Enable Engine Level Clock Gating power
feature for gm20b.

Bug 1552466

Change-Id: I6f0bc565700bfd183c703fc35389188906842a4e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/499539
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoASoC: tegra-alt: Spinlock in ISR
Dipesh Gandhi [Wed, 17 Sep 2014 04:42:19 +0000]
ASoC: tegra-alt: Spinlock in ISR

I2S driver has shared interrupt routine for
all the i2s devices. This requires addition of
spinlock for critcal section protection.

Bug 200008382

Change-Id: I4f113cddf63a942711960c00702a0db41f0e3d41
Signed-off-by: Dipesh Gandhi <dipeshg@nvidia.com>
Reviewed-on: http://git-master/r/499623
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Pai <npai@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

5 years agoASoC: tegra-alt: Fix byte mask for AMX for 512fs
Arun Shamanna Lakshmi [Wed, 17 Sep 2014 06:17:59 +0000]
ASoC: tegra-alt: Fix byte mask for AMX for 512fs

Bug 1540137

Change-Id: I51d006721407e2bf66d2c9dd461ca228754a9079
Signed-off-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Reviewed-on: http://git-master/r/499649
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Justin Kim (SW-TEGRA) <juskim@nvidia.com>

5 years agogpu: nvgpu: gm20b: enable blcg
Seshendra Gadagottu [Tue, 16 Sep 2014 20:04:39 +0000]
gpu: nvgpu: gm20b: enable blcg

Enable Block Level Clock Gating power
feature for gm20b.

Bug 1552466

Change-Id: Ibdd611bc2932ae9c3ce2c0d9eb847fa46a3759c7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/499538
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoplatform: tegra: call shutdown_core only if any other cpu online
Allen Yu [Wed, 17 Sep 2014 02:46:32 +0000]
platform: tegra: call shutdown_core only if any other cpu online

Change-Id: Ib85aa00512a814b3457a61319f5cbbbd640baded
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/499596
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agogpu: nvgpu: use TSG recover API
Deepak Nibade [Wed, 10 Sep 2014 11:04:32 +0000]
gpu: nvgpu: use TSG recover API

Use TSG specific API gk20a_fifo_recover_tsg() in following cases :
- IOCTL_CHANNEL_FORCE_RESET
  to force reset a channel in TSG, reset all the channels
- handle pbdma intr
  while resetting in case of pbdma intr, if channel is part of
  TSG, recover entire TSG
- TSG preempt failure
  when TSG preempt times out, use TSG recover API

Use preempt_tsg() API to preempt if channel is part of TSG

Add below two generic APIs which will take care of preempting/
recovering either of channel or TSG as required
gk20a_fifo_preempt()
gk20a_fifo_force_reset_ch()

Bug 1470692

Change-Id: I8d46e252af79136be85a9a2accf8b51bd924ca8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497875
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: handle MMU fault for TSG
Deepak Nibade [Wed, 17 Sep 2014 07:08:34 +0000]
gpu: nvgpu: handle MMU fault for TSG

- add support to handle MMU faults on a channel in TSG
- first get the ID and type of channel that engine is running
- if TSG, abort each channel in it
- if regular channel, abort that channel

- also, add two versions of API set_ctx_mmu_error(), one for
  regular channel and another for TSG

Bug 1470692

Change-Id: Ia7b01b81739598459702ed172180adb00e345eba
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497874
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: add API to recover TSG
Deepak Nibade [Wed, 17 Sep 2014 07:07:52 +0000]
gpu: nvgpu: add API to recover TSG

- add and export API "gk20a_fifo_recover_tsg()" to
  recover a TSG
- if TSG is running on any engine, then trigger MMU fault
  on those engines
- otherwise, abort each channel in TSG

- modify channel specific API engines_on_ch() to generic
  engines_on_id() which will take an ID and a flag to specify
  whether ID is for channel or TSG and return engines running
  on that ID

- modify channel specific API get_faulty_channel() to generic
  get_faulty_id_type() which will take pointers to ID and type
  of ID (either a regular channel or TSG)

- remove runlist update from recover_ch() since
  no need to touch runlist during recovery

- set error notifier first and then only abort the channels
  for TSG recovery path

- also, add necessary accessors to get engine
  status type as TSG

Bug 1470692

Change-Id: I7137f611f80916b3d256d4b0dc6e5cf1e93eef6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/497873
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agousb: gadget: tegra: Increase NV-Y cable charging current
Rakesh Babu Bodla [Tue, 16 Sep 2014 07:51:16 +0000]
usb: gadget: tegra: Increase NV-Y cable charging current

Increase the NV-Y cable charging current to 3A so
that it charges at 2.1A at h/w level.

Bug 200038358

Change-Id: Ib6fcc0089bd4810fb547b85d0eb5eb46506ad6ad
Signed-off-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/499219
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm64: dts: t210-ers: Enable sharp 25x16 panel
Vineel Kumar Reddy Kovvuri [Mon, 1 Sep 2014 05:03:30 +0000]
arm64: dts: t210-ers: Enable sharp 25x16 panel

Enables support for sharp 25x16 panel

Change-Id: I00cc1eab19a5ac0ed8cc7c52ae0a9983fb0099e2
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/499276
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: vcm30t124: vm2: DVFS disable
sreenivasulu velpula [Mon, 15 Sep 2014 05:01:12 +0000]
arm: tegra: vcm30t124: vm2: DVFS disable

Add CPU/GPU DVFS defconfigs in vm2
Disable CPU/GPU DVFS thorugh DT.

Bug 200032624

Change-Id: I0db42a4e3ac13102bb88f5cfd3c388c46e838e0d
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/496462
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: tegra12: dvfs: Read DT nodes for dvfs disable
sreenivasulu velpula [Mon, 8 Sep 2014 06:32:24 +0000]
arm: tegra12: dvfs: Read DT nodes for dvfs disable

For CPU and GPU DVFS
if DVFS_DEFCONFIG enabled
if ( DVFS DT node does exist <AND> DT node enable is flase)
then disable dvfs
else
disable dvfs

Bug 200032624

Change-Id: Ib3ec8755b09336da6cd091a60d16f93bbb393c93
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/496463
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm64: dts: Expand number of translation registers
Terje Bergstrom [Sun, 14 Sep 2014 16:24:38 +0000]
arm64: dts: Expand number of translation registers

T210 has five translation enable registers.

Bug 1551221

Change-Id: I5b569dc9df7fff6a22dbce3ff0a1a6726b539b9a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/498664

5 years agoiommu/tegra: Expand num_translations to 5 slots
Terje Bergstrom [Sun, 14 Sep 2014 16:22:52 +0000]
iommu/tegra: Expand num_translations to 5 slots

T210 has five translation enable registers. Add the fifth register.
As the fifth register is not consequtive, add function for
calculating the correct register offset.

Bug 1551221

Change-Id: I2ea99c50413be05fb51b4e033d678735b7360f57
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/498663

5 years agoplatform: tegra: fix switch_cluster during suspend
Allen Yu [Tue, 16 Sep 2014 18:43:51 +0000]
platform: tegra: fix switch_cluster during suspend

Interrupts were disabled while switching to slow cluster before entering LP0.
Re-enabling irq in syscore_suspend() is not allowed and will lead to a BUG_ON
in suspend_enter(). This patch avoids enabling irq in switch_cluster() if it's
called with irq disabled.

Bug 200033800

Change-Id: I535a101e1e9e5fa6049aaee8b5cab0386c9ffbcb
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/499425
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agowatchdog: max77620: add shutdown callback
Allen Yu [Mon, 15 Sep 2014 11:27:27 +0000]
watchdog: max77620: add shutdown callback

This patch adds shutdown callback to stop wdt and cancel restart work,
so as to avoid i2c failure in case max77620_wdt_restart_wq() is executed
after i2c bus was shut down.

Bug 1553898

Change-Id: I1447e5ad93e2acf74210f2039366fc63d3e7c628
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/498839
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomisc: Change info print as debug message
Pankaj Dabade [Mon, 7 Jul 2014 05:52:43 +0000]
misc: Change info print as debug message

Updating the message severity to debug.

Bug 200007132
Bug 1283757

Change-Id: Ide4a7cc5b205939e561f96e9e6205e082440e515
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/435015
(cherry picked from commit 94e6176605001ee0e4fd1444dfeb8e006d1289d8)
Reviewed-on: http://git-master/r/439844
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adam Cheney <acheney@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: support of vi-i2c
Charlie Huang [Tue, 16 Sep 2014 20:50:23 +0000]
video: tegra: host: support of vi-i2c

add support of vi-i2c which interfaced with nvhost

bug 1506409
bug 200036553

Change-Id: Iac79149401c3a8221b292cc4f2a26469efc3df93
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/499461
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agodrivers: i2c: bus: support vi i2c engine
Charlie Huang [Tue, 16 Sep 2014 20:57:58 +0000]
drivers: i2c: bus: support vi i2c engine

i2c bus support through vi-i2c.

bug 200036553
bug 1506409

Change-Id: If836e8649169a562a323549b22301004d298a1da
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/499462
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agospi: tegra: use proper of_read function to get boolean property
Laxman Dewangan [Tue, 16 Sep 2014 17:34:55 +0000]
spi: tegra: use proper of_read function to get boolean property

Instead of using of_find_property() for boolean property, use
of_property_read_bool().

Change-Id: If5f7d0385b151cbff43670f26bcd1e7f06197ce1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/499392

5 years agoarch: arm: config: Add CONFIG_SCSI to tegra12_defconfig
Amit Sharma [Tue, 16 Sep 2014 14:09:51 +0000]
arch: arm: config: Add CONFIG_SCSI to tegra12_defconfig

Bug 1349702

Change-Id: I0da751207635cf36f353b37cd39971b069851671
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/498905
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agovideo: tegra: host: common flcn driver for nvjpg
Shridhar Rasal [Fri, 12 Sep 2014 10:31:40 +0000]
video: tegra: host: common flcn driver for nvjpg

Use common falcon driver for nvjpg.

Bug 200006528

Change-Id: Ib3231eaa674cca40693f87e19fd9d1086f9cc821
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/498315
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Senthilkumar Loganath <sloganath@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agopower: bq2419x:disable vbus suppy while shutdown
Venkat Reddy Talla [Tue, 16 Sep 2014 11:54:59 +0000]
power: bq2419x:disable vbus suppy while shutdown

disable vbus supply when otg cable connected
and device powered off.

Bug 200038401

Change-Id: I0fac793b99486898c1d09bf8548f786711a24f6e
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/499291
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agothermal: of: Fix adding a sensor to a zone with polling delay.
Hyungwoo Yang [Mon, 15 Sep 2014 22:02:26 +0000]
thermal: of: Fix adding a sensor to a zone with polling delay.

during a zone creation by DT, since there's no sensor connected to the zone yet,
polling cannot be triggered. The polling should be re-triggered when the sensor
is conntected to the zone.

Bug 1554411

Change-Id: I8877f1afa1eb5cb5861c93777ffdfa8d0dedd316
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/499012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: Fix polling delay of Tboard zone
Hyungwoo Yang [Mon, 15 Sep 2014 21:45:55 +0000]
ARM: tegra: Fix polling delay of Tboard zone

The polling delay of Tboard zone should be 15 seconds

Bug 1554393

Change-Id: I8a5885f370f83f280e35044f092b65760a685aad
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/499003
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agotegra: therm-est: Returns 25C when estimator is not actiaved
Hyungwoo Yang [Mon, 15 Sep 2014 22:24:55 +0000]
tegra: therm-est: Returns 25C when estimator is not actiaved

The device with Tskin Activator should show 25C as its default value
when the estimator is not activated.

Bug 1554425

Change-Id: Iac03cf8d27a3aa7dc912d5748dcdb6ded2cb9dfa
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/499016
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoMerge "Merge remote-tracking branch 'android/android-3.10' into dev-kernel-3.10"...
Bharat Nihalani [Wed, 17 Sep 2014 04:41:21 +0000]
Merge "Merge remote-tracking branch 'android/android-3.10' into dev-kernel-3.10" into dev-kernel-3.10

5 years agoASoC: Tegra: Fix double regulator disable
Shreshtha SAHU [Mon, 15 Sep 2014 11:32:35 +0000]
ASoC: Tegra: Fix double regulator disable

digital_reg was disabled second time instead of codec_reg

Bug 200036995

Change-Id: I8e9b3aeafa613a5a58063b88ee81bf3d0aaf4e43
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/498855
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: change minimum CPU clock rate
sreenivasulu velpula [Tue, 16 Sep 2014 04:32:18 +0000]
arm: tegra: change minimum CPU clock rate

if default clock min rate  is < dvfs lowest frequency
 then change clock min rate to clock min rate

Bug 200033929

Change-Id: I2ee55a0e3acfab7b141def280430aede52327be9
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/499129
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agotegra: thermal: remove untested thermal actions
Diwakar Tundlam [Tue, 26 Aug 2014 21:45:57 +0000]
tegra: thermal: remove untested thermal actions

Remove all soctherm related thermal actions (trip points, throttle
settings, etc.) in preparation for soctherm enablement.

Each soctherm thermal feature will be enabled after sufficient testing and
thermal characterization.

Change-Id: I2508f3c2595937b41938a5b61173f8115e9e750b
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/497641
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agotegra: thermal: remove T11x and T14x support
Diwakar Tundlam [Wed, 10 Sep 2014 01:15:41 +0000]
tegra: thermal: remove T11x and T14x support

Also removed low-precision support which was only used for T11x.

Change-Id: I432978b91674075492b69933700ff9c283b6143e
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/497640
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dc: dump missing nvdc mode info
Sungwook Kim [Fri, 22 Aug 2014 23:44:10 +0000]
video: tegra: dc: dump missing nvdc mode info

NVDC mode dump by reading /sys/kernel/debug/tegradc.X/mode file missed
fields dc->mode.flags and avi_m.
This fix will add them to the dump.

bug 1546992
bug 1532971

Change-Id: I68ba279ff54fe5a3a1877d5bfa37c7dcb7b8eda9
Signed-off-by: Sungwook Kim <sungwookk@nvidia.com>
Reviewed-on: http://git-master/r/487208
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agothermal: pwm_fan: fix bug in fan state setting
Shaoming Feng [Tue, 6 May 2014 22:56:48 +0000]
thermal: pwm_fan: fix bug in fan state setting

Fan temp_control flag was not checked in state setting, so
thermal control is always on. This change fixed this issue.

Bug 1397929

Change-Id: I4be53634d838282baab7b154e15976a31f70e8aa
Signed-off-by: Shaoming Feng <shaomingf@nvidia.com>
Reviewed-on: http://git-master/r/406092
(cherry picked from commit 75bbad8890565cac6762de4760d2f1c6330c4998)
Reviewed-on: http://git-master/r/432878
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>

5 years agotegra: fuse: consolidate all tsosc fuse APIs
Diwakar Tundlam [Thu, 4 Sep 2014 00:07:31 +0000]
tegra: fuse: consolidate all tsosc fuse APIs

Removed tsosc fuse definitions and APIs from chip specific
header files and collected them in one source file.
This is now independent of soctherm.

The list of supported chips is: T12x, T13x, T210.

Change-Id: Ia5474b82efb43ff075c05caf6405bebf477fe9e0
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/497639
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: Ensure clk rate before cluster switch
Sai Gurrappadi [Tue, 16 Sep 2014 00:21:01 +0000]
ARM: tegra: Ensure clk rate before cluster switch

In order to guarantee that a manual cluster switch always succeeds,
ensure that the clock rate is in the permissible range for the new
cluster before the clusterswitch operation starts.

Change-Id: I1be076e33ef10bba5c024bd5d7e71bee416d8b45
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/499064
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agodrivers: edp: restore an erroneously dropped "inline"
Matt Longnecker [Tue, 16 Sep 2014 19:24:38 +0000]
drivers: edp: restore an erroneously dropped "inline"

Change-Id: I7e4add8d0cae04ae382ef7ca7d4d16769405e227
Signed-off-by: Matt Longnecker <mlongnecker@nvidia.com>
Reviewed-on: http://git-master/r/499428
Tested-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agogpu: nvgpu: Change GM20B post-divider in flight
Alex Frid [Sat, 6 Sep 2014 01:29:47 +0000]
gpu: nvgpu: Change GM20B post-divider in flight

Restored changing GM20B GPCPLL post-divider in flight with the
following limitation: post divider transition is glitch-less only if
there is common "1" in binary representation of old and new settings.

Transitions that may create glitch are implemented in glitch-less steps
with minimum possible interim divider value (for example, 1 <=> 2
transition has interim value 3: 1 <=> 3 <=> 2).

Steps allowed for glitch-less transitions may not always have frequency
jump at/below VCO min/2 (in the example above 1st step jumps 2/3 of
VCOmin). Enabled external linear divider at 1:2 during such steps.

Used extra write of the same data when changing GM20b linear divider.

Bug 1552225

Change-Id: Ie8fba2fbe44afd34ca68f5f355bd302b7426a632
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/496319
(cherry picked from commit bdd21e0003032fe664bd20f163dbab9942fd1d1d)
Reviewed-on: http://git-master/r/499193
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agogpu: nvgpu: Update GM20B GPCPLL bypass operations
Alex Frid [Thu, 4 Sep 2014 04:01:10 +0000]
gpu: nvgpu: Update GM20B GPCPLL bypass operations

- Skipped PLL re-locking if only post-divider is changing under bypass
- Added 1us delay after switch to bypass clock source
- Changed wait for lock under bypass resolution from 2us to 1us

Change-Id: I259581c00c417752263ef3b2ea057200bb78ecbf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/495473
(cherry picked from commit d90a19b8bf59c608a2a3a891b34ca714dfe990e9)
Reviewed-on: http://git-master/r/499192
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: vcm30t124: vm1: enable missing configs
Nitin Sehgal [Tue, 19 Aug 2014 16:34:22 +0000]
arm: tegra: vcm30t124: vm1:  enable missing configs

- Enable all the config options enabled in native defconfig

bug 200027162

Change-Id: I1d88c1150957928d42ee620b05f37ba8427bdfee
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/482128
Reviewed-by: Bhavesh Parekh <bparekh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-on: http://git-master/r/498877
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: tegra: vcm30t124: fix vm_2 config
Nitin Sehgal [Wed, 20 Aug 2014 09:45:27 +0000]
arm: tegra: vcm30t124: fix vm_2 config

- Add config options for drivers controlled via device tree

Bug 200022367

Change-Id: I3409e5eaf1ff2ba903f034164a46ed94e0d4fbf5
Signed-off-by: Nitin Sehgal <nsehgal@nvidia.com>
Reviewed-on: http://git-master/r/482508
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Tested-by: Vladislav Buzov <vbuzov@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-on: http://git-master/r/498875
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agovideo: tegra: dc: Correcting SOR enable sequence
Ravi Chandra SV [Wed, 27 Aug 2014 10:20:36 +0000]
video: tegra: dc: Correcting SOR enable sequence

enabling safe clk was not happening in disable
due to which system hangs on accessing SOR register.
clk_type to changed to TEGRA_SOR_MACRO_CLK during enable
sequence.

bug 1536393

Change-Id: I26a2944ef0a63308251d6d81bd964994ce153be4
Signed-off-by: Ravi Chandra SV <ravichandrav@nvidia.com>
Reviewed-on: http://git-master/r/489181
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: Fix DT support for LVDS
Ravi Chandra SV [Mon, 18 Aug 2014 10:51:42 +0000]
video: tegra: dc: Fix DT support for LVDS

bug 1536393

Change-Id: Id59397cb4625fefe79c22579db885a3f88c49929
Signed-off-by: Ravi Chandra SV <ravichandrav@nvidia.com>
Reviewed-on: http://git-master/r/486528
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: dt: p2360: DT change for lvds support
Ravi Chandra SV [Tue, 19 Aug 2014 07:14:23 +0000]
arm: dt: p2360: DT change for lvds support

bug 1536393

Change-Id: I6920a1838232b6c6dab9e1ec3425889a785cc289
Signed-off-by: Ravi Chandra SV <ravichandrav@nvidia.com>
Reviewed-on: http://git-master/r/486527
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra: p2360: lvds bringup
Ravi Chandra SV [Tue, 19 Aug 2014 07:13:31 +0000]
arm: tegra: p2360: lvds bringup

register lvds panel as primary display and hdmi as
secondary display.

bug 1536393

Change-Id: Id423379d3bcfce589a0b2463875fb79c9961acfe
Signed-off-by: Ravi Chandra SV <ravichandrav@nvidia.com>
Reviewed-on: http://git-master/r/486526
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: config: p2360: lvds driver enabled
Ravi Chandra SV [Tue, 19 Aug 2014 07:12:11 +0000]
arm: config: p2360: lvds driver enabled

bug 1536393

Change-Id: Id28ab29368cc04e872cd0f901000a93a971f0f90
Signed-off-by: Ravi Chandra SV <ravichandrav@nvidia.com>
Reviewed-on: http://git-master/r/486525
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM64: dts: tegra:add powermon device dt node for Foster
Venkat Reddy Talla [Wed, 3 Sep 2014 13:02:24 +0000]
ARM64: dts: tegra:add powermon device dt node for Foster

add device tree node for power monitor devices and extcon-otg
for foster patform to enable vbus detection through INA interface.

Bug 1547891

Change-Id: I66481e1182e28b60a19e49dfb0705f34a945a515
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/499300
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoedp: add DT support for sysedp_reactive_capping
Steve Rogers [Mon, 9 Jun 2014 19:57:51 +0000]
edp: add DT support for sysedp_reactive_capping

Bug 1391872

Change-Id: I7f920a2aca96ea79799459ea98564c772cdfed78
Signed-off-by: Steve Rogers <srogers@nvidia.com>
Reviewed-on: http://git-master/r/420755
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>

5 years agoedp: sysedp : CPU/GPU priority depends on fGPU
Matt Longnecker [Tue, 19 Aug 2014 00:00:01 +0000]
edp: sysedp : CPU/GPU priority depends on fGPU

Provide sysedp_dynamic_capping with the instantaneous GPU frequency
when notifying it of the GPU load. Modify the gpu/cpu priority
decision logic to choose CPU priority until GPU frequency gets "near"
the CPU-priority-limited-GPU-fmax. Introduce the priority_bias debugfs
parameter to facilitate tuning of "near". priority_bias takes a value
from 0 to 100.

Change-Id: Ia2cba36b8ea024fb8b01b5ba195dcf6550e38121
Signed-off-by: Matt Longnecker <mlongnecker@nvidia.com>
Reviewed-on: http://git-master/r/481720
GVS: Gerrit_Virtual_Submit
Reviewed-on: http://git-master/r/498912
Reviewed-by: Timo Alho <talho@nvidia.com>

5 years agoMerge remote-tracking branch 'android/android-3.10' into dev-kernel-3.10
Sumit Singh [Tue, 16 Sep 2014 13:48:43 +0000]
Merge remote-tracking branch 'android/android-3.10' into dev-kernel-3.10

Bug 200036626

Change-Id: I4da76bd0eca82e5a1a3a10b98e60fbdfeea38d64
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>

5 years agonet: wireless: bcmdhd: update bcmdhd Kconfig
Manikanta [Mon, 8 Sep 2014 14:28:23 +0000]
net: wireless: bcmdhd: update bcmdhd Kconfig

- Remove default option y from Kconfig
- Remove duplicate code in Makefile

bug 200036211

Change-Id: I4564d68d8976db245a6c527655c6172a45768b78
Signed-off-by: Manikanta <mmaddireddy@nvidia.com>
Reviewed-on: http://git-master/r/496527
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: configs: update bcmdhd config options
Manikanta [Mon, 8 Sep 2014 14:27:37 +0000]
arm: configs: update bcmdhd config options

sync bcmdhd config options as per the changes in Kconfig

bug 200036211

Change-Id: I2458546d854a9175b00fd39ca0003e5bd9f48013
Signed-off-by: Manikanta <mmaddireddy@nvidia.com>
Reviewed-on: http://git-master/r/496526
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: Correct ISPB clock init
Shridhar Rasal [Wed, 20 Aug 2014 06:51:15 +0000]
video: tegra: host: Correct ISPB clock init

Change-Id: Ib866ad93fff323185707809e47269e11475e0ac4
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/498211
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agospi: tegra: set default chip select
Krishna Yarlagadda [Mon, 15 Sep 2014 10:42:58 +0000]
spi: tegra: set default chip select

Set default chip select to single slave connected or
to slave which has default-cs in its dt entry

Bug 1540684

Change-Id: I33850ac21fd641a5950c4ab280b4e93450cf01da
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/498815
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>