5 years agoarm: tegra: vcm3.0: t124: Add panel file
Raghavendra VK [Thu, 3 Oct 2013 06:24:26 +0000]
arm: tegra: vcm3.0: t124: Add panel file

- Register host, nvmap and AVP devices.
- Register eDP, HDMI displays. eDP is not functionally tested. Only HDMI
  is intended to be used.
- Power on GK20A (VDD_GPU)

bug 1373849

Change-Id: I979b6fdbbfbcf474b7644533d531c90759a0cd2b
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/289691
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: vcm30_t124: Disable DP
Raghavendra VK [Thu, 10 Oct 2013 08:47:02 +0000]
ARM: tegra: vcm30_t124: Disable DP

bug 1373849

Change-Id: Id9a898d1a0aad8de8bc61383c9d5a0dba444f091
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/289692
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agomedia: soc_camera_platform: add dev_priv field
Bryan Wu [Tue, 8 Oct 2013 22:36:33 +0000]
media: soc_camera_platform: add dev_priv field

.priv field is used by Tegra V4L2 SoC camera driver, so introduce
a new field named .dev_priv.

Bug 1377330

Change-Id: Id714dca05d7640175b3dc25f7ce582d76abbcaf4
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/289328
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agovideo: tegra: dp: Update DP MSA on modeset
Daniel Solomon [Tue, 15 Oct 2013 20:30:16 +0000]
video: tegra: dp: Update DP MSA on modeset

Update SOR registers from which DP main stream
attribute data is derived when a DC modeset
has occurred.

Change-Id: Ica53d4908eb56cbbce964342986164fc9b8d9543
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/300069
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: add modeset notifier
Daniel Solomon [Thu, 17 Oct 2013 00:24:46 +0000]
video: tegra: dc: add modeset notifier

Add out_ops operation to notify the interface layer
of when a modeset has occurred.

Change-Id: Id39b6a1e80a8bd6fbce09b159213423c9a864038
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/300068
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra: soctherm: keep soc therm clk always on
Seema Khowala [Thu, 17 Oct 2013 00:21:10 +0000]
arm: tegra: soctherm: keep soc therm clk always on

Bug 1367985

Change-Id: I845ea2645d6aefc13717edec43472f34e39140b5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/300241
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoRevert "input: sensor: compass: Add sec-salve-id for compass"
Sridhar Lavu [Thu, 17 Oct 2013 18:17:27 +0000]
Revert "input: sensor: compass: Add sec-salve-id for compass"

This reverts commit a5d457ed40342736b059ab66e68839d9b901df6c
since this may be causing sanity regressions.

Bug 1356943 - original change
Bug 1390642 - sanity regression

Change-Id: I40a9ff951ebb81df6f3e44603e2f34097fa653d0
Signed-off-by: Sridhar Lavu <slavu@nvidia.com>
Reverts-what-was-Reviewed-on: http://git-master/r/290021
Reviewed-on: http://git-master/r/300656
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agotegra: dc: providing default lcd rotation
Vladislav Sahnovich [Tue, 24 Sep 2013 01:36:07 +0000]
tegra: dc: providing default lcd rotation

Allow support for default panel rotation.

Bug 1323602.

Change-Id: I55169442afe89331bc61a18c995aa567ca90ff2e
Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com>
Reviewed-on: http://git-master/r/300690
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: TN8: Add mt9m114 sensor support
David Wang [Tue, 1 Oct 2013 19:29:51 +0000]
ARM: tegra: TN8: Add mt9m114 sensor support

Add SOC1040 (mt9m114) YUV sensor board file
support.

bug 1364405

Change-Id: Ib778467f96fa77f376cad2c127cd9e9763955e3f
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/282824
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add gbus edp capping clock
Alex Frid [Wed, 16 Oct 2013 05:58:47 +0000]
ARM: tegra12: clock: Add gbus edp capping clock

Bug 1307919

Change-Id: I4e237e1ac70c434ac8041fdc9ef3c559317fe61f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299792
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: ardbeg: Support E1767 PMIC module prototype
Alex Frid [Tue, 15 Oct 2013 07:21:32 +0000]
ARM: tegra12: ardbeg: Support E1767 PMIC module prototype

Added support for E1767 PMIC module prototype based on E1735 module
with sku 1001 (E1735 module itself has sku 1000). Major difference:
PWM 1-wire regulator with external buffer is replaced with directly
connected regulator.

Bug 1349163

Change-Id: If5a00a65dea12f9a84f8f7659ac065d44b4afd63
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299684
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Don't change mode of uninitialized DFLL
Alex Frid [Tue, 15 Oct 2013 01:37:13 +0000]
ARM: tegra: power: Don't change mode of uninitialized DFLL

If DFLL has not initialized, yet, or initialization failed:
- do not change DFLL mode from sysfs callback
- do not resume DFLL bypass mode after CPU rail gating/cluster switch

Change-Id: Ife68679b942e9af30cdc7dddbec1abf15f42dd66
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299264
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: nvmap: don't get handle that has ref count as zero
Krishna Reddy [Wed, 16 Oct 2013 20:51:01 +0000]
video: tegra: nvmap: don't get handle that has ref count as zero

Don't get handle that has ref count as zero. This is necessary to
avoid dmabuf NULL issue during nvmap_duplicate_handle_id based on id.
Bug 1389719

Change-Id: I46ad6282bccc3a7445c6ddfb8e76438cb23eb931
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/300146
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agoarm: tegra: build only one tegra*_la.c file
Matt Craighead [Mon, 14 Oct 2013 20:24:54 +0000]
arm: tegra: build only one tegra*_la.c file

This slightly reduces the kernel's size and build time and is
more consistent with how other files are handled in the makefile.

Bug 1351594

Change-Id: I087263f0e1d9afa1fa844a337b1823ddc8cbfa80
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/299058
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agoarm: tegra: T124 DIS and VE powergate dependency
Pablo Ceballos [Wed, 9 Oct 2013 21:01:48 +0000]
arm: tegra: T124 DIS and VE powergate dependency

The DIS partition cannot be powergated without the VE partition first
being powergated. Implement this dependency using the ref-counts.

Bug 1310335
Bug 1350333

Change-Id: I4686816260e7e966635dc4786d07d7d390254c59
Signed-off-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-on: http://git-master/r/288574
Reviewed-on: http://git-master/r/298773
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: host: ELPG off on gr isr and ctx init
Terje Bergstrom [Mon, 14 Oct 2013 12:51:01 +0000]
video: tegra: host: ELPG off on gr isr and ctx init

Turn ELPG off when processing a gr interrupt, and when initializing
a new GR context.

Change-Id: I9f081049995cc8f137324bf13d72a7415d2f2e69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/298969
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: gk20a GPC/TPC/SM exception handling, event notifications
Ken Adams [Wed, 9 Oct 2013 16:10:11 +0000]
video: tegra: gk20a GPC/TPC/SM exception handling, event notifications

- Enabling GPC/TPC/SM exceptions
- Handling above exceptions and notifying debug clients
- Multiple debug interfaces per channel
- Sticky and queued debug events
- Ioctl interface for enabling/disabling/clearing events

Change-Id: If760e72ea4390591a2397b2c2306327f34ccdd30
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/284225
GVS: Gerrit_Virtual_Submit
Tested-by: Ryan Wong <ryanw@nvidia.com>
Reviewed-on: http://git-master/r/299123

5 years agovideo: tegra: gk20a regops whitelisting
Ken Adams [Wed, 9 Oct 2013 16:03:08 +0000]
video: tegra: gk20a regops whitelisting

All regops (debugger/profiler) must now pass a whitelist
check.

Removes superfluous is_quad and pad fields from the ioctl interface.
Re-orders regop elements to be 64b friendly.

Bug 1228597

Change-Id: I84b374a1462e6ec722ed50212a97d32c25a73bb5
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/284223
Reviewed-by: Mayank Kaushik <mkaushik@nvidia.com>
Tested-by: Mayank Kaushik <mkaushik@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-on: http://git-master/r/299122
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Geoffrey Gerfin <ggerfin@nvidia.com>

5 years agoinput: sensor: compass: Add sec-salve-id for compass
Xiaohui Tao [Tue, 17 Sep 2013 17:53:00 +0000]
input: sensor: compass: Add sec-salve-id for compass

Bug 1356943

Change-Id: If34b39b849e350fd9312b9a73130db13c3571b4c
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/272840
Reviewed-on: http://git-master/r/273830
Reviewed-on: http://git-master/r/275874
(cherry picked from commit 9f42dfc3cda19db08aec5a01ed124789240c4970)
Reviewed-on: http://git-master/r/290021
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Loki: Auto detect touch panel
Xiaohui Tao [Tue, 24 Sep 2013 17:26:32 +0000]
ARM: tegra: Loki: Auto detect touch panel

Change-Id: I8cbd73ab4b14ee685f3ca89964f9adc160a7e11b
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/290020
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoapbdma: tegra: save and restore apbdma context
Prashant Gaikwad [Tue, 15 Oct 2013 12:08:36 +0000]
apbdma: tegra: save and restore apbdma context

Save apbdma context before entering LP0 from cpuidle
and restore on exit.

Bug 1254633

Change-Id: Idb21d6b8807064ea9b522f4ca99031b9c18e9f5e
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299482
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoinput: misc: Add support for MPU6515
Erik Lilliebjerg [Mon, 14 Oct 2013 14:32:27 +0000]
input: misc: Add support for MPU6515

- Add support for MPU6515
- Add SW global reset to fix intermittent IRQ storm.
- Add regulator callback to improve POR time.

Bug 1364407
Bug 1387432
Bug 1379869

Change-Id: Ied280b343c7dfd9ff2e0448640d7cb6450e69fdd
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/299491
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoinput: misc: Fix self-test
Erik Lilliebjerg [Mon, 29 Jul 2013 18:42:18 +0000]
input: misc: Fix self-test

- Fix self-test HW restore after test.
- Fix register write failures due to PM cycle mode.

Bug 1327608
Bug 1313284
Bug 1311053
Bug 1315609
Bug 1364407

Change-Id: I9b9fb1afc8b9a10309e0224e56813bc9e400598c
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/255171
(cherry picked from commit 029e3a6a8053e128c93b6bfc3850b74d5577ca66)
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/299490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agousb: gadget: tegra: Notify if HOST PC is connected
Rohith Seelaboyina [Tue, 15 Oct 2013 09:40:39 +0000]
usb: gadget: tegra: Notify if HOST PC is connected

While going to LP0 with charger/PC connected, otg state
changes from peripheral to suspend. If the previous connect type
is charger then udc driver need not notify otg as this would
acquire a temporary wakelock and abort the suspend.
Notify only when HOST PC is connected.

Bug 1354941

Change-Id: Id90af5c4a224424d06322ccc6b3e8e0e13a084d6
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/299405
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>

5 years agoARM: tegra: vcm30t124: pinmux update
Ashwin Joshi [Thu, 17 Oct 2013 08:28:35 +0000]
ARM: tegra: vcm30t124: pinmux update

Update pinmux sheet for vcm30t124 with the following:

- SDMMC pinmux PULL_UP values set properly for SDIO1, SDIO2 and SDIO3
- Some GPIOs updated
- Updated I2C4 pinmux, set RCV_SEL to NORMAL.

Bug 1319925
Bug 1373849

Change-Id: I998f13dc65e99015ce72bf93e6f66998b50ca0d5
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/300460
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoRevert "Revert "ARM: smp_twd: convert to use CLKSRC_OF init""
Ajay Nandakumar [Tue, 15 Oct 2013 11:25:17 +0000]
Revert "Revert "ARM: smp_twd: convert to use CLKSRC_OF init""

This reverts commit ddb49eadadb47df43a5cec0bc3a39cd5ee718121.

Now that we have OF based init with CLKSRC_OF, convert smp_twd init
function to use it and covert all callers of
twd_local_timer_of_register.

Bug 1379817

Change-Id: Ie0bad574361f805081fc050a91e1e3a60513da2d
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299479
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoRevert "Revert "clocksource: tegra: use the device_node pointer passed to init""
Ajay Nandakumar [Thu, 26 Sep 2013 20:48:19 +0000]
Revert "Revert "clocksource: tegra: use the device_node pointer passed to init""

This reverts commit 0e653907ac1d0be9172419c884b820c11864b567.

We've already matched the node, so use the node pointer passed in.
The rtc init was intermingled with the timer init, so split this out
to a separate init function.

Bug 1379817

Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Change-Id: I239269bacad3c7e7f0c3fdc63e4d018d53b542a4
Reviewed-on: http://git-master/r/299023
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Don't depend on 32-bit ulong
Terje Bergstrom [Sat, 12 Oct 2013 13:44:17 +0000]
video: tegra: host: Don't depend on 32-bit ulong

Avoid BITS_PER_LONG and macros BIT_WORD and BIT_MASK that depend on
it. Also avoid ulong when a 32-bit value is expected.

Bug 1377229

Change-Id: I2b146917bf6aff618c01124d16fbdadd804581a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/298698
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: gk20a: bump gk20a_init prio
Prashant Malani [Thu, 3 Oct 2013 03:16:26 +0000]
video: tegra: host: gk20a: bump gk20a_init prio

Increase the gk20a init task's nice value so that
it is pre-empted less, and therefore completes more
quickly as a result.
Also restore the original nice value just before the
task completes.

Change-Id: Icc15e1699d8bf8c5c3d07c2d6d24ac7144aeb616
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/299257
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: improve reset_priv_ring
Prashant Malani [Thu, 3 Oct 2013 03:11:51 +0000]
video: tegra: host: gk20a: improve reset_priv_ring

The number of register writes to perform priv ring reset
is reduced significantly. We also set gpc2clk bypass
divider value to 1 here itself, so that it speeds up not
just priv ring reset, but also clock init.

Change-Id: I0047ac3ab5c734c13daa27d82ebc82f5c76975c8
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/298486
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoRevert "Revert "clocksource: pass DT node pointer to init functions""
Ajay Nandakumar [Thu, 26 Sep 2013 14:16:54 +0000]
Revert "Revert "clocksource: pass DT node pointer to init functions""

This reverts commit 06139bf5f233c03ce1aad929e0adf75fc5fb5898.

In cases where we have multiple nodes of the same type, we may need
the node pointer to know which node was matched. Passing the node
pointer also keeps the init function from having to match the node
a 2nd time.

Update bcm2835, vt8500, and tegra20 init functions for the new
function prototype. Further tegra20 clean-ups are in follow-up commit.

Bug 1379817

Change-Id: Icb37a7bbe4e8f673ce1bcd4ecc92de52d12195eb
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299022
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: move tsc timers to drivers/clocksource
Ajay Nandakumar [Thu, 26 Sep 2013 13:48:41 +0000]
ARM: tegra: move tsc timers to drivers/clocksource

Moving tegra tsc timer to drivers/clocksource

Bug 1379817

Change-Id: Ifa1b1b1638960c390f3fca4ba2261a5692cc8f61
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299021
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: move nv timers to drivers/clocksource/
Ajay Nandakumar [Mon, 16 Sep 2013 13:28:56 +0000]
ARM: tegra: move nv timers to drivers/clocksource/

Moving nvidia timers to drivers/clocksource/

Bug 1379817

Change-Id: I1412fa18d0fbc7f1106d98934f3faf7975dea7cb
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299020
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}
Ajay Nandakumar [Thu, 26 Sep 2013 07:03:07 +0000]
ARM: tegra: Move mach-tegra/{cpuidle.h,timer.h}

Moving mach-tegra/clock.h and mach-tegra/timer.h to
include/linux/tegra-cpuidle.h and include/linux/tegra-timer.h so that
it helps faclitate the movement of drivers from mach-tegra/ to
drivers/.

Bug 1379817

Change-Id: Ia0a33c3f726d2f672409c270ac8ca1629f05eff8
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299019
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: config: vcm30-t124: Add dummy_regulator for PMU
Bhavesh Parekh [Fri, 11 Oct 2013 13:43:26 +0000]
ARM: config: vcm30-t124: Add dummy_regulator for PMU

Add support for dummy regulator in vcm30-t124 defconfig
Also remove unnecessary regulators from the defconfig

bug 1369885

Change-Id: Ie23201cd35890e0d97bf7b152714f6971d64a8e5
Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-on: http://git-master/r/289876
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashwin Joshi <asjoshi@nvidia.com>

5 years agoARM: vcm30-t124: Power: Remove un-necessary rails
Bhavesh Parekh [Fri, 11 Oct 2013 13:46:38 +0000]
ARM: vcm30-t124: Power: Remove un-necessary rails

For VCM30-t124, currently no support for DVFS is required and POR values
of all rails other than LDO5 are correct.
So use dummy-regulator instead of registering the code based on H/w team
input

bug 1369235

Change-Id: I52eb9fb90fa13c4fd35b570b74de9cebd5fd7788
Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-on: http://git-master/r/289877
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: vcm30-t124: Add suspend support
Bhavesh Parekh [Fri, 11 Oct 2013 13:48:34 +0000]
ARM: vcm30-t124: Add suspend support

Call suspend_init call in the init sequence to enable LP0 support
Configure the USB properties to disable wakeup support from USB

bug 1360277

Change-Id: Ia6ff83fee2cc1fdd6b233a54e04cea00dbc1990d
Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-on: http://git-master/r/289878
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: fix clamp status mask
Prashant Gaikwad [Thu, 17 Oct 2013 04:54:03 +0000]
arm: tegra: fix clamp status mask

PCIE and VDE ids are swapped in REMOVE_CLAMPING_COMMAND
but not in CLAMP_STATUS. This results in timeout for
VDE partition.

Bug 1390084

Change-Id: I5d14688f7140d9fc23bb54798147620f631402d1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/300346
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Remove Tegra2 and 3 support
Terje Bergstrom [Tue, 15 Oct 2013 13:05:25 +0000]
video: tegra: host: Remove Tegra2 and 3 support

Remove support for Tegra2 and Tegra3 and host1x clients that exist
only in them.

Change-Id: I60c9e46368657d681502626e43b1a6483674e9fe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/299845

5 years agoARM: tegra: t124: Set DDR mode's TRIM_VAL to 0
Naveen Kumar Arepalli [Wed, 16 Oct 2013 08:52:15 +0000]
ARM: tegra: t124: Set DDR mode's TRIM_VAL to 0

-For eMMC change DDR mode's TRIM_VAL from 4 to 0
as per char team data.

Bug 1333552

Change-Id: Ia5d877be07de80dcfe55ca8f78528e8a6a6fa12c
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/299864
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agovideo: tegra: host: Enable VIC 2nd lvl cg
Terje Bergstrom [Fri, 11 Oct 2013 12:27:40 +0000]
video: tegra: host: Enable VIC 2nd lvl cg

Bug 1338335

Change-Id: I37706d974392bf9098d7c02f116310b60759ece1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/289796

5 years agovideo: tegra: host: Update VIC clock gating params
Terje Bergstrom [Fri, 11 Oct 2013 12:26:31 +0000]
video: tegra: host: Update VIC clock gating params

Update VIC clock gating parameters.

Bug 1338335

Change-Id: I2287cb1f3e7ef875db890d76ec15cd664572e32f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/289795

5 years agoinclude: linux: nvmap: add cma_dev in nvmap_platform_carveout
Krishna Reddy [Thu, 10 Oct 2013 22:21:55 +0000]
include: linux: nvmap: add cma_dev in nvmap_platform_carveout

prepare nvmap to use CMA allocations.
Bug 1279160

Change-Id: I8e61e359329f92a814dd6f23c777f4913b55830f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289417

5 years agoARM: tegra: t124: add SATA support for Laguna FFD
venkatajagadish [Thu, 22 Aug 2013 07:15:23 +0000]
ARM: tegra: t124: add SATA support for Laguna FFD

Change-Id: Icc8e90d3fbc482723a1df9a2d6cfa6b5abcf0068
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>

Conflicts:
arch/arm/mach-tegra/board-ardbeg.c
Change-Id: Ic685f018d5b1170231d9392d0bfe36979c9ad855
Reviewed-on: http://git-master/r/299902
Tested-by: Venkata Jagadish <vjagadish@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: t12x: add SATA support for Laguna FFD
venkatajagadish [Thu, 22 Aug 2013 07:21:12 +0000]
ARM: tegra: t12x: add SATA support for Laguna FFD

Change-Id: I74f1261117fec4352e25fb1121eebcc948c0273a
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/299812
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agovideo: tegra: host: Fix overflow in EMC calc
Arto Merilainen [Thu, 10 Oct 2013 07:16:36 +0000]
video: tegra: host: Fix overflow in EMC calc

This patch fixes an overflow in EMC calculation. We used to square
the difference between gpu clock minimum and maximum which overflow
always.

Change-Id: I8f3b15aff6769e1386430a9222db2940ecef109d
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/288905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: loki: don't init b00 memory
Ray Poudrier [Thu, 10 Oct 2013 00:07:56 +0000]
ARM: tegra: loki: don't init b00 memory

Initializing the a00 mem table on b00 will hang

Bug 1326949

Change-Id: Iba471bad27a5d00b291d2cda6d70f98a515d198d
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/289258
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Tao Xie <txie@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: t12x: Update drive strengths for I2C
Chaitanya Bandi [Wed, 16 Oct 2013 10:47:11 +0000]
ARM: tegra: t12x: Update drive strengths for I2C

Updated the drive-strengths of I2C pads as per
the new recommended values

Bug 1347466

Change-Id: I1b94f76d101877fa3bf28655f5a9c4edbc1e2893
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/299937
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarch: config: Update ardbeg MODS defconfig
Anand Bhatia [Mon, 14 Oct 2013 19:05:12 +0000]
arch: config: Update ardbeg MODS defconfig

Disable HS200 Mode at boot for EMMC

Change-Id: I155c33eb5273ce1aae1c521d1f034f86f77fc82d
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/299041
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: ardbeg: powermon: set ina230 avg value
Jon McCaffrey [Wed, 25 Sep 2013 19:30:08 +0000]
ARM: tegra: ardbeg: powermon: set ina230 avg value

Sets a value for the avg field of the ina230 config.  This will take 128
samples per-reading.  With the default conversion time of 140us, this
works out to ~18ms per-reading, which is a long time, but works well for
anti-aliasing power measurements for changes in power consumption over
graphics frames (~16ms).

Change-Id: I81f2a40dbae3f70e2fb24538d5a01b5c7c17ac24
Signed-off-by: Jon McCaffrey <jmccaffrey@nvidia.com>
Reviewed-on: http://git-master/r/299577
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agohwmon: ina230: add avg to platform_data
Jon McCaffrey [Wed, 25 Sep 2013 19:27:21 +0000]
hwmon: ina230: add avg to platform_data

Make the avg configurable via platform-data so that it can be adjusted
on a device-specific basis.  The default is no averaging, and this
value is not one-size-fits-all.

Change-Id: I114c3d15ff7679d0a20b5f7d34a02d6ac252d55c
Signed-off-by: Jon McCaffrey <jmccaffrey@nvidia.com>
Reviewed-on: http://git-master/r/299576
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: ardbeg: add PBB4 to VGP4 in pinmux
David Wang [Mon, 30 Sep 2013 17:16:22 +0000]
ARM: tegra: ardbeg: add PBB4 to VGP4 in pinmux

Added the connection from GPIO_PBB4 to VGP4 in the pinmux
board file.

bug 1369360

Change-Id: I6f222bcb0432bb54ba29866e386ec2b3ec7ebd24
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/282815
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: remove 53Hz mode from Sharp 1080p panel
Mitch Luban [Fri, 20 Sep 2013 18:27:04 +0000]
arm: tegra: remove 53Hz mode from Sharp 1080p panel

Reviewed-on: http://git-master/r/277308

Change-Id: Ib3acb9cdaebe6f53ac623ef5daa11b71b2cd0984
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/299593
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: dvfs: Don't enbale DFLL bypass on LP cluster
Alex Frid [Mon, 14 Oct 2013 22:28:13 +0000]
ARM: tegra: dvfs: Don't enbale DFLL bypass on LP cluster

Since Cl-DVFS PWM logic is on G CPU power rail, keep DFLL bypass
output in PWM mode disabled when running on LP CPU cluster.

Change-Id: If2325fb824bc8f812e43e479abf43658d5550b70
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/299263
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Remove obsolete gpu_dvfs debugfs node
Alex Frid [Sat, 12 Oct 2013 04:01:23 +0000]
ARM: tegra: dvfs: Remove obsolete gpu_dvfs debugfs node

Change-Id: Idb9e5b225b2b94232200154e00f5843889516106
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/298529
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>

5 years agomedia: platform: tegra: update ov5693 driver.
Frank Chen [Thu, 3 Oct 2013 02:10:01 +0000]
media: platform: tegra: update ov5693 driver.

Update the ov5693 driver to reflect changes made during
tegranote development on serperate branch.

Fixing the following issues:
- Sluggish preview
- Pink preview in video mode

Bug 1373309
Bug 1367317

Change-Id: Ic0de85a6b783678cebfc328e38cf84c30e6bf316
Signed-off-by: Frank Chen <frankc@nvidia.com>
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/298692
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agomedia: platform: tegra: update ad5823 driver
Frank Chen [Thu, 3 Oct 2013 01:37:38 +0000]
media: platform: tegra: update ad5823 driver

This is to bring the ad5823 focuser driver to
the same state of TegraNote ad5823 driver.

This should solve the focuser timeout issue.

Bug 1371717

Change-Id: I33ea762f489f38e92a024bb3c49596c96a88606b
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/282828
Tested-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agostaging: android: nvmap page pool free memory should be in other_free
Krishna Reddy [Mon, 14 Oct 2013 18:23:19 +0000]
staging: android: nvmap page pool free memory should be in other_free

nvmap page pool free memory should be added to other_free, which is
used to detect low memory conditions.
Bug 1385817
Bug 1387131

Change-Id: I60adf77c004383e43940c3fc586099f4da80a1f5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/299032
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: get dma_buf from fd
Krishna Reddy [Wed, 2 Oct 2013 21:34:14 +0000]
video: tegra: host: get dma_buf from fd

get dma_buf from fd directly when nvmap handles are
represented using fd's.

Change-Id: Iccf1e55e08c42f86e958a4ea6a8d707b44a8628d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294245
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agomedia: platform: tegra: nvavp: get dma_buf from fd
Krishna Reddy [Wed, 2 Oct 2013 21:30:15 +0000]
media: platform: tegra: nvavp: get dma_buf from fd

get dma_buf from fd directly when nvmap handles are
represented using fd's.

Change-Id: I360ff76b713ef076d3bcc03d66d656bf2ccacea5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294243
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Soumenkumar Dey <sdey@nvidia.com>

5 years agoARM: tegra12: update tegra12_defconfig for L4T
Bibek Basu [Tue, 15 Oct 2013 09:51:47 +0000]
ARM: tegra12: update tegra12_defconfig for L4T

Enable FRAMEBUFFER_CONSOLE
Enable LOGO
Disable TEGRA_EHCI_BOOST_CPU_FREQ

Bug 1387426

Change-Id: I669d8bc4f10d80b62efd27b78e179bd5509fe0b1
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/299548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

5 years agoRevert "usb: gadget: tegra: Reduce CPU boost trigger size"
Mitch Luban [Tue, 15 Oct 2013 22:52:42 +0000]
Revert "usb: gadget: tegra: Reduce CPU boost trigger size"

This reverts commit b0be3cdc61bc17398d2363d484366053ea097bcb.

Bug 1383091

Change-Id: I02ad6b260a62648d6cfad2e0ff889a4d6415d16f
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/299666
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>

5 years agoarm: tegra: add tegra12-se to MC clock domain
Prashant Gaikwad [Wed, 16 Oct 2013 09:52:37 +0000]
arm: tegra: add tegra12-se to MC clock domain

Bug 1307958

Change-Id: Ic99ef03be4483d664d118863b6b16f6661526f2b
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299915
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: common: fix unused variable warning
Philip Rakity [Fri, 11 Oct 2013 13:20:44 +0000]
arm: tegra: common: fix unused variable warning

/home/prakity/dev-kernel_linux/kernel/arch/arm/mach-tegra/common.c:
In function 'tegra_reserve':

/home/prakity/dev-kernel_linux/kernel/arch/arm/mach-tegra/common.c:1786:6:
warning: unused variable 'i' [-Wunused-variable

Change-Id: I91416c4720b639e3333adba242466fb022e7fedc
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/289853
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agocpufreq: Interactive: make cpufreq_interactive_tunables global
Ajay Nandakumar [Tue, 15 Oct 2013 20:32:18 +0000]
cpufreq: Interactive: make cpufreq_interactive_tunables global

Making cpufreq_interactive_tunables global so that the tuning knobs
values set from user space presist.

This needs to be re-visited once per-cpu governor is enabled.

Change-Id: I762510c8e588a73a4dfcaac95d2b6008e7fee0f4
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299598
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Enable gk20a on debug spew
Terje Bergstrom [Mon, 14 Oct 2013 08:18:54 +0000]
video: tegra: host: Enable gk20a on debug spew

Change-Id: Ia5efe3c46f46ebe6494f3a023ea3d8783f0739f2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/298881
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: Add mutex for PMU dmem copy
Eric Eells [Wed, 2 Oct 2013 22:25:28 +0000]
video: tegra: host: Add mutex for PMU dmem copy

For copying data between system memory and GK20a
PMU data memory, there are two functions.
pmu_copy_to_dmem and pmu_copy_from_dmem use
registers that must have only one transaction
happening at a given time.  That is, there can be
exactly _one_ read happening or exactly _one_
write happening, but not both.  Using an atomic
integer, we could see that there were multiple
reads and writes happening simultaneously.  This
change prevents this situation by adding a simple
mutex around execution of these functions.

Change-Id: I70bf1f1c0bb4b53adfba231c6f3646d3dac63367
Signed-off-by: Eric Eells <eeells@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/289710

5 years agoarm: tegra: make sure that the PG request is accepted by PMC
Prashant Gaikwad [Tue, 15 Oct 2013 12:19:54 +0000]
arm: tegra: make sure that the PG request is accepted by PMC

The role of START bit has changed, beginning T35. To account
for bug 863229 start bit will now be cleared by HW when PMC
accepts the request to powergate or unpowergate the partition.
So in order to powergate/unpowergate a partition SW needs to
do the following.

1. Check to see if the partition is already in the correct state,
by looking at the PWRGATE_STATUS register. If not then SW reads
the PWRGATE_TOGGLE register to see if START bit is 0. If not poll
till start bit is set to 0.
2. After that program the PWRGATE_TOGGLE register with start bit
set as 1 and choose the required partition to be powrgated.
3. Ideally then SW can poll to check the START bit going back to 0,
to indicate that PMC has accepted the request.
4. Then poll the STATUS register to make sure the required partition
is powergated/unpowergated.

Also, in current implementation SW is polling REMOVE_CLAMPING_CMD to
check the CLAMP remove status. As per the HW guys this register is
write only and does no make sense polling it. Instead use CLAMP_STATUS
for polling.

Bug 1376147

Change-Id: Id34e900dff870d4d22288922ee1d0487ab4911dc
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299801
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: enabled PASR config for T124
Prashant Gaikwad [Tue, 1 Oct 2013 09:11:42 +0000]
arm: tegra: enabled PASR config for T124

Bug 1347784

Change-Id: I14679000206399188e006cfa0fe4fc8fd9c85b92
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299364
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: add PASR support for T124
Prashant Gaikwad [Tue, 15 Oct 2013 07:55:28 +0000]
arm: tegra: add PASR support for T124

This supports only LPDDR2/3 DRAM parts.

Bug 1347784

Change-Id: I5772a552938ac7c3cb20543e2b096587e0531f77
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299363
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoiommu/tegra: smmu: save and restore smmu context
Prashant Gaikwad [Tue, 15 Oct 2013 11:45:07 +0000]
iommu/tegra: smmu: save and restore smmu context

Save SMMU context before entering LP0 from cpuidle
and restore on exit.

Bug 1254633

Change-Id: I9069a9eceae1c4ab89c04d3bc40fe0f97ac5138f
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agovideo: tegra: host: gk20a: don't enable ARCH timer
Edgardo Handal [Tue, 15 Oct 2013 21:37:55 +0000]
video: tegra: host: gk20a: don't enable ARCH timer

Change-Id: I592a0bd0f4276cbab92ccf7aa95ad89c4090038b
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/299618
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: register save and restore ops
Prashant Gaikwad [Fri, 20 Sep 2013 10:17:31 +0000]
arm: tegra: register save and restore ops

Register syscore ops for modules whose context has to
saved/restore during entry/exit to LP0 state from CPU
Idle.

Bug 1254633

Change-Id: Idf4a67535754db3ccc2fc528469fb17ec198cee0
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299447
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoPM / Core: add save and restore syscore ops
Prashant Gaikwad [Fri, 20 Sep 2013 10:09:25 +0000]
PM / Core: add save and restore syscore ops

Add ops to save and restore system context when entering deep
idle state.

Bug 1254633

Change-Id: Iea36ed98544827ce73b50fcb2bf201c233baf2ca
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299446
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agommc: tegra: Set calibration offsets for all modes
Pavan Kunapuli [Tue, 15 Oct 2013 13:52:01 +0000]
mmc: tegra: Set calibration offsets for all modes

Characterization team agreed for two sets of calibration offsets - one
for 3.3V and one for 1.8V. The 1.8V offsets would be applicable for all
UHS modes and HS200 mode as well.

Calibration would be run when voltage is set. There is no requirement to
run calibration after setting UHS mode. Removing the related changes.

Bug 1347531

Change-Id: If74b0722c630a36ad53807ba64d1fffc4904920b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/299521
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: ardbeg/loki: Fix calibration offsets
Pavan Kunapuli [Tue, 15 Oct 2013 13:35:57 +0000]
ARM: tegra: ardbeg/loki: Fix calibration offsets

Based on the latest characterization results, calibration offsets should
be set for all modes. Removing the platform data that would selectively
set calibration offsets for some modes.

Bug 1347531

Change-Id: I40e92c6b2f11a7030e0b0cc6fac03ad12767ada7
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/299520
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: add ops for vdd_core domain
Prashant Gaikwad [Tue, 15 Oct 2013 11:01:49 +0000]
arm: tegra: add ops for vdd_core domain

Before turning off VDD_CORE from CPU Idle it is
required to save context of all modules powered
from VDD_CORE rail. This change add ops to call
suspend function of all device in VDD_CORE domain.

Bug 1254633

Change-Id: I0bcacc5c7049e87f91289ccd9c2d54c9389b8ed1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299443
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: update power state residency
Prashant Gaikwad [Thu, 19 Sep 2013 08:12:05 +0000]
arm: tegra: update power state residency

Update minimum residency expected for different power
states as derived from analysis done in bug 1347388

Bug 1347388

Change-Id: Ifd3d1e68d58a3c0bf5015b33be5ed8c926dd1e91
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299462
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: support for FIQ debugger with secure OS
Varun Wadekar [Fri, 11 Oct 2013 07:13:03 +0000]
arm: tegra: support for FIQ debugger with secure OS

Most of the set up for the debugger is done by the secure
OS, but the kernel setup that needs to be done is done here.

Use the following config options to enable the debugger -

CONFIG_FIQ=y
CONFIG_TEGRA_FIQ_DEBUGGER=y
CONFIG_FIQ_GLUE=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_TEGRA_WATCHDOG=y
CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE=y

Bug 1326082

Original-author: Hyung Taek Ryoo <hryoo@nvidia.com>

Change-Id: If1a5dd4f158530dea6c0455ead74a8eeaa226163
Reviewed-on: http://git-master/r/#/c/261217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/289165

5 years agovideo: tegra: t124: Add emc clocks for VI/ISP
Sudhir Vyas [Tue, 15 Oct 2013 08:51:45 +0000]
video: tegra: t124: Add emc clocks for VI/ISP

Bug 1328905

Change-Id: I473c493301bef53203feea1724d1d94369f8c529
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/299390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: Create VI/ISP emc clocks
Sudhir Vyas [Tue, 15 Oct 2013 08:49:36 +0000]
arm: tegra: Create VI/ISP emc clocks

Bug 1328905

Change-Id: Ide1c6fb232ba818598b2dc130b8c127d5113b190
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/299389
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dsi: Disable TE during OSidle
Animesh Kishore [Tue, 8 Oct 2013 14:30:41 +0000]
video: tegra: dsi: Disable TE during OSidle

Bug 1381539

Change-Id: I4758b12f782dc3c669af3937182f77e8e74c4a6a
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/289990
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: pcie: Enable PLL Power down and WAR
Jay Agarwal [Tue, 15 Oct 2013 09:25:37 +0000]
ARM: tegra: pcie: Enable PLL Power down and WAR

1. Support added for PLL power down.
2. High temp refclk disappear WAR:
CLKREQ PEX pins are used to determine whether to
drive 100MHz refclk, but some platfroms have CLKREQ
floating resulting in disappear of refclk specially
at higher temperatures. This WAR overrides CLKREQ
to always drive REFCLK and revert it later if any
device connected to RP has CLKREQ capability after
applying pullup on CLKREQ# PEX pins.

Bug 1356695
Bug 1330959

Change-Id: I9178cc748fcd28bef728dfad0f023e2ff900cd61
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/299399
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: ardbeg: set LDOUSB to always on
Mallikarjun Kasoju [Tue, 15 Oct 2013 05:06:47 +0000]
ARM: tegra: ardbeg: set LDOUSB to always on

set LDOUSB to always on to get cable state of USB-ID

Bug 1360804

Change-Id: Ie89bc691f60864a1229333ba2ed8eb3339e73417
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/299295
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agonet: wireless: bcmdhd: NULL checks for dhd and wlfc state pointers
Mohan T [Wed, 16 Oct 2013 06:32:31 +0000]
net: wireless: bcmdhd: NULL checks for dhd and wlfc state pointers

On wlan reset state wlfc_state is getting cleared.
If The bw call on this stage are leading to
kernel panic. So do NULL checks for wlfc_state
and dhdp to avoid kernel panic.

Bug 1380656

Change-Id: I71255620f1c751a06ca55f7c9398ab80a4686475
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/289606
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>

5 years agoARM: tegra: pcie: Add WAR for Eye Diagram failure
Jay Agarwal [Tue, 15 Oct 2013 09:11:36 +0000]
ARM: tegra: pcie: Add WAR for Eye Diagram failure

1. Apply WAR for EYE diagram failure
2. USE board ID to distinguish implementation for
   different boards on same chip

Bug 1346141

Change-Id: I8ead24a5e8bcd00608dfa3a6d087353c2a8c22b6
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/299398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agovideo: tegra: gk20a: Fix GPCPLL lock timeout
Kaz Fukuoka [Tue, 1 Oct 2013 22:55:24 +0000]
video: tegra: gk20a: Fix GPCPLL lock timeout

bug 1372372

Change-Id: I548e19a8c611eb7e9bb8029d3a939909945b7005
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/299011
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: nor: Make NOR mapping size configurable
Ashwin Joshi [Fri, 11 Oct 2013 10:15:06 +0000]
drivers: nor: Make NOR mapping size configurable

Keep NOR static mapping size configurable since different boards could
have NOR of different size.

Bug 1373849
Bug 1386803

Change-Id: If009fb09125ff3d6576c2a82ed82a8984bdf11d2
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/289676
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dp: Implement full link training
Animesh Kishore [Wed, 2 Oct 2013 10:31:55 +0000]
video: tegra: dp: Implement full link training

Bug 1368069

Change-Id: Ibb4144a328aa5775cd9d0dbf231fc3402df070ba
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/298720
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agomedia:video:tegra: add HDR for ar0261
Amey Asgaonkar [Thu, 15 Aug 2013 00:32:11 +0000]
media:video:tegra: add HDR for ar0261

adding HDR support code for front camera
sensor ar0261.

Bug 1330898

Change-Id: I455d8d9fc8b529ea0bd35ce4538932fd48b6882a
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-on: http://git-master/r/299108
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoextcon: palmas: don't check line state
Mallikarjun Kasoju [Tue, 15 Oct 2013 05:05:18 +0000]
extcon: palmas: don't check line state

No need to check line state for getting cable state.

Bug 1360804

Change-Id: Id1b591939f5aa931281cbb32336d3234d0b23c4a
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/299294
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: ardbeg: board file change for maxim touch
Xiaohui Tao [Fri, 20 Sep 2013 20:37:30 +0000]
arm: ardbeg: board file change for maxim touch

Bug 1364399

Change-Id: I4c8f854e7d3c08dcf6d91350c41a490ffdeb2f7e
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoxhci: tegra: Fix bias pad power control
joyw [Fri, 13 Sep 2013 09:59:52 +0000]
xhci: tegra: Fix bias pad power control

Per UTMIP software guideline document, if xusb own OTG port0,
use xusb padctl register space to power on/off bias pad.

Bug 1334491

Change-Id: I8037cd2811b6069e7c19957975a7e12b05cd834c
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/289624
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: Redefine SWGROUP ID
Hiroshi Doyu [Fri, 11 Oct 2013 08:19:28 +0000]
ARM: tegra: Redefine SWGROUP ID

Redefine SWGROUP ID for the future chips with more HWAs.

Also modified how to calculate MC_SMMU_<SWGROUP ID>_ASID_0 offset from
ID in SMMU in order not to break git bisctability.

Change-Id: If7239e626fba6e935a48b525897ed7e592882a0a
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/299346
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: la: program bbc ptsa dynamically
Krishna Reddy [Tue, 6 Aug 2013 23:23:07 +0000]
arm: tegra: la: program bbc ptsa dynamically

program bbc ptsa dynamically based on bw requested for BBCR and BBCW
add sysfs nodes to disable display, bbc ptsa's.
Bug 1322650

Change-Id: I8dbb9445c1fa9ca32072c77a9193164925aaa8da
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272179
(cherry picked from commit 0ec1afbc0d38fbbe3a86542169f137d6c4241ae3)
Reviewed-on: http://git-master/r/294241
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: dsi: Fix unbalanced clk API calls
Vineel Kumar Reddy Kovvuri [Mon, 7 Oct 2013 07:53:41 +0000]
video: tegra: dsi: Fix unbalanced clk API calls

Fixes unbalanced clk enable disable calls

Bug 1376053

Change-Id: I9a6933fa21b91989c5f36f110c47690455148909
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/288740
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agousb: xhci: tegra: Fix error in non-SMP build
Edgardo Handal [Mon, 14 Oct 2013 17:22:38 +0000]
usb: xhci: tegra: Fix error in non-SMP build

Bug 1386515

Change-Id: Ic297f5a4fe08888b71062f284ad75b62e7393ee8
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/299015
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: t124: fury: update fury dtb to latest status.
Hayden Du [Tue, 15 Oct 2013 05:25:44 +0000]
arm: t124: fury: update fury dtb to latest status.

Change-Id: Id68caa538b987d18597191aff82f5734dc02979f
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/299303
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoinput: touch: maxim_sti: Update to version 1.4.1, v28
Andy Chiang [Fri, 13 Sep 2013 09:44:16 +0000]
input: touch: maxim_sti: Update to version 1.4.1, v28

Fast-forward code from the first maxim code drop.

Bug 1364399

Change-Id: I01f1078b6c4942cd3e5102c0c33d823b54bb56e8
Signed-off-by: Andy Chiang <achiang@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>

5 years agoarm: ardbeg: defconfig change for adding maxim touch
Xiaohui Tao [Thu, 26 Sep 2013 00:00:30 +0000]
arm: ardbeg: defconfig change for adding maxim touch

Bug 1364399

Change-Id: I0ed38a61aff83c28ddad0aa070f18f1130d13b93
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289388
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>