5 years agoMerge tag 'v3.10.17' into dev-kernel-3.10
Ajay Nandakumar [Thu, 31 Oct 2013 01:42:36 +0000]
Merge tag 'v3.10.17' into dev-kernel-3.10

This is the 3.10.17 stable release

Conflicts:
drivers/usb/host/xhci.c

Change-Id: I6bd3b15ff92a0b94568b9d02e9bb1036becfca20

5 years agoARM: tegra12: clock: Update PLLD 594MHz rate table
Kaz Fukuoka [Thu, 26 Sep 2013 23:56:31 +0000]
ARM: tegra12: clock: Update PLLD 594MHz rate table

Bug 1339555

Change-Id: I23d804fe93f20df4ecd797f288768f2481b6d1e0
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/298511
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: dvfs: Show DFLL thermal profiles in debugfs
Alex Frid [Sun, 27 Oct 2013 05:17:43 +0000]
ARM: tegra: dvfs: Show DFLL thermal profiles in debugfs

Change-Id: Id955390bec1a4edd2f166c29776e964c5e04dcbf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304159
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Combine GPU CVB tables
Alex Frid [Wed, 30 Oct 2013 01:49:07 +0000]
ARM: tegra12: dvfs: Combine GPU CVB tables

Combined GPU CVB frequency scaling tables for different chip skus into
one table, and applied per-sku maximum frequency limits to this table.

Bug 1342499

Change-Id: I58d24f56d43142891cadffc28ccacfae1b382d71
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/309374
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update Tegra12 sku selection
Alex Frid [Tue, 29 Oct 2013 20:11:46 +0000]
ARM: tegra12: dvfs: Update Tegra12 sku selection

- added CPU speedo ids 0x2 (frequency limit 2.1GHz) and 0x3 (frequency
limit 2.5GHz)
- added support for sku 0x83 - mapped to CPU speedo id 0x2, GPU speedo
id 0, core speedo id 0
- updated CPU and GPU speedo thresholds so that there is only one CPU
and GPU process id per sku

Bug 1342499

Change-Id: Iaf10f9939c2cd7a576c22814e67fb67c01901e43
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/305126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra12: soctherm: Check and register cdev
Diwakar Tundlam [Mon, 28 Oct 2013 22:49:32 +0000]
arm: tegra12: soctherm: Check and register cdev

Save previous reigstration of tegra-shutdown cooling device and check
it to avoid duplicates.

Bug 1342361

Change-Id: I01c7e68c6045d27f8bf2c1173d36245f87cd9342
Reviewed-on: http://git-master/r/304542
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: update balanced throttling table
Hyungwoo Yang [Mon, 7 Oct 2013 17:42:53 +0000]
ARM: tegra: update balanced throttling table

Updated balanced throttling table. Support separate GPU throttling table.

Bug 1364149

Change-Id: Ia29361e1851b0e3abbbc1bbd8561f04a4530f531
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/303530
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: laguna: correct avdd_dsi_csi owner
Bryan Wu [Wed, 25 Sep 2013 20:13:02 +0000]
ARM: tegra: laguna: correct avdd_dsi_csi owner

avdd_dsi_csi regulator is owned by vi.0 and vi.1. With the wrong name
of owner like "vi", driver will fail to get this regulator:

"nvhost_vi_init: couldn't get regulator"

Bug 1377330
Bug 1398103

Change-Id: Ibba0e8afc5c353e0a7f41f6996313afc7e0f0f2e
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/289323
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: enable skin estimator based throttling
Hyungwoo Yang [Fri, 25 Oct 2013 22:19:00 +0000]
ARM: tegra: enable skin estimator based throttling

Enable skin estimator based throttling.

Bug 1392971

Change-Id: I684682b62b0d2b54af981946ec3715c97820d4d1
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/304028
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra12: soctherm: support CP1/CP2 fuses
Diwakar Tundlam [Wed, 30 Oct 2013 00:05:09 +0000]
arm: tegra12: soctherm: support CP1/CP2 fuses

Check CP fuse ATE revision and if more recent, use CP1/CP2 fusing
style and use the corresponding new fuse corrections.

Bug 1291108

Change-Id: I911ecc5713233a2304f731e215108b1d72e9852d
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/305119
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agotegra: dc: copied bksv into the packet structure
sharath [Thu, 3 Oct 2013 00:30:52 +0000]
tegra: dc: copied bksv into the packet structure

copied bksv from tegra_nvhdcp structure to tegra_nvhdcp_packet structure.

bug 1354159

Change-Id: I6157428a6044977de5365b048ac20a35ffbc109a
Signed-off-by: sharath <ssarangpur@nvidia.com>
Reviewed-on: http://git-master/r/281198
Reviewed-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Signed-off-by: Sharath Sarangpur <ssarangpur@nvidia.com>
Reviewed-on: http://git-master/r/301485
Reviewed-by: Automatic_Commit_Validation_User

5 years agoinclude: dt-binding: input: create a DT header defining key codes.
Laxman Dewangan [Tue, 6 Aug 2013 14:12:49 +0000]
include: dt-binding: input: create a DT header defining key codes.

Many of Key device tree bindings uses the constant number as key code
which matches with kernel header key code and then comment as follows
for reference/better readability:
linux,code = <102>; /* KEY_HOME */

Create a DT header which defines all the key code so that DT key bindings
can use it as follows:
linux,code = <KEY_HOME>;

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
(cherry picked from commit 8851b9f1625ce0858e9b1bb0ae4a57d4b43178b1)

Change-Id: I44bf6a594d6a678751c8e0e4b3fc0737fd5f2f78
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/309601

5 years agoinput: gpio-keys: report key event if it is casue of wakeup
Laxman Dewangan [Wed, 30 Oct 2013 09:44:57 +0000]
input: gpio-keys: report key event if it is casue of wakeup

Report key press in resume if it is causes for wakeup the system from
suspend.

Change-Id: I5b92d8d31d7d6c7a529139207652d4170004bd9b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/309528

5 years agoARM: tegra: wakeup: add function to get wakeup irq
Laxman Dewangan [Wed, 30 Oct 2013 09:37:02 +0000]
ARM: tegra: wakeup: add function to get wakeup irq

Add API to get irq number of wakeup source which causes
system to wakeup from LP0.

Change-Id: I3a61099bad9880f1a560d7d9477e1ff69044876b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304932
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: move wakeup APIs to common file
Laxman Dewangan [Wed, 30 Oct 2013 07:11:07 +0000]
ARM: tegra: move wakeup APIs to common file

Instead of implementing some common api for every chip on
same way n different files, moving this code to a single file
to avoid code duplication.

Change-Id: I0a7ed15f63d7034533deb07da0bd7e8e650d682a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304931
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: pmc: move exported APIs declaration to public header
Laxman Dewangan [Tue, 29 Oct 2013 12:42:30 +0000]
ARM: tegra: pmc: move exported APIs declaration to public header

Change-Id: If245f123f9903a6fc17c3d9ae7bdb6607d9deb9f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304930

5 years agoRevert "video: tegra: host: add DT support"
Deepak Nibade [Wed, 30 Oct 2013 15:01:02 +0000]
Revert "video: tegra: host: add DT support"

This partial change for DT support breaks boot on T124
This change will be re-pushed along with other changes of
device tree support

This reverts commit d79d84948ff69a382bd04d0087d7a421273ebe62.

Bug 1366383

Change-Id: I70d9b7356c9cf0ff1cfa554436c7f45a64c350ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/309665
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Initialize as only for GPU
Terje Bergstrom [Tue, 29 Oct 2013 07:06:15 +0000]
video: tegra: host: Initialize as only for GPU

Create as devices only for units that support as. At the moment that
is only gk20a.

Bug 1389581

Change-Id: I7e6f9fbdf2ce1fb35cb07cd6c4c46a85247914e8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/304717
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: add DT support
Deepak Nibade [Wed, 30 Oct 2013 06:26:40 +0000]
video: tegra: host: add DT support

make necessary driver changes to enable DT support in nvhost

bug 1366383

Change-Id: I0dd98f598fda09a9a4065b54a3b37870d993fdfa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/299484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: fix VI regulator crash
Deepak Nibade [Wed, 30 Oct 2013 06:27:21 +0000]
video: tegra: host: fix VI regulator crash

assign VI regulator to NULL after regulator_put() call
to avoid race where regulator_disable() is called after
regulator_put() which results into crash

bug 1366383
bug 1398454

Change-Id: Ie13155775f67d842d6fbdd7a5746bb3bb4d1b0d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/309447
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: Tegra: Fix comment about clock switch
Antti P Miettinen [Mon, 28 Oct 2013 11:17:09 +0000]
ARM: Tegra: Fix comment about clock switch

Upon turning off PLLs CPU is switched to CLKM.

Change-Id: I72d3cd6a6a103ef954b03453f5bcc0131a9737f2
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/304351
(cherry picked from commit 5528184cfee750a3e64e62f3d0054537e40fa329)
Reviewed-on: http://git-master/r/309558
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agomedia: nvavp: uninit nvavp in runtime PM
Prashant Gaikwad [Wed, 30 Oct 2013 06:12:45 +0000]
media: nvavp: uninit nvavp in runtime PM

If we enter LP0 from cpuidle all the context of nvavp will
be reset as VDD_CORE is turned off in LP0.

Save and restore the context of nvavp in runtime suspend and
resume. If nvavp is idle for 2s then it will get suspended
and context is saved. If some request or remote weakeup is
received for it then it is restored.

Also, add current task checks to avoid deadlocks in reentrant
calls.

Task1
nvavp_open
  nvavp_init
    pm_runtime_get_sync
      runtime_resume
          nvavp_init (DEADLOCK)

Bug 1254633

Change-Id: I7c3690624c371c2c111ad3d6f4b41b41d5e7aa97
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/304210
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoEDP: tn8: add consumer data for cameras
Timo Alho [Tue, 29 Oct 2013 12:09:36 +0000]
EDP: tn8: add consumer data for cameras

add system edp consumer data for ov5693 and mt9m114 cameras.

Bug 1391719
Bug 1391722

Change-Id: Ibdd41b6cd39d04c855087f23025218de41ea469c
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/304861
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agodrivers: media: tegra: edp support (new framework)
Timo Alho [Tue, 29 Oct 2013 12:08:17 +0000]
drivers: media: tegra: edp support (new framework)

on ov5693 and mt9m114 (SOC1040)

Bug 1391719
Bug 1391722

Change-Id: I7f8ffb8266d536f72dc2a2b43319cd5760b2d535
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/304860
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: tegra: spi: Add tegra_spi_cs_low callback
Shardar Shariff Md [Fri, 25 Oct 2013 15:34:07 +0000]
arm: tegra: spi: Add tegra_spi_cs_low callback

added tegra_spi_cs_low() callback, called
from spi core for spi client users to set chip
select state(low/high).

Bug 1371286

Change-Id: Ifea4282a46f88c1744c44e6fd6dee7d98d72bc05
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/303904
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: loki: Enable UHS modes
Bitan Biswas [Mon, 21 Oct 2013 09:14:02 +0000]
ARM: tegra: loki: Enable UHS modes

Enable following modes for SDIO
 - SDR104 mode maximum clock as 204MHz
   per characterization data.
 - SDR12 and SDR25 UHS modes are enabled

Bug 1344631

Change-Id: I9829bd95c9f8307dbde13902128a0cc4e28b268b
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/301719
Reviewed-by: Automatic_Commit_Validation_User

5 years agospi: Add spi_cs_low() callback
Shardar Shariff Md [Fri, 25 Oct 2013 15:28:35 +0000]
spi: Add spi_cs_low() callback

spi_cs_low() callback is added for spi client
users to set chip select state(low/high).

prototype:
int spi_cs_low(struct spi_device *spi, bool state);

Bug 1371286

Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Change-Id: I4b2374202267338246262d902d6492d35dc755fb
Reviewed-on: http://git-master/r/303902
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoxhci: tegra: enable runtime PM for xusb
Prashant Gaikwad [Tue, 29 Oct 2013 06:22:03 +0000]
xhci: tegra: enable runtime PM for xusb

Bug 1388533

Change-Id: Idddeab680f6f232dec897b8a6e26515c0d071d3c
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/304682
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: dsi: Fix slow slew rate
Vineel Kumar Reddy Kovvuri [Tue, 29 Oct 2013 06:55:47 +0000]
video: tegra: dsi: Fix slow slew rate

Programmed the recommended register sequence to improve signal swing

Bug 1393348

Change-Id: Ic851ddbdf6ce52c5d378420ecda698334ae2e947
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/304629
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: host: Fix VIC clock gating writes
Terje Bergstrom [Tue, 29 Oct 2013 13:33:42 +0000]
video: tegra: host: Fix VIC clock gating writes

Writes for VIC clock gating registers were incorrect.

Bug 1392299
Bug 1396170
Bug 1397600

Change-Id: Ia59d81d6dcc3368e70f809baa8bf6215d2d9cbba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/304890
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agopower: bq2419x: fix multiple issue
Laxman Dewangan [Tue, 29 Oct 2013 10:17:29 +0000]
power: bq2419x: fix multiple issue

Fixing multiple issue with driver:
- pass the enable time of vbus through the desc.
- Move rtc configuration to core.
- Fix suspend/resume functionality.
- Avoid LP0 only when high current charger is connected.
- Fix checkpatch error.

Change-Id: Iec3c0e6907f5a275fc3d09c5227e7f8a4aacf8d9
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304807
Reviewed-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Tested-by: Darbha Sriharsha <dsriharsha@nvidia.com>

5 years agoARM: tegra: select SYSTEM-PMIC config fro all tegra SoCs
Laxman Dewangan [Wed, 30 Oct 2013 06:05:57 +0000]
ARM: tegra: select SYSTEM-PMIC config fro all tegra SoCs

System PMIC  driver provides the abstraction to configure
pmics for different power off and power on requirements.

Change-Id: I0cebdd060aceafd1809cd333da2867d058e4ca14
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/309445

5 years agopower: reset: system-pmic: make all exported function to extern
Laxman Dewangan [Wed, 30 Oct 2013 06:05:25 +0000]
power: reset: system-pmic: make all exported function to extern

Change-Id: I1652ebad5fec19b072f003f905aadfb0fafbde19
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/309444

5 years agopower: batter-gauge: enhance helper APIs
Laxman Dewangan [Tue, 29 Oct 2013 10:14:47 +0000]
power: batter-gauge: enhance helper APIs

Add following APIs:
- Add helper function to configure RTC.
- Add the APIs to cancel the auto restart.
- Avoud multiple locking and unlocking of wake_lock
- Register thermal zone only if it is required.

Change-Id: Ic473c25968e87786c948366316527b471ab16d35
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304806

5 years agopower: reset: palmas: add power on through RTC expire
Laxman Dewangan [Tue, 29 Oct 2013 10:13:11 +0000]
power: reset: palmas: add power on through RTC expire

Add support to power on system through PMIC RTC event.

Change-Id: I381f1b0fb156c7aec55130f7f9c276d2cb1f16b0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304805

5 years agopower: reset: system-pmic: add rtc event data
Laxman Dewangan [Tue, 29 Oct 2013 10:11:54 +0000]
power: reset: system-pmic: add rtc event data

The system can be power on through RTC event. define RTC event
data so that client can set the power-on case using the RTC.

Change-Id: I84db56c7f742b1c71d2667b896f87eff4af40f76
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304804

5 years agoARM: tegra: ardbeg: print power key wakeup if it is from power key
Laxman Dewangan [Tue, 29 Oct 2013 10:22:54 +0000]
ARM: tegra: ardbeg: print power key wakeup if it is from power key

bug 1396728

Change-Id: I24ed8e2f76ac5cfefea8d0e57e24194371cb14d6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/304808

5 years agoARM: tegra: turn off AVDD_PLL_1V05 rail in lp0
Mallikarjun Kasoju [Tue, 29 Oct 2013 10:29:53 +0000]
ARM: tegra: turn off AVDD_PLL_1V05 rail in lp0

control AVDD_PLL_1V05 using external control so that
it can be turned off in LP0.

Bug 1371114

Change-Id: Iead8b8231ac8bfacb3c25209bfdd932ca9121540
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/304810
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra12: clock: fix battery_edp clock
Timo Alho [Tue, 29 Oct 2013 10:07:26 +0000]
ARM: tegra12: clock: fix battery_edp clock

battery_edp clock is constraining the maximum frequency of GPU. On
T114 this clock was constraining cbus frequency but on T124 gbus
frequency needs to be constrained. This patch fixes the issue.

Change-Id: I26b7f6e98a35ef15455773d4d77d41351c9edf0b
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/304864
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoEDP: remove warning prints of missing GPU clock
Timo Alho [Tue, 29 Oct 2013 09:18:13 +0000]
EDP: remove warning prints of missing GPU clock

GK20A driver does initializes clocks until very late init –
clk_set_rate() is returning error until then. This patch adds graceful
handling of missing gpu clock.

Change-Id: Ia0825985425494675637c20f3d25bc77b24afb91
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/304863
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra11: clock: add missing sbc clock
Shreshtha Sahu [Mon, 28 Oct 2013 11:00:32 +0000]
ARM: tegra11: clock: add missing sbc clock

This patch adds sbc1.sclk:sbc6.sclk clocks missing in
tegra_list_clks[] list.

Bug: 1353715

Change-Id: Ibba2f6455492f006c9fd324e6cc4775d84634e00
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/304344
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: DT: Add DT entry for PWMs and Backlight
Ajay Nandakumar [Tue, 29 Oct 2013 14:21:21 +0000]
ARM: DT: Add DT entry for PWMs and Backlight

Add DT entry for PWM controller and Backlight for NVIDIA's
Tegra 114,124 SoCs.It has 4 PWM controllers.

Bug 1256106

Change-Id: Ia927d3231db1a07490b5027c1f23d8e736173f30
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299035
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: loki: Add ina3221 support for E2549
Jun Yan [Tue, 8 Oct 2013 22:35:46 +0000]
arm: tegra: loki: Add ina3221 support for E2549

Add platform data for ina3221 on E2549 board

Bug 1317330

Change-Id: Ie5a1a354024a496c385de4690a6daff538055245
Signed-off-by: Jun Yan <juyan@nvidia.com>
Reviewed-on: http://git-master/r/301340
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoArm: tegra: clk_get_rate from non atomic context
Puneet Saxena [Fri, 25 Oct 2013 11:31:14 +0000]
Arm: tegra: clk_get_rate from non atomic context

Clk_get_rate() for emc client should be called from non
atomic context.

Bug 1371564

Change-Id: I2b6c1b804dcc0847639757d53a2fdf29124a7bca
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/303862
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoPM / Domains: fix device runtime status print
Prashant Gaikwad [Tue, 29 Oct 2013 08:40:47 +0000]
PM / Domains: fix device runtime status print

Device runtime status is valid only if runtime PM
is enabled or there is no error.

Change-Id: Ie1175aaa54069ec655d669b83f5252f5d92c55b1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/304759
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agomedia: platform: tegra: ar0261: update fuseid read
Phil Breczinski [Sat, 26 Oct 2013 19:07:15 +0000]
media: platform: tegra: ar0261: update fuseid read

Updates the fuse ID read function.  Eliminates fixed sleep time.
Restores previous control register state.

Bug 1379777
Bug 1367436

Change-Id: Idbd7e97d3c52973ec165b6887640e71a8737cc15
Signed-off-by: Phil Breczinski <pbreczinski@nvidia.com>
Reviewed-on: http://git-master/r/304144
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: nvmap: Handle error condition correctly
Alex Waterman [Tue, 29 Oct 2013 18:44:52 +0000]
video: tegra: nvmap: Handle error condition correctly

Make sure to check for both error and NULL when checking the
return from __nvmap_alloc().

Change-Id: I0508d2dd1c5178e539c7f9ba31f2281bb0a8a349
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/305037
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agonet: wireless: bcmdhd: clear hang state on dev open with stop call
Mohan T [Tue, 29 Oct 2013 12:09:34 +0000]
net: wireless: bcmdhd: clear hang state on dev open with stop call

It seems DUT the hang event is not getting cleared by calling
stop in some scenarios. So call stop when the hang flag is set
in the open call before return.

Bug 1391368

Change-Id: Ie7fbb658cc8094c1dd763a082ffc30af5363ba55
Reviewed-on: http://git-master/r/302321
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Tested-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: loki: Re-allocate CPU Vmax thermal trip-points
Alex Frid [Sun, 27 Oct 2013 04:03:10 +0000]
ARM: tegra: loki: Re-allocate CPU Vmax thermal trip-points

Moved CPU Vmax thermal trip-points to SOC_THERM if available,
otherwise kept them on external thermal monitor.

Change-Id: I5318c243f1b7fbcf576e7dd451b5a2e68a3735d5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304158
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: ardbeg: Add CPU Vmax thermal trip-points
Alex Frid [Sun, 27 Oct 2013 04:00:32 +0000]
ARM: tegra: ardbeg: Add CPU Vmax thermal trip-points

Change-Id: Ib139673f91d17533e8e55f61ba2540cd2dbd1e84
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304157
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Add CPU Vmax thermal profile
Alex Frid [Sun, 27 Oct 2013 03:45:08 +0000]
ARM: tegra12: dvfs: Add CPU Vmax thermal profile

Bug 1342499

Change-Id: Ide9c19b50e5567d758ba468cd57b71241b08cfdf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304156
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Don't apply upper bound to Vmax profile
Alex Frid [Mon, 28 Oct 2013 23:17:38 +0000]
ARM: tegra: dvfs: Don't apply upper bound to Vmax profile

Removed warning when Vmax thermal profile entries exceed rail nominal
voltage - the profile limitations are satisfied in this case, anyway.
Still fail profile initialization, and generate warning if Vmin
profile entries are too high.

Change-Id: I107ddd7843c1440d644b089477ae33e5a9fa493b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304562
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dc: fix isomgr bandwidth compuations
Rakesh Iyer [Fri, 19 Jul 2013 00:03:40 +0000]
video: tegra: dc: fix isomgr bandwidth compuations

Allow for minimum bandwidth to be reserved while display is in operation.

Bug 1326337.
Bug 1319943.

Change-Id: I923880928dacccbf73918164d10b6ef3911b1210
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/299603
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: fail propose for removed display
Rakesh Iyer [Mon, 8 Jul 2013 22:41:50 +0000]
video: tegra: dc: fail propose for removed display

If a display has been removed e.g. HDMI we need to fail propose immediately.

Bug 1321777.

Change-Id: If31bfee89914b2f23de12b4e926899dfea9d2adf
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/246343
(cherry picked from commit 86a47ca92dbf3a82fa4d55b5c46c9de98ecde360)
Reviewed-on: http://git-master/r/299602
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: fix isomgr feature issues
Rakesh Iyer [Thu, 27 Jun 2013 01:25:42 +0000]
video: tegra: dc: fix isomgr feature issues

Fix isomgr related code including bandwidth computation.

Bug 1311433.

Change-Id: Ieb0487df1c23c868e1a8608d9e249a0d70325086
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/299601
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: use available bandwidth info
Rakesh Iyer [Tue, 25 Jun 2013 21:22:29 +0000]
video: tegra: dc: use available bandwidth info

Use available bandwidth information to force renegotiation of window configs.

Bug 1311433.

Change-Id: I735c42e77ea7e25912043a13e14e31bae4a07fb4
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/242125
(cherry picked from commit 3a20f9b1d1ccb8d86141e79e32019b6e3a1e5c81)
Reviewed-on: http://git-master/r/299600
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: add asynchronous bw negotiation.
Kevin Huang [Thu, 9 May 2013 16:37:48 +0000]
video: tegra: dc: add asynchronous bw negotiation.

Add asynchronous bandwidth negotiation support for display.

Bug 1197598.

Change-Id: I16c1ba1dcbe790cec0f6b907c5d4071dc3840629
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/299599
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: dvfs: Update CPU DVFS table
Alex Frid [Tue, 29 Oct 2013 05:02:09 +0000]
ARM: tegra12: dvfs: Update CPU DVFS table

Added two new frequencies to CPU DVFS table, and updated CVB
coefficients, accordingly.

Bug 1342499

Change-Id: Ieacbe00193f902f3940a5fe2a2e439aa200a80f8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304673
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agomedia: platform: tegra: Add features for OV7695
Frank Chen [Fri, 4 Oct 2013 21:18:20 +0000]
media: platform: tegra: Add features for OV7695

Adding the following features to ov7695 YUV sensor
- EV Compensation(-2, -1, 0, +1, +2)
- White Balance Modes (Auto, Cloudy, Daylight,
  Fluoresent, Incandescent)

Bug 1327952

Change-Id: Ib0d326daa31aad8bd77e884501a302666c1af0d5
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/302538
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: ardbeg: Set regulator idle mode limit
Alex Frid [Thu, 24 Oct 2013 03:44:52 +0000]
ARM: tegra: ardbeg: Set regulator idle mode limit

Set 5A load limit for E1735 power module regulator.

Bug 1302884

Change-Id: I7e13a7af438e36dc88a1f0164d4b7aa8508e85de
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304488
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dp: Avoid enabling pll_d directly
Daniel Solomon [Mon, 28 Oct 2013 23:27:29 +0000]
video: tegra: dp: Avoid enabling pll_d directly

During setup_clk, SOR enables pll_d and never disables
it afterwards. This consumes power during display off
usecases. There's no need for this call as the DC driver
takes care of (indirectly) enabling pll_d before enabling
SOR and disabling pll_d after disabling SOR.

Change-Id: I574096b5a84640ba378214e203d737c1e673721d
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/304553
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: power: Fix EDP calculator
Alex Frid [Sat, 26 Oct 2013 04:26:46 +0000]
ARM: tegra: power: Fix EDP calculator

Removed hard-coded iddq settings in order to use per-chip iddq value
for EDP calculations.

Change-Id: Ia58d307007c969159037a037c7b81eb93cda93c5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304489
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agodrivers: misc: therm: Clean up work func
Graziano Misuraca [Wed, 16 Oct 2013 17:18:03 +0000]
drivers: misc: therm: Clean up work func

Change-Id: I243ae542480b742461297d3540e756c231dd42ec
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-on: http://git-master/r/300054
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dc: clean up only valid windows
Jon Mayo [Mon, 28 Oct 2013 19:14:46 +0000]
video: tegra: dc: clean up only valid windows

Do not increment syncpoints of invalid windows during controller disable.
Print a warning if a window has an invalid syncpt during disable.

Bug 1396107
Bug 1393193

Change-Id: I38afdcd07fdf3b8ddb6b0c88fff0cdacb3f2951d
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/304463
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Sharath Sarangpur <ssarangpur@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: usb: add remote wakeup callback
Neil Patel [Fri, 11 Oct 2013 18:31:43 +0000]
ARM: tegra: usb: add remote wakeup callback

Drivers can take actions based on remote wakeup events to prevent a
device or the bus from suspending before the incoming data is handled.

Bug 1362837

Change-Id: I55cf26663cbf00bd2eccc60f18aa95ab5777e604
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/289968
(cherry picked from commit 980b0ef762747561fa40b14d3cde33275927b9bb)
Reviewed-on: http://git-master/r/303390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoarm: tegra: tn8: add PMU E1769 support for TN8.
Hayden Du [Fri, 25 Oct 2013 06:43:47 +0000]
arm: tegra: tn8: add PMU E1769 support for TN8.

Change-Id: I5d9bf80c2ab6c330fc6b4be94a4f0d92820b2780
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/303752
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: tn8: add PMU E1769 support for TN8.
Hayden Du [Fri, 18 Oct 2013 06:04:55 +0000]
arm: tegra: tn8: add PMU E1769 support for TN8.

Change-Id: I9a33464b1c1095d80d62094dde3a7be065bc7c13
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/301014
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: remove all t148 simulation references
Bo Yan [Tue, 29 Oct 2013 01:11:05 +0000]
arm: tegra: remove all t148 simulation references

Change-Id: Ic01105b6154bf4e6bcacc1f05e1c19e64d6c7805
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/304590
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agommc: sdhci: tegra: delayed clock gate enable
Bitan Biswas [Tue, 29 Oct 2013 07:24:18 +0000]
mmc: sdhci: tegra: delayed clock gate enable

bug 1299485

Change-Id: Ief6ba6268f1157cf8dc591c677448222ca034297
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304728
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: Tegra12x sdio clock gate enable
Bitan Biswas [Tue, 29 Oct 2013 07:20:46 +0000]
ARM: tegra: Tegra12x sdio clock gate enable

SDIO clock gate is enabled for following T12x
boards:
ardbeg
loki
vcm30_t124

bug 1299485

Change-Id: I01f3777269c8d82899ac427c91618f3a2962a2eb
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304727
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: ardbeg: Enable SDIO SDR104 mode
Bitan Biswas [Thu, 19 Sep 2013 09:32:43 +0000]
ARM: tegra: ardbeg: Enable SDIO SDR104 mode

Enable SDR104 mode for SDIO with clock 204MHz
per characterization data.

Bug 1299485

Change-Id: Ib6c93fb81a7868101153d852883b9c58576b3711
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304726
Reviewed-by: Automatic_Commit_Validation_User

5 years agommc: host: sdhci: sdio delayed clock gate
Pavan Kunapuli [Thu, 24 Oct 2013 13:33:45 +0000]
mmc: host: sdhci: sdio delayed clock gate

Aggressive clock gate degrades sdio performance.
Hence, sdio clock gate is delayed.
 - sdio clock gate is done if no further
   transaction starts within 20msec interval

bug 1299485

Change-Id: Icb7a647bd4c725372173ea65894524f393220843
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304725
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: disable SDIO clock gating
R Raj Kumar [Mon, 23 Sep 2013 08:52:09 +0000]
ARM: tegra: disable SDIO clock gating

SD/SDIO/EMMC Clock gate control done through
board platform data. SDIO clock gate disabled
for all boards.

Bug 1360926
Bug 1299485

Change-Id: I64bd530a1fcb862bc67b363b7ab5537f995a3fd3
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/304724
Reviewed-by: Automatic_Commit_Validation_User

5 years agopower: power_supply: fix build break
Sivaram Nair [Fri, 25 Oct 2013 08:25:45 +0000]
power: power_supply: fix build break

Provide empty implementation for power_supply_get_by_name when
CONFIG_POWER_SUPPLY is not enabled.

Change-Id: Ibb901a470c9affda7ddf279c5098a0b071434b20
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/303792
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoRevert "ARM: tegra12: enable DT support for host1x"
Terje Bergstrom [Tue, 29 Oct 2013 12:00:05 +0000]
Revert "ARM: tegra12: enable DT support for host1x"

This reverts commit 1a48e3a1826b6347b95aa3c1c96ab1c957a240ac.

Change-Id: Ibd58be83afadda460b81def37665ab19e95b1693
Reviewed-on: http://git-master/r/304851
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra12: enable DT support for host1x
Deepak Nibade [Thu, 3 Oct 2013 09:20:05 +0000]
ARM: tegra12: enable DT support for host1x

- make board file changes to enable DT support for host1x
- rename duplicate ISP clock name to tegra_isp.0
  since with DT, device name becomes isp.0 now

bug 1366383

Change-Id: I3b8f08c8c52035dfcd019126774c9d1569499d8c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/299483
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoregulator: palmas: get external control gpio from dt node also
Laxman Dewangan [Fri, 25 Oct 2013 12:14:45 +0000]
regulator: palmas: get external control gpio from dt node also

In Palmas devices, the rails can be controlled by external input pin
and these pins can be driven by GPIO of SoCs.

Add the support to get the gpio number from dt node in this case if it
is gpio controlled.

Change-Id: I675ed3736b8ef162246c8793443bc2d8bcf57c5f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/303871

5 years agoARM: tegra: loki: Pass vcore limits in plat data
Naveen Kumar Arepalli [Thu, 3 Oct 2013 10:07:04 +0000]
ARM: tegra: loki: Pass vcore limits in plat data

Pass boot core voltage, nominal core voltage, min vcore override
voltage limits through platform data for sdmmc1/3/4.

Bug 1344640

Change-Id: I2e0ea481ef5cb2f5bacfd8f559729c1ab0544016
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/300482
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARCH: arm: vcm30t124: Increase LDO5 limit to 3.95V
Ashwin Joshi [Mon, 28 Oct 2013 09:46:32 +0000]
ARCH: arm: vcm30t124: Increase LDO5 limit to 3.95V

Incrase max LDO5 limit to 3.95 V for vcm30t124 board.

Bug 1369885

Change-Id: Id8e816d5bb0a7e0240c4a8d49f1e379b021f197b
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/304310
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bhavesh Parekh <bparekh@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: pcie: Fix issues caused by 3.10 merge
Jay Agarwal [Fri, 25 Oct 2013 12:55:56 +0000]
arm: tegra: pcie: Fix issues caused by 3.10 merge

1. Fix broken pcie_test.ko by exporting required
functions and structures.
2. Move mach/pci.h -> linux/pci-tegra.h as mach is
to be deprecated.
3. Organized add_port function

Bug 1375550

Change-Id: I148444585f35ed912d86aa7eb70533cb7405d078
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/303877
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agovideo: host: vi: split out built-in code
Bryan Wu [Wed, 23 Oct 2013 18:31:15 +0000]
video: host: vi: split out built-in code

VI driver could be a module. Those T124 sepcific functions are
used by other drivers, which make VI driver can't be built as a
module. So split them out to a separated file and always build
it into kernel, then the rest of vi.c driver can be a module.

Bug 1377330

Change-Id: I4a35ddd62f1c3caca09e596603f5f99b16159754
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/289327
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: laguna: add usb vbus_en support
Bibek Basu [Thu, 3 Oct 2013 07:28:02 +0000]
ARM: tegra: laguna: add usb vbus_en support

Add correct fixed regulator support for all
three falvors of Laguna

Bug 1381552
Bug 1372221

Change-Id: I76734f030e10620b3aac6a6d0b33756c25300f66
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/299549
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: laguna: correct sdmmc regulator
Bibek Basu [Mon, 21 Oct 2013 11:13:12 +0000]
ARM: tegra: laguna: correct sdmmc regulator

move the sdmmc0 regulator to SD5.
correct dev_name for pwrdet_sdmmc regulator

Bug 1382004
Bug 1382018

Change-Id: I5c8b5f46fdf34b2010e7aa1ff587acfc2da9d86f
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/301761
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: laguna: remove nct72 skin temp sensor
Bibek Basu [Mon, 21 Oct 2013 09:56:54 +0000]
ARM: tegra: laguna: remove nct72 skin temp sensor

Remove the registration of nct72 skin temp sensor
for Laguna

Bug 1385303

Change-Id: I1672731d107cd8cca384e485ad1bd48977c75e57
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/301736
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: loki: disable nct72 on Thor 195
Sang-Hun Lee [Sat, 26 Oct 2013 02:15:35 +0000]
ARM: tegra: loki: disable nct72 on Thor 195

 - nct72 is not connected to any tdiode Thor 195, so disable

Bug 1394697

Change-Id: Ic5a140d3aa83ec3619da20dfbc02ddaad0f27cb2
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/304116
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agousb: tegra: do not increase rtpm reference on device connect
Prashant Gaikwad [Mon, 28 Oct 2013 04:46:57 +0000]
usb: tegra: do not increase rtpm reference on device connect

RTPM is handled by USB core driver and device is runtime
suspended after some idle time. If reference count is
incremented on device connect then the RTPM status remains
active unless device is disconnected.

Change-Id: I68c96ad8fffaf7f3a4795a6949779b0e5cdef64e
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/304195
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: loki: add loki nff b00 emc table
siddardha naraharisetti [Fri, 25 Oct 2013 23:08:30 +0000]
ARM: tegra: loki: add loki nff b00 emc table

Based on sku, load loki nff b00 emc table.

Bug 1326949

Change-Id: I7710c39387a131d43e932d9b38b0ac351c8fe114
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/304575
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: move irq drivers to drivers/irqchip
Ajay Nandakumar [Mon, 28 Oct 2013 10:16:56 +0000]
ARM: tegra: move irq drivers to drivers/irqchip

Bug 1379891

Change-Id: I18a95deafbc112aa22da66d599e8ffb1c85fedab
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/302909
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Move mach-tegra/{gic.h, pm-irq.h}
Ajay Nandakumar [Wed, 23 Oct 2013 15:30:12 +0000]
ARM: tegra: Move mach-tegra/{gic.h, pm-irq.h}

Moving mach-tegra/gic.h and mach-tegra/pm-irq.h to
include/linux/irqchip/tegra-irq.h so that it helps faclitate the
movement of irq drivers from mach-tegra/ to drivers/.

Bug 1379891

Change-Id: Id062ebc16441ac295df78731c1e44b32e75d3286
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/302884
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: config: vcm30t124: Enable tegra_alt driver
Songhee Baek [Mon, 28 Oct 2013 16:28:35 +0000]
ARM: config: vcm30t124: Enable tegra_alt driver

This change is for enabling tegra-alt ASoC driver and vcm30t124
machine driver.

Bug 1373091

Change-Id: Iffbe782f074da24f9416e5f37bde6ed30bc71a0f
Signed-off-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-on: http://git-master/r/304434
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>

5 years agoARM: tegra: MC: Fix L4T build
Alex Waterman [Fri, 25 Oct 2013 17:30:28 +0000]
ARM: tegra: MC: Fix L4T build

Correct relative paths are necessary for L4T build.

Bug 1395858

Change-Id: Ia112989c8c8d971bb84c58da0c955bd4f7c204b2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/304419
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: ardbeg: update edp settings
Charlie Huang [Fri, 18 Oct 2013 21:51:43 +0000]
ARM: tegra: ardbeg: update edp settings

for ar0261 and imx135

bug 1358215

Change-Id: Ia6871792cdd02f4b37d7d4b2110886fe40832810
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/301405
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agodrivers: media: tegra: edp support
Charlie Huang [Fri, 18 Oct 2013 21:50:08 +0000]
drivers: media: tegra: edp support

Added edp support on ar0261 and imx135

bug 1358215

Change-Id: I9930865d438be7e672435fc792d5c0f1daf70ea0
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/301404
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoALSA: hda:Update logs with platform driver support
siddardha naraharisetti [Tue, 22 Oct 2013 20:39:53 +0000]
ALSA: hda:Update logs with platform driver support

Updated debug logs for the case where the driver is used as
platform driver. On devices where HD-audio controller is on a
proprietery non-pci interface, debug logs referring to pci
device resuled in OOPS. fixed this by updating debug messages
print the device name either pci_name or platform device name.

Bug 1390896

Change-Id: I00f61d9c05473de7c4686d4e5bb1215ee87b72c5
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/302463
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clock: Don't clip EMC max rate to boot rate
Alex Frid [Sat, 26 Oct 2013 02:47:06 +0000]
ARM: tegra12: clock: Don't clip EMC max rate to boot rate

Don't set EMC maximum rate based on boot rate - let EMC DVFS to
determine maximum limit when EMC scaling table is loaded.

Change-Id: I0156ded9907fbda2fa6d42eb26d3b4026eeb5848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304122
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Combine CPU CVB tables
Alex Frid [Tue, 22 Oct 2013 23:26:27 +0000]
ARM: tegra12: dvfs: Combine CPU CVB tables

Combined CPU CVB frequency scaling tables for different chip skus into
one table, and applied per-sku maximum frequency limits to this table.
Since max frequency is specified now explicitly, do not trim list of
CPU frequencies in DFLL mode to fit voltage range (maximum voltage
limit is applied to DFLL voltage control directly, anyway).

Bug 1342499

Change-Id: I425e19ad2437b14cc4b54328a4b94802f8c58c25
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304151
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Set non-zero CPU minimum rate
Alex Frid [Sat, 26 Oct 2013 01:08:58 +0000]
ARM: tegra12: clock: Set non-zero CPU minimum rate

Set minimum 3.1875 MHz rate for both LP and G CPUs on Tegra12.
CPU frequency scaling table never go such low, anyway. However, debug
interface allows to request any rate, and this request would fail for
rates below minimum reachable from backup PLLP at max divider setting
(408/128 = 3.1875MHz).

Change-Id: Ib9541fb56e0a38e124e7d52c8440cf9867ce6baf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/304121
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Calculate regulator idle limits table
Alex Frid [Wed, 23 Oct 2013 00:49:00 +0000]
ARM: tegra: power: Calculate regulator idle limits table

Added EDP calculation of maximum frequency limits in CPU regulator idle
mode based on platform specific idle current, number of on-line CPUs,
and temperature. Updated interface with cpu-tegra driver, respectively.
Expanded EDP debugfs nodes with the new table.

Bug 1302884

Change-Id: If983f3c683a7d0679f6b381916b2790406d602d3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/302661
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Add dynamic CPU regulator mode control
Alex Frid [Thu, 17 Oct 2013 01:50:08 +0000]
ARM: tegra: power: Add dynamic CPU regulator mode control

Operational mode of CPU voltage regulator depends on load current.
Commonly on Tegra platforms this dependency was handled by regulator
h/w itself. There are exceptions, however, introduced on some Tegra12
designs that requires s/w control of the mode.

In order to dynamically control regulator mode based on load,
s/w has to

(a) estimate load based on CPU frequency, number of on-line CPU cores,
and temperature
(b) compare load estimation with regulator specific threshold whenever
any of the above factors changes
(c) change regulator mode when the respective threshold is crossed

This commit adds layer (b) in cpu-tegra driver. It expects existing
Tegra CPU load calculator in EDP driver to implement (a), and provide
look-up table of frequency thresholds for each combination of on-line
CPU cores and temperature ranges. When the respective threshold is
crossed standard regulator mode change interface is called to carry
on (c).

Only switching between IDLE and NORMAL regulator modes is supported.
The respective EDP calculator functions are just stubbed, for now.

Bug 1302884

Change-Id: Iaea42a101aaea239643c0c80a7ad165ece3b1e36
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/301520
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: remove non-upstreamed wifi drivers
Matt Craighead [Fri, 18 Oct 2013 20:50:42 +0000]
ARM: tegra11: remove non-upstreamed wifi drivers

The intent is to migrate to the upstream brcm80211 driver.

Bug 1354953
Bug 1368586

Change-Id: Ib791dd6acbbced7aa6e35854cbc7934009bd1b45
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/301370
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>