Jin Qian [Mon, 12 Sep 2011 19:33:15 +0000 (12:33 -0700)]
ARM: tegra: power: fix build error on tegra_pm_enter routines
Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c
Reviewed-on: http://git-master/r/51852 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861
Jin Qian [Fri, 2 Sep 2011 23:24:01 +0000 (16:24 -0700)]
ARM: tegra: power: do not check time after kernel time suspend
cluster switch for LP0 is called after linux timekeeping suspend,
which turns off timer.
Bug 862504
Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe
Reviewed-on: http://git-master/r/50611 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a
Jin Qian [Fri, 2 Sep 2011 23:22:18 +0000 (16:22 -0700)]
ARM: tegra: power: save cluster switch status before entering LP0
warm boot reads SCRATCH4 to choose wake-up from LP or G
Bug 862504
Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94
Jin Qian [Thu, 1 Sep 2011 02:47:26 +0000 (19:47 -0700)]
ARM: tegra: power: move cluster switch to syscore for LP0
move printk as well since they rely on uart resume in syscore
Bug 862504
Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e
Reviewed-on: http://git-master/r/50240 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b
Jin Qian [Thu, 1 Sep 2011 02:39:57 +0000 (19:39 -0700)]
ARM: tegra: power: fix lp0 suspend
enable pllm and skip io_dpd for lp0
Bug 862504
Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7
Reviewed-on: http://git-master/r/50239 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0
Jin Qian [Wed, 31 Aug 2011 00:23:55 +0000 (17:23 -0700)]
ARM: tegra: power: move cluster switch prolog/epilog from suspend
They're called only when doing cluster switch so move them to
cluster control function.
Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c
Reviewed-on: http://git-master/r/49952 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363
Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f
Jon Mayo [Thu, 28 Jul 2011 00:01:57 +0000 (17:01 -0700)]
ARM: defconfig: tegra3: use REPORT_PRESENT_CPUS
enable reporting of present cpus in /proc/cpuinfo and /proc/stat
Bug 849167
Original-Change-Id: I8651079ff63c7399942d937cb0af126aa67a2fd7
Reviewed-on: http://git-master/r/43632 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R24122a5d7e8b2517e99518a698f89ac3946a76ec
Jin Qian [Wed, 24 Aug 2011 01:15:32 +0000 (18:15 -0700)]
ARM: tegra: power: restore reset handler after lp0
Bug 862504
Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7
Reviewed-on: http://git-master/r/50241 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400
Scott Williams [Wed, 7 Sep 2011 00:19:18 +0000 (17:19 -0700)]
ARM: tegra: Clean up the chip revision decoder
Replace the chip revision decoder with something that is more
extensible and maintainable.
Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50931 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com>
Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136
In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.
Alex Frid [Wed, 24 Aug 2011 05:52:42 +0000 (22:52 -0700)]
ARM: tegra: power: Tune Tegra3 hotplug algorithm
- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.
- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%
Scott Williams [Wed, 31 Aug 2011 15:37:27 +0000 (08:37 -0700)]
ARM: tegra: pinmux: Prevent access to uninitialized pin groups
There is no guarantee that every element in the pin group array
will be used (i.e., initialized) for a particular SOC. Prevent
access to pin group array elements that are not initialized.
Original-Change-Id: I90ea3616f8508b12ffe4a7daf9ff4b2bac057075 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50059 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: Rd6c206b805d180fb3c52be52edfeebed701ca73d
Scott Williams [Thu, 1 Sep 2011 23:20:47 +0000 (16:20 -0700)]
ARM: tegra: Use SATA and PCIE SOC architecture conditionals
Use the SOC architecture conditionals for determining the
presense of PCIE and SATA.
Change-Id: I312d0d1b45fc08e4938260b978d083b113ed9d66 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50379 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Ra949d477a8e96ccc7760c4974ae93909ea054bbb
Scott Williams [Thu, 1 Sep 2011 22:07:44 +0000 (15:07 -0700)]
ARM: tegra: Clean up makefile conditionals
Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50358 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2
Scott Williams [Thu, 1 Sep 2011 22:03:48 +0000 (15:03 -0700)]
ARM: tegra: Clean up power gating code
Clean up conditionals.
Use the generic name of CELP for the LP partition.
Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a
Scott Williams [Thu, 1 Sep 2011 21:59:01 +0000 (14:59 -0700)]
ARM: tegra: Remove unnecessary SOC conditionals
Change-Id: I4ad09ea97db373dbed0764214fc5d98be2e29f7a Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50356 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R5c2b9b638a4e150eb1fa6e1d4f587bb71622efea
Scott Williams [Thu, 1 Sep 2011 21:55:13 +0000 (14:55 -0700)]
ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets
Determine the number of GPU register sets based upon the setting
of ARCH_TEGRA_DUAL_3D.
Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50355 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96
Scott Williams [Thu, 1 Sep 2011 21:47:32 +0000 (14:47 -0700)]
ARM: tegra: Only Tegra3 has TSENSOR
Change-Id: I232d3ae5e037d491d1d8d185e75c1c9a7035cd4c Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50354 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R899f3aaf97ca7f21785749a8675ba1bc461f81f9
Scott Williams [Thu, 1 Sep 2011 02:24:56 +0000 (19:24 -0700)]
ARM: tegra: Use forward looking architecture conditionals
Change-Id: I31f2717327a627ad83e4cc2f083b71fd68fb1465 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50221 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rcaef7248cf06aa01c40b8e5eae13e3a20ed097d3
Scott Williams [Thu, 1 Sep 2011 15:56:31 +0000 (08:56 -0700)]
ARM: tegra: Add SOC architectural capabilities
Add architectural capabilities the at are selected by the top-level
architecture type rather than deriving this knowledge directly from
the top-level type in the code.
Change-Id: I1c1e5d986a65301cf2e474d866f01e4f8c2a5505 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50298 Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R118b523b4c6cac8f4f530f01a1d14ed961d5a085
Scott Williams [Thu, 25 Aug 2011 21:28:10 +0000 (14:28 -0700)]
ARM: tegra: Fix warnings
Change-Id: Ic2cecccf0f4f6e6ca612af2ee07acdbca2ce07a5 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49281 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R59e04e0a46099403284a036de7f35d21c6188d81
Yudong Tan [Thu, 18 Aug 2011 22:29:08 +0000 (15:29 -0700)]
ARM: tegra: power: Call cluster_switch_prolog/epilog for LP1
cluster_switch_prolog is needed to set up car/flow controller registers
for LP1 entry. epilog is needed to clean up some flags in flow controller
after LP1 exit.
Bug 862502
Change-Id: Ib9eeac6fc541cfa644d782071dbd4187255404d8
Reviewed-on: http://git-master/r/47585 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R2c72673ba1b7f04ffa1b760ff54aaf73cf23f09e
Change-Id: I728d5163bff3fb2bd4a2ea7946d2e57cb0854589 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49346 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R470db120396c95bdcafc48ba357652a43d63da82
Scott Williams [Fri, 26 Aug 2011 01:39:56 +0000 (18:39 -0700)]
ARM: tegra: power: Fix build error on non-SMP systems
Can't use NR_CPUS on non-SMP systems. Just use the maximum.
Change-Id: Ie0d6289c3b8bdaada6335e4670c9f6b5ab2bcc93 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49344 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R58abf556bf542b8cf0ee6dd0f091806235f49623
arm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values
The pin-func set by board-xxx-pinmux.c should be one of the 4 possible
values of the pin-func in master pinmux table. Also the safe pin-func
setting should follow the same rule.
If this is not followed then, warnings will be seen whenever a driver
tries to set a pin-func that is not in the master pinmux table. This is
specically seen for the mux values RSVD_X.
The hardware is always programmed with the bit value of setting
(00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table.
For bug 865503
Change-Id: I3933ca0002e099376798cc131690922fefa16868 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48197 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R6d5a11f9f3ab523a2557a512ab85c3ef5f90815a
APIs lock_name(), od_name(), ioreset_name() are called from code for
Tegra3 and above. However, their implementation was not taking care
of this. This was causing 3 warnings during Tegra2 builds.
Change-Id: I4ac4d394c68fd1f8bab5938b2af76c8b92d04a64 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48195 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R4e7e7a4ec3cd7b31a2297bdeedccedc8cbcb5a01
Scott Williams [Tue, 23 Aug 2011 22:52:45 +0000 (15:52 -0700)]
ARM: tegra: Fix build errors when PM_SLEEP is not selected
Change-Id: I2037be4b1309ac1fe9af0ec3e644e0a1a4924857 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48796 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R0840ee98b17984f73f9a5396ab6f86d4d92b744e
Do not switch to clock event broadcast mode until the final CPU
is going into LP2. Switching into broadcast mode on the secondary
CPUs can cause double ticking and/or kernel panics on the primary.
Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48743 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5
ARMv6+ architecture does not allow ioremap on system memory.
lp0 is relocated using ioremap on DRAM. If lp0 vector start address
is in system memory then use memblock_reserve and do not relocate.
Else if it is overlapping with carveout/fb then first remove the
carveout/fb using memblock_remove and then use ioremap.
LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.
Kaz Fukuoka [Thu, 26 May 2011 01:21:32 +0000 (18:21 -0700)]
media: tegra: avp: Clear interrupt registers when AVP starts
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
Bitan Biswas [Fri, 12 Aug 2011 09:32:31 +0000 (15:02 +0530)]
arm: tegra: tsensor: fuse revision corrected
tsensor functionality is enabled based on fuse revision.
The fuse revision is to be interpreted as an unsigned integer
while it is interpreted as a decimal number. Corrected this
in platform source file.
- updated EDP table for AP30 A02 2.5A to match data from Bug 844268
- updated EDP cap for single core on AP30 A02 to 1.3Ghz
- changed EDP table for A01 to match AP30 A02
Original-Change-Id: I1722768f235d63a2f311d082d8126ba071226eb6
Reviewed-on: http://git-master/r/46482 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc98aaffd4568b9ad642696eef5f559d9c7fd7237
Jon Mayo [Wed, 10 Aug 2011 23:16:10 +0000 (16:16 -0700)]
ARM: tegra: la: use lower LA for display clients
In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.
Bug 840688
Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1
Alex Frid [Sat, 6 Aug 2011 01:56:04 +0000 (18:56 -0700)]
ARM: tegra: clock: Use rounded ActMon maximum rate
Used round rate API to determine maximum frequency of Tegra3 activity
monitoring shared users, instead of maximum rate directly. The former
takes into account available PLL/dividers and return actually
reachable frequency.
Bug 860618
Original-Change-Id: I48292c65bfbf58906ab59f86959b0e7155117558
Reviewed-on: http://git-master/r/45711 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Tested-by: Chandrakanth Gorantla <cgorantla@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R2be5b1549b53d2b203ccfe6ea1d1cd2368359d91
Jon Mayo [Thu, 21 Jul 2011 01:49:00 +0000 (18:49 -0700)]
ARM: tegra: la: Add debugfs to latency allowance.
add /sys/kernel/debug/tegra_latency/la_info to print programmed latency
allowance settings.
Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77
Reviewed-on: http://git-master/r/42285 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09
Diwakar Tundlam [Thu, 23 Jun 2011 04:17:19 +0000 (21:17 -0700)]
ARM: Tegra: dvfs: Proc array indep of new T30 char SKUs
- Make process_ids array independent of SKU to avoid confusion when
detecting SKU, speedo_id and parsing process_id.
- Added SKU definitions for characterization SKUs of AP30, T30, T30S
Bug 855816
Original-Change-Id: I925d54ab6d35e8af038cbfe84ef4b4c076cd596d
Reviewed-on: http://git-master/r/43096 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R832f8fb1a34ab700af0c6389fbe5307f334cc54c
Alex Frid [Sun, 24 Jul 2011 03:14:25 +0000 (20:14 -0700)]
ARM: tegra: power: Add package mask to IO pad control
Modified dynamic IO pad configuration control to support SoC package
dependencies: set into "no-io-power state" IO pads that are not bonded
out on the particular package. Updated IO power detect table to account
for differences in Tegra2 and Tegra3 architecture.
Bug 853132
Original-Change-Id: I5f0aedfa784173cc37251ccf4e1dfb4d919db96e
Reviewed-on: http://git-master/r/42785 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Rebase-Id: R46208845c32e25340de6b1cebfb6b617c6c7ce4d
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.
Alex Frid [Wed, 20 Jul 2011 23:15:25 +0000 (16:15 -0700)]
ARM: tegra: power: Control IO pad configuration dynamically
Tegra IO pads are automatically re-configured when IO power level is
changed. Current code keeps auto-detection cells in default, active
state all the time. This change will allow turning off cells when IO
power is stable, and activate them only during power transitions.
In addition IO pads will be set into "no-io-power" state after the
respective regulator is disabled, and re-configured back for regular
operations before regulator is re-enabled.
Dynamic IO pad control introduced in this commit is still disabled
by default on all tegra platforms.
Yen Lin [Sun, 10 Jul 2011 23:07:39 +0000 (16:07 -0700)]
arm: tegra: ahci/sata: enable sata rails/partition at init
Enable sata rails and sata partition when driver initializes
- add sata_oob and cml1 clocks to sata powergate partition.
- set sata and sata_oob clock source using clk_set_parent API.
- fix a bug in while(timeout) loop
Bug 836589
Original-Change-Id: Iddc08bf851ffc83d45bd6aed4df85cde3b13f0e4
Reviewed-on: http://git-master/r/41314 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R500e99ac50d1e3c0851958b1c83316dded00d617
Added throttling enable reference counting, so that it can be
controlled by drivers for different thermal sensors (e.g, on
chip and device skin sensors).
Fixed possible dead-lock when cancel delayed work synchronous is
called while locked with the very same mutex that protects work
function.
Alex Frid [Sun, 10 Jul 2011 04:33:37 +0000 (21:33 -0700)]
ARM: tegra: clock: Unify CPU set rate paths
Made sure that CPU thermal and edp limits are applied on all CPU set
rate paths: cpufreq governor, thermal throttling, edp notification,
power management notification. Also included auto-hotplug governor
state update in all these paths (current code does not apply the
limits, or does not include auto-hotplug on some rate change paths).
One exception - keep current functionality for suspend notification:
set pre-defined CPU rate, and force auto-hotplug idle state.
- Added table with EDP Capping values for different SKUs/regulator
currents in new file edp.c
- New entry point tegra_init_cpu_edp_limits()
- Added DebugFS entry under debug/edp to list the currently
selected EDP table
- Populated EDP table in edp.c with data from Bug 844268
- edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c
both read from there
Alex Frid [Wed, 13 Jul 2011 02:34:35 +0000 (19:34 -0700)]
ARM: tegra: clock: Clean tegra3_emc.c macro style
Original-Change-Id: I472be800ad84b79783577264b51c6478aa4bb41b
Reviewed-on: http://git-master/r/40769 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R0b3b4124618ecafc6f83ff165634ebba664a24a1
Alex Frid [Tue, 12 Jul 2011 05:55:04 +0000 (22:55 -0700)]
ARM: tegra: clock: Support Tegra3 EMC DFS table revision
Support Tegra3 EMC DFS table revision 3.1 that includes two additional
EMC shadow registers (reserved with previous table revision 3.0).
Bug 836260
Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb
Reviewed-on: http://git-master/r/40749 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478
Fixed EMC clock change procedure to skip XM2CLKPADCTRL register during
shadow burst write, and set it within unshadowed section.
Bug 836260
Original-Change-Id: Ief92c7d3957c9685b8c528297da2e905159a530d
Reviewed-on: http://git-master/r/40748 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Thomas Cherry <tcherry@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R5016ffd224db2b3eb6639a6b33063d1c27456b24
ARM: tegra: add support for hardware statistic counter
Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS
modules. This commit adds the support for AVP statistics gathering and
controlling avp clock during video playback.
Alex Frid [Wed, 29 Jun 2011 03:50:29 +0000 (20:50 -0700)]
ARM: tegra: clock: Add Tegra3 emc high voltage bridge
On Tegra3 platforms emc configurations for DDR3 rates below 300MHz
can not work at high core voltage; the intermediate step (bridge) is
mandatory when core voltage is crossing the 1.2V threshold (fixed for
Tegra3 arch). In addition emc must run above bridge rate if any other
than emc clock requires high voltage.
EMC bridge is implemented as a special emc shared user: its rate is set
once during emc dvfs table initialization; then, the bridge is enabled
or disabled when sbus and/or cbus voltage requirement is crossing the
threshold (sbus and cbus together include all clocks that may require
voltage above threshold - other peripherals can reach their maximum
rates below threshold).
Alex Frid [Mon, 27 Jun 2011 21:36:58 +0000 (14:36 -0700)]
ARM: tegra: clock: Use bus lock to protect shared bus update
Protected shared bus update with bus lock - common for all shared bus
users (update procedure was already covered by individual shared users
locks, but it did not prevent concurrent access to shared rates list).
Karan Jhavar [Thu, 9 Jun 2011 21:50:35 +0000 (14:50 -0700)]
ARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3
By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions. Also
3D,3D1 and MPE are not powergated at startup.