Alex Frid [Fri, 5 Jun 2015 03:34:35 +0000 (20:34 -0700)]
platform: tegra21: Support EMC/CPU ratio from DT
Added Tegra21 cpufreq driver support for parsing T210 EMC scaling data
compatible with DT binding defined in nvidia,cpufreq-tegra.txt, and
initialized EMC/CPU ratio table accordingly.
Change-Id: I8dd8ed41f8af8d66217f609b1b419f04bcbfd0e8 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/755352 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
Change-Id: I8672ddc2d21aff1bfe6c1a304b9f1ae71f8f7a2e Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/755351 Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
Michael Hsu [Tue, 13 Jan 2015 00:22:17 +0000 (16:22 -0800)]
net: wireless: bcmdhd: Add custom scan policy.
Add sysfs node to allow wifi scan policies to be selected / added / removed.
Each wifi scan policy consists of:
- policy name
- one or more scan rules
Each wifi scan rule consists of:
- wait time before starting this scan rule
- scan parameters
-- home channel away time
-- number of probes per channel scan
-- active, passive scan time
-- home channel dwell time (between channel scans on non-home channel)
-- channel list to scan
Alex Waterman [Wed, 10 Jun 2015 20:53:23 +0000 (13:53 -0700)]
gpu: nvgpu: Check for split_order > max_order
When choosing an order of buddy to start splitting from (happens when
no buddies of the requested alloc order exist) don't sit in the while
loop past max_order. This makes no sense and hangs the system.
gpu: nvgpu: vgpu: support additional notifications
Client notification support is now added for the following:
- stalling and non-stalling GR sema release
- non-stalling FIFO channel intr
- non-stalling CE2 nonblockpipe intr
video: tegra: nvmap: set proper value for min_clen
min_clen value can't be greater than max_clen. Therefore,
in case min_clen value is equal to PAGE_SIZE and max_clen is zero, reset
min_clen value to zero.
In t186, following output was seen on reading the /d/nvmap/stats/compression
debugfs after mouting the debugfs node.
compression algo: lzo
compression %: 0
uncompressed non-zero bytes: 0
compressed non-zero bytes: 0
compression non-zero bytes %: 0
zero filled page bytes: 0
zero filled bytes %: 0
min compress bytes: 4096
max compress bytes: 0
average compress bytes: 0
Bitan Biswas [Wed, 3 Jun 2015 11:54:10 +0000 (17:24 +0530)]
rtc: RTC_SPEC_2006_TEST fix set hw time logic
We see system time lag by more than 10sec after
10min LP0 test.
Problem was traced to sync_to_rtc_time call after
LP0. sync_to_rtc_time calls rtc_hctosys() which
has code specific to CONFIG_RTC_SPEC_2006_TEST
that modifies RTC time.
Fix the logic of CONFIG_RTC_SPEC_2006_TEST
so that hardware time is updated only if
time is before 2013.
Alex Waterman [Wed, 10 Jun 2015 17:25:10 +0000 (10:25 -0700)]
gpu: nvgpu: Swap order of free/rb_erase
If rb_erase() is called after __balloc_do_free_fixed() then the
rb_tree code crashes when trying to dereference the possibly changed
(or poisoned in the case of debugging) data in the rb_node.
Change-Id: I4a4456a5ec453fd9ab117c804dc19b2c048a61d4 Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/755646 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Ian Stewart <istewart@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Alex Waterman [Thu, 4 Jun 2015 23:00:52 +0000 (16:00 -0700)]
gpu: nvgpu: Remove simulation WAR
The WAR put into simulation to avoid a simulator crash can now be
removed (c85be1a0968de813fe9b99ebd5c261dcb0ca8875). The first issue
with the failing test was found to be GPFIFO entries that were not
invalid.
Other issues are still present with the test and are fixed in a
later commit.
Alex Waterman [Fri, 5 Jun 2015 21:04:12 +0000 (14:04 -0700)]
gpu: nvgpu: WAR for bad GPFIFO entries from userspace
Userspace sometimes sends GPFIFO entries with a zero length. This
is a problem when the address of the pushbuffer of zero length is
larger than 32 bits. The high bits are interpreted as an opcode and
either triggers an operation that should not happen or is trated as
invalid.
John Moser [Fri, 22 May 2015 18:48:53 +0000 (11:48 -0700)]
ARM64: DT: Hawkeye: Update camera edp consumers
Add sysedp consumer DT definition for the Hawkeye front camera sensor
and adjust read camera sensor power state to account for Hawkeye
regulator efficiencies.
Laxman Dewangan [Fri, 5 Jun 2015 11:53:01 +0000 (17:23 +0530)]
ARM: tegra: hawkeye: use pmc iopower driver for IO POWER control
On T210, there is no auto power detect logic for most of rail and
SW need to override the PMC configuration as per power tree.
Also when IO rail state get change, it is require to control
NO_IOPOWER of PMC for power save and it is done through regulator
notification.
On above context, mode the power detect driver to io-power driver
to control the NO_IOPOWER register.
Laxman Dewangan [Fri, 5 Jun 2015 11:50:37 +0000 (17:20 +0530)]
platform: tegra: add driver for PMC IO power control
Add driver to control the IO Power through PMC based
on IO rail state and there state change. The notification
event generated from regulator driver at PRE-DISABLE and
POST-ENABLE which will be used for enabling/disabling
IO power.
Laxman Dewangan [Thu, 4 Jun 2015 12:14:20 +0000 (17:44 +0530)]
ARM: tegra21: hawkeye: move manual edited pinconfig to different dtsi file
Pinmux is generated automatically for Hawkeye. Moving manual addition
on pinmux to new file i.e. pinmux-manual to untouch the auto-generated
dtsi file for pinmux.
Laxman Dewangan [Sat, 6 Jun 2015 12:04:58 +0000 (17:34 +0530)]
regulator: max16989: add max16989-new as new compatible/id
Add new compatible and device id as max16989-new to support it
from DT.
Currently the device id is max16989 and when compatible is set as
max16989, the max15569 driver get selected as their compatible value
is max16989x and it matchess with DT.
After this change, DT will set compatible as max16989-new to select
max16989 new driver.
Alex Frid [Fri, 29 May 2015 02:52:21 +0000 (19:52 -0700)]
platform: tegra21: Support cpufreq table from DT
Added Tegra21 cpufreq driver support for parsing T210 CPU scaling data
compatible with DT binding defined in nvidia,cpufreq-tegra.txt, and
initialized cpufreq scaling table accordingly.
Change-Id: I609a9b4143e7b3df3422d4be0d5c2cd7eb4ba64a Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/749066 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
Change-Id: Ie78b0fb3b3c32aa74560b16f618dc39934c8fe28 Signed-off-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-on: http://git-master/r/735385
(cherry picked from commit d29d21798accbd8a016a081751ff5be011a50cab)
Reviewed-on: http://git-master/r/746573 Reviewed-by: Steve Lin <stlin@nvidia.com> Tested-by: Steve Lin <stlin@nvidia.com>
Sivaram Nair [Tue, 2 Jun 2015 23:01:41 +0000 (16:01 -0700)]
firmware: tegra: reorganize mail ops
Re-arrange the mailing functions in order to introduce platform specific
mail ops. This patch essentially moves some shared code into platform
specifc files.
Change-Id: I87a65395fc4682e92fad432a1a53f9d267319f94 Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/744492 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Change-Id: I49a66143ce9233f3fb90be6713c90180bd77646b Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/748533
(cherry picked from commit c4db23cc4ed55a4d8c1f3551fcd2a39bfbf61dae)
Reviewed-on: http://git-master/r/749254 Reviewed-by: David Schalig <dschalig@nvidia.com> Tested-by: David Schalig <dschalig@nvidia.com> Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com> Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Mark Kuo [Tue, 12 May 2015 03:03:39 +0000 (11:03 +0800)]
drivers: platform: tegra: fix UTMI tracking delay
Set the UTMI pad tracking delay to 50us before we turn off pad tracking
clocks. The total time required to complete tracking from the time
PD_TRK is deasserted by SW = (TRK_START_TIMER + TRK_DONE_TIME + (2 *
TRK_DONE_RESET_TIMER)) = (31 + 100 + 2*10) = 151 cycles.
SW delay should keep at least 2x time = 300 cycles (=50us assuming
TRK_CLK of 6M) to give enough margin.
Hans de Goede [Fri, 16 Jan 2015 15:54:02 +0000 (17:54 +0200)]
xhci: Silence "xHCI xhci_drop_endpoint called with disabled ep ..." messages
When re-applying the configuration after a successful usb device reset,
xhci_discover_or_reset_device has already dropped the endpoints, and free-ed
the rings.
The endpoints already being dropped is expected, and should not lead to
warnings. Use the fact that the rings are also free-ed in this scenario to
detect this, and suppress the "xHCI xhci_drop_endpoint called with disabled
ep ..." message in this case.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
--
Changes in v2:
Move the ring check to only guard the xhci_warn, so as to avoid side-effects
in case we have a scenario where the rings are free-ed, but the endpoint is
not yet dropped. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Change-Id: I94392cf985208f96c7102e5115268c3460338a46 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/721398
(cherry picked from commit 291516cede2ff78d33857251ccb7ef1e3eb2ac9a)
Reviewed-on: http://git-master/r/752496 Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Laxman Dewangan [Thu, 4 Jun 2015 10:00:19 +0000 (15:30 +0530)]
ARM: tegra21: make pinmux drive register range to 0x8d8 to 0xb78
Include the PAD control for QSPI i.e. QSPI comp control and
LPBK control inside driver control so that it can be configure
through pinmux DT for desired value.
Laxman Dewangan [Wed, 3 Jun 2015 12:09:22 +0000 (17:39 +0530)]
ARM: tegra210: Set IO PAD default voltage to 1.8V which only work on 1.8V
On T210, some of IO pads are designed to work on two voltages 1.8V
and 3.3V. The IO-PAD SPI-HV is having the autodetect capability to
detect the voltage level from platform but for other IO PAD, the
capability is removed as part of 20nm design. Hence SW need to
explicitly set the PWR-DET register for the other IO PADS as per
power tree.
All IO pads are not the capable of working on 1.8V and 3.3V
although there is PWR-DET bits on the power detect registers.
These are dummy on nature and just available for backward
compatibility.
The IO pads are:
SPI-HV:
Autodetect capability and 1.8/3.3V support.
GPIO, SDMMC1, SDMMC3, AUDIO_HV:
Work on 1.8V and 3.3V, SW need to set PWR-DET bit.
AUDIO, CAM, DBG, DMIC, PEX-CTRL, SPI, UART, SYS, BB:
Only work on 1.8V.
Configure the IO pad volateg to 1.8V which works on 1.8V only to
match with power tree.
Laxman Dewangan [Mon, 1 Jun 2015 10:21:32 +0000 (15:51 +0530)]
ARM: tegra: initialise GPIO IO pad through platform-io-pad-voltage
Bootloader initialise the GPIO IO pad voltage through dt property
platform-io-pad-voltage, provide the pad voltage through this
property. Kernel does not use this property.
Konsta Holtta [Fri, 6 Mar 2015 14:33:43 +0000 (16:33 +0200)]
gpu: nvgpu: add per-channel refcounting
Add reference counting for channels. A channel is freed only when its
refcount goes to zero, and the free channels are kept in a list
protected with a mutex since the refcounts alone are not enough for
taking a dead channel into use.
Each use of a channel should have a reference taken right before or held
by the caller. Taking a reference of a wild channel pointer may fail, if
the channel is already dead. Lifetime of the references may be quite
wide, such as one for a whole channel fd, or one during a job
submission.
The last user of a channel might eventually be the threaded interrupt
handler, so add a scheduled work for actually freeing the channels whose
reference counts go to zero there, because freeing needs interrupts.
Some of the free-sensitive functions used in the interrupt are also used
elsewhere, so a purging loop is added whenever such entry point ends.
Change-Id: I2301e15f2db01b281c060aa1f7261396f68499e7 Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/753293 Reviewed-by: Amey Asgaonkar <aasgaonkar@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Gary Fitzer <gfitzer@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
Change-Id: I191704a12f99272e018ff37bee3fe1634a19b53b Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/751132 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
Alex Frid [Tue, 2 Jun 2015 02:48:02 +0000 (19:48 -0700)]
ARM64: tegra: Separate common power DVFS definitions
Moved common for all platforms power DVFS definitions from E2174 board
DT include file into a separate file with all nodes disabled. To keep all
DTs unchanged, included new file into E2174 board file, and re-enabled
appropriate E2174 nodes.
- Honor device tree status disable mechanism by unloading driver without any
communication with device.
- See Documentation/devicetree/bindings/iio/iqs253-ps.txt for ability to
disable AND leaving device in a low power state.
Daniel Solomon [Wed, 20 May 2015 21:38:59 +0000 (14:38 -0700)]
arm: tegra: hawkeye: apply backlight transfer function
Adjust backlight update requests to create a nonlinear
change in brightness (smaller increments at lower
backlight levels, larger increments at higher backlight
levels).
The current curve data is borrowed from Shield Tablet 8.
Daniel Solomon [Wed, 20 May 2015 21:30:00 +0000 (14:30 -0700)]
backlight: lp855x: add support for backlight curve
By default, backlight updates are linear with respect
to brightness. In some cases it's desirable to use
specific transfer functions instead of a simpler linear
response.
This change adds bl_curve to the LP855x platform data,
a LUT used to implement backlight transfer functions.
LUT data is parsed from DT.
Disabled the /dev/kmem device on t210 by disabling the CONFIG_DEVKMEM config.
This device is already disabled on t124 and t132 too.
kernel panic is observed when we try to read and write from /dev/kmem device.
Currently, there is no real usecase which needs /dev/kmem device. And
there are some security concerns on keeping it enable. Therefore,
disabled the /dev/kmem device.
iommu/tegra: smmu: protect page table walks with as->lock
page table walks in iova_to_phys and iovainfo debugfs need to be
protected from page table updates in order get correct snap shot
and to avoid updates page tables while trying to dump it
Arto Merilainen [Wed, 27 May 2015 12:05:13 +0000 (15:05 +0300)]
video: tegra: host: vi: Enable IRQ during poweron
Currently VI IRQ is enabled when the device node is opened, however,
this approach is vulnerable to races and it does not guarantee that
the VI device is kept on after configuring it.
This patch moves IRQ enablement and VI configuration to the device
->finalize_poweron callback which is called when the device is
powered. The patch also moves the disablement of the IRQ to
->prepare_poweroff callback which is called before turning off the
device.
This patch also reorders the deinitialization sequence to account
the changes while interrupts are being disabled.
In order to avoid cases where the VI comes up in state that would
trigger interrupts immediately, the IRQs are kept masked after
turning on the IRQs. Userspace can enable them through submit.
Arto Merilainen [Wed, 27 May 2015 20:36:31 +0000 (23:36 +0300)]
video: tegra: host: Fix module deinit
This patch reworks module deinitialization to call prepare_poweroff
only if runtime pm is disabled. In case pm runtime is enabled, the call
may lead to multiple calls against prepare_poweroff. The poweroff
sequence is fixed in cases where pm runtime is disabled.
Additionally, this patch fixes the deinitialization in cases where
there is a master-slave relation between devices; If device has a
slave device, the master information from the slave device is wiped
out. This allows the slave device to determine if the master has
already been disabled.
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