5 years agoxhci: tegra: support HSIC ports
JC Kuo [Thu, 1 Aug 2013 15:03:55 +0000]
xhci: tegra: support HSIC ports

This change add HSIC ports support to tegra XHCI host controller.
HSIC hub can be enumerated by XHCI host successfully.

Wakes from U3/ELPG/LP0 by either host or device initiated resume
signaling are also working.

bug 1301838

Change-Id: Id7e6fd949194489c6c7d0f212c659f11de85417e
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/256882
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra: T12x wake table add UHSIC wake events
JC Kuo [Wed, 31 Jul 2013 07:37:06 +0000]
ARM: tegra: T12x wake table add UHSIC wake events

Add UHSIC wakes to T12x wake table so that UHSIC line wake events can
wake system from LP0.

bug 1301838

Change-Id: I6d3345eab316cdc0f7d54837f1ae564f4b821fdb
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/256881
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Joy Wang <joyw@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agousb: xhci: tegra: enable clock after unpowergate
joyw [Tue, 6 Aug 2013 08:28:42 +0000]
usb: xhci: tegra: enable clock after unpowergate

Follow PG, enable host partition clock after unpowergate
host partition.

Bug 1333946

Change-Id: I47d7bfaedded3d8ca07edd9c1315ade2cccdc579
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/258633
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoARM: configs: Enable SMP for bonaire_sim
Alex Van Brunt [Mon, 5 Aug 2013 23:16:49 +0000]
ARM: configs: Enable SMP for bonaire_sim

Change-Id: Ic1c0f457daa7b242c4e7ac557c718c6c4c5ad489
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/258380
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: nvmap: Fix compile error in nvmap.h
Alex Waterman [Mon, 5 Aug 2013 23:04:44 +0000]
video: tegra: nvmap: Fix compile error in nvmap.h

When page pools are disabled an inline function gets compiled that
has no default return. This generates a warning and causes main to
fail compilation.

Bug 1343106

Change-Id: I8ac23e43e7832c4cedff73d0a8735b51f0760af2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/258377
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra14: clock: Allow G CPU min rate same as LP backup
Alex Frid [Mon, 17 Jun 2013 23:30:47 +0000]
ARM: tegra14: clock: Allow G CPU min rate same as LP backup

Changed cpufreq table generation to support G CPU minimum rate as low
as LP CPU back-up rate.

Bug 1262597

Change-Id: I590e01b6a52b6d1bc61a84c77bffe05f54a3d1d6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239452
(cherry picked from commit 8d402bfcf48ad96cf5a588148144877de5674dd5)
Reviewed-on: http://git-master/r/258310
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: power: Save clock configuration on LP1BB entry
Alex Frid [Mon, 17 Jun 2013 22:03:40 +0000]
ARM: tegra14: power: Save clock configuration on LP1BB entry

Change-Id: If8ca43f947005187ebe03b49ccc22387db21885d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239434
(cherry picked from commit 3871cdd921a315c5c69395d9350dc975c1526c8c)
Reviewed-on: http://git-master/r/258309
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: clock: Add interface to set LP CPU idle rate
Alex Frid [Sun, 12 May 2013 05:56:45 +0000]
ARM: tegra14: clock: Add interface to set LP CPU idle rate

Added interface to set LP CPU idle rate by direct (i.e., underneath
cpufreq governor) backup PLL rate control. This interface is not used
by cpu idle governor, yet.

Change-Id: I26a6c1a0169d08e0881799f36433a362d2f1c8aa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238754
(cherry picked from commit 5cb065936ac0cd32a039e3406e053dcd3f9fcf5e)
Reviewed-on: http://git-master/r/258308
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Boost CPU rate for EMC bus update
Alex Frid [Sun, 12 May 2013 04:50:33 +0000]
ARM: tegra14: clock: Boost CPU rate for EMC bus update

Set CPU rate to backup rate during EMC clock bus update on LP CPU.
This would allow to reduce the worst case of EMC clock update latency
when CPU is running on LP cluster at sub-backup rates.

Since backup rate is guaranteed to be safe at minimum voltage boosting
and restoring rate can be done underneath dvfs and cpufreq governor.
Used sequence counter mechanism to make sure new governor rate setting
(that may happen during EMC bus update) is not overwritten when backup
rate is restored.

Bug 1278984

Change-Id: Ic66a5d50139c61dba4457425002f10b0aabaffeb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238753
(cherry picked from commit 6b107a7da43c87ce21b182b50805e1602b5d8cac)
Reviewed-on: http://git-master/r/258307
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Re-factor and expand host1x bus
Alex Frid [Sun, 9 Jun 2013 03:27:44 +0000]
ARM: tegra14: clock: Re-factor and expand host1x bus

- Set host1x dev_id = "host1x" and con_id = NULL (these definitions
were used before conversion of host1x to shared bus; during conversion
ids were inadvertently swapped - restored now)

- Add cap, and floor, shared users to host1x bus. Attached cap user to
core cap interface.

Change-Id: I7a9823889ca9e0a8d18856aef4470e0c2e7318c5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238748
(cherry picked from commit eb9fcb97e0220af42b732713885967252ba32164)
Reviewed-on: http://git-master/r/258306
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Re-factor and expand host1x bus
Alex Frid [Sat, 8 Jun 2013 06:42:11 +0000]
ARM: tegra11: clock: Re-factor and expand host1x bus

- Set host1x dev_id = "host1x" and con_id = NULL (these definitions
were used before conversion of host1x to shared bus; during conversion
ids were inadvertently swapped - restored now)

- Add cap, and floor, shared users to host1x bus. Attached cap user to
core cap interface.

Change-Id: I75d73964fc8f74558ba4ac555a2b018bc554e88a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238746
(cherry picked from commit 0da8b11f8d90bc1a00ab1e62f36f184bf64db66f)
Reviewed-on: http://git-master/r/258305
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Turn Off memory PLLs in resume
Alex Frid [Thu, 13 Jun 2013 04:10:13 +0000]
ARM: tegra11: clock: Turn Off memory PLLs in resume

Turned Off memory PLLs (PLLM or PLLC) in clock resume if they are left
enabled by LP0 or LP1 exit code, but not used as EMC clock sources.

Change-Id: I017e79007873d8d4b918853e08e0cc27a424e310
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238745
(cherry picked from commit ab02ca044fe93aceb6e32f7daa24ab5d9dcb2fd1)
Reviewed-on: http://git-master/r/258304
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Increase number of rail stats bins
Alex Frid [Tue, 14 May 2013 21:55:14 +0000]
ARM: tegra: dvfs: Increase number of rail stats bins

Change-Id: Ia18237f06e407f14b9ab10758fc9eb16fb483cb9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/228510
(cherry picked from commit 26f1e60b69ce8fe4b2202df1c358d38a92bc226d)
Reviewed-on: http://git-master/r/240016
(cherry picked from commit 525569c6658f12e528d38bca11c510a00ec59a64)
Reviewed-on: http://git-master/r/258272
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: clock: Show ISO/BW marginal rates in clock tree
Alex Frid [Thu, 23 May 2013 02:35:53 +0000]
ARM: tegra: clock: Show ISO/BW marginal rates in clock tree

Change-Id: I8b1b55dc5684e95d7074f84f667d4242410a29f2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238750
(cherry-picked from commit a8556ee16c8da597a399fb592f41c4b3ba7f5c8f)
Reviewed-on: http://git-master/r/258271
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dvfs: Separate dvfs rail safe steps up/down
Alex Frid [Sun, 16 Jun 2013 00:52:40 +0000]
ARM: tegra: dvfs: Separate dvfs rail safe steps up/down

Separated safe voltage steps definitions for dvfs rail transitions
up and down. For now keep steps the same on all tegra platforms.

Bug 1306654

Change-Id: Ica06149577d42ea8c30aa15f642642ebe552de1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239133
(cherry picked from commit 7f0789482589fa1de8e6bf6f800032fb6b87b58f)
Reviewed-on: http://git-master/r/258270
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: mc: Handle spurious interrupts
Alex Waterman [Fri, 2 Aug 2013 00:24:08 +0000]
ARM: tegra14: mc: Handle spurious interrupts

T114 is not the only chip that appears to generate spurious MC
interrupts. This patch expands the ability to handle such
interrupts to all chips.

Bug 1325378

Reviewed-on: http://git-master/r/257181
(cherry picked from commit d9c0356b2d66c57f6978595710ad4d2aed690bba)
Change-Id: I5431f8f11714428c0219a4074a09ae9eeb9e218c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/258254
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: emc: Derating support
Alex Waterman [Wed, 3 Jul 2013 21:55:14 +0000]
ARM: tegra: emc: Derating support

Add support for derating via keeping two separate sets of EMC tables.
One set is nominal, the other set is derated. Based on the temperature
reported by the DRAM the EMC thermal driver can specify which set of
tables the EMC driver should use when swapping frequencies.

This patch also adds support for a more graduated response to rising
temperature. The DRAM reports 3 levels of refresh and derating
requirements:

  0x4: Refresh x2
  0x5: Refresh x4
  0x6: Refresh x4 + derating

The particular combination of refresh modification and derating is now
picked based on the particular level of throttling necessary.

This feature is not imlpemented in older chips. The old approach is
maintained - just a 4x refresh timing for all temperature throttle
states.

Reviewed-on: http://git-master/r/252624
(cherry picked from commit 5073cf9a13344c7e9c35475bce17539615ec4956)
Change-Id: I16f0477a0b0eadc194c9f1f48a66a0bf098b0df3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257646
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: emc: Set DATA_SEL_DPD based on freq
Alex Waterman [Tue, 16 Jul 2013 22:49:59 +0000]
ARM: tegra14: emc: Set DATA_SEL_DPD based on freq

For frequencies above 408 MHz, disable DATA_SEL_DPD in the
EMC_SEL_DPD_CTRL register.

Bug 1270473

Reviewed-on: http://git-master/r/249954
(cherry picked from commit 7557508927d2b513dfa7bbb02a12f6e25f24878f)
Change-Id: I24859c57b45f1d072e853907ab2eb77f3c162172
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257645
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Update DFLL bypass start/suspend/resume
Alex Frid [Fri, 2 Aug 2013 05:43:18 +0000]
ARM: tegra: power: Update DFLL bypass start/suspend/resume

- Initialized DFLL before legacy dvfs if DFLL bypass is enabled
(reversed common initialization order: first legacy dvfs - then DFLL,
since  DFLL bypass device is used as regulator by legacy dvfs)

- Isolated DFLL output from voltage supply on entry to any state with
CPU cluster powered down (suspend, cluster idle), and resumed normal
operation on exit. This is necessary to avoid unpredictable effect of
DFLL output on CPU voltage during power transitions.

Bug 1310396

Change-Id: Ie42b92633367337ebc08200ab425baaf9043d133
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257346
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: ardbeg: Add DFLL bypass device
Alex Frid [Thu, 1 Aug 2013 22:28:31 +0000]
ARM: tegra: ardbeg: Add DFLL bypass device

Added dfll bypass regulator definitions for ardbeg board. Since
initial regulator voltage cannot be read, initialize it to nominal
level explicitly.

Bug 1310396

Change-Id: I580c4c7825f1e279b98b73002638a8e9bc5c4aea
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257345
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: dvfs: Add offset to rail alignment
Alex Frid [Fri, 2 Aug 2013 04:02:05 +0000]
ARM: tegra: dvfs: Add offset to rail alignment

With the introduction of analog PWM regulator on Tegra12 platforms,
minimum cpu voltage may not be exactly aligned with PWM steps. The
respective offset is specified by platform data early enough for dvfs
initialization, and accounted for when rounding dvfs cvb voltages.

Bug 1310396

Change-Id: I4ff570a5c0519b85085b3b5e22076b906e95068c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257344
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: dvfs: Add DFLL bypass interfaces
Alex Frid [Tue, 30 Jul 2013 07:15:31 +0000]
ARM: tegra: dvfs: Add DFLL bypass interfaces

When DFLL voltage supply is connected to CL-DVFS control logic via
PWM interface, the respective regulator can be accessed only via
CL-DVFS registers.

This commit has added set/get APIs for direct access to CL-DVFS force
output register to be used by dfll bypass regulator driver. Set API
always updates force value, but applies it only in open loop mode, or
disabled mode. In closed loop mode bypass request is ignored to avoid
interference with automatic voltage control. Get API returns force
value back if it is applied, and returns monitored output, otherwise.
Hence, get value matches real CL-DVFS output in any mode.

The new APIs are not exposed to dfll bypass driver if DFLL supply is
connected by I2C interface, since h/w provides access to the regulator
I2C bus via one of tegra I2C controllers.

Bug 1310396

Change-Id: I90b433cc03cb739cc7b9c89d2d3ef8dbb00cb447
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257343
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: power: Add DFLL bypass regulator driver
Alex Frid [Tue, 30 Jul 2013 01:12:26 +0000]
ARM: tegra: power: Add DFLL bypass regulator driver

In addition to its main function - automatic voltage scaling, Tegra
DFLL can be used in bypass mode to control voltage by s/w. This
commit introduced a simple linear voltage regulator as a wrapper
around DFLL bypass interfaces.

Bug 1310396

Change-Id: I18430b8125de6b6e84d7eee91f2f887d68d96fb5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/257342
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoarm: mm: cpa: fix compilation errors when nvmap is disabled
Krishna Reddy [Mon, 5 Aug 2013 23:24:51 +0000]
arm: mm: cpa: fix compilation errors when nvmap is disabled

avoid dependency on nvmap defined variables.
set inner cache size threshold correctly between A9 and A15.
fix compilation issue during non-SMP build.
Bug 134220

Change-Id: I65eb0c3a8c11a03b4bf49e7903f91bb74d27a20f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/258385
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoarm: tegra: make ahb gizmo writel irq safe
Nitin Kumbhar [Thu, 8 Aug 2013 17:31:32 +0000]
arm: tegra: make ahb gizmo writel irq safe

Bug 1315068

Change-Id: I59566817601a102f95aba5415fb4a7d9ce138bab
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/259701
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: host: Disable gk20a power gating
Terje Bergstrom [Thu, 8 Aug 2013 08:05:25 +0000]
video: tegra: host: Disable gk20a power gating

Power gating causes losing CBC state. Disable it by extending
timeout.

Bug 1331831

Change-Id: I49757cee751e8d17c514a4ad5c9c024679608b10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/259548
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: disable tskin throttling for board with no skin diode
Diwakar Tundlam [Thu, 8 Aug 2013 00:28:12 +0000]
arm: tegra: disable tskin throttling for board with no skin diode

Disable by raising throttle limit to 200C. Those with skin diode can
manually set it to 50C as needed.

Bug 1345131
Bug 1315460

Change-Id: I1eb14d1f473825c10be3d05e63aedc5d40079e17
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/259385

5 years agovideo: tegra: host: fix gk20a comptag address error
Ken Adams [Wed, 7 Aug 2013 20:00:32 +0000]
video: tegra: host: fix gk20a comptag address error

We were trying to perform a round-up but botched
the comparison.

bug 1331831

Change-Id: Id5426fd97002fea186c011afae96fdceaf14b944
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/259306
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agovideo: tegra: host: Report LTC interrupts
Terje Bergstrom [Mon, 5 Aug 2013 09:58:15 +0000]
video: tegra: host: Report LTC interrupts

Add reporting and clearing of LTC interrupts. This prevents an
interrupt storm if we have an L2 related error.

Change-Id: I24dd596143b69fbab85caca4cdc653f80222e0ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/258151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: gk20a: disable ELCG.
Kevin Huang [Tue, 6 Aug 2013 23:46:36 +0000]
video: tegra: gk20a: disable ELCG.

Disable it for stability.

Change-Id: I7abfdb19cddfc5ccaae5852389b2e48cc5e566ea
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/258891
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agodrivers: tegra: gk20a: disable slcg
Prashant Malani [Tue, 6 Aug 2013 21:02:30 +0000]
drivers: tegra: gk20a: disable slcg

Disable slcg graphics and perf load gating.

Change-Id: I5dc4a8869ef14c412469fd49ae5dd4d551fa841e
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/258835
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agodrivers: tegra: gk20a: Disable blcg
Prashant Malani [Tue, 6 Aug 2013 21:00:47 +0000]
drivers: tegra: gk20a: Disable blcg

Change-Id: Ie5c38d16ca2f00cd45ee64844030d4814b9ab0af
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/258834
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: dsi: Fix dsi resume
Animesh Kishore [Mon, 5 Aug 2013 10:44:29 +0000]
video: tegra: dsi: Fix dsi resume

- Support lp-00/lp-11 before panel wakeup.
- Platform flag to enable/disable ulpm.

Bug 1341152

Change-Id: I99b77bd4fd707de1a9a2f452be93610b971f5844
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/258165
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: dalmore: Fix sharp 25x16 power on/off
Animesh Kishore [Mon, 5 Aug 2013 10:48:53 +0000]
arm: tegra: dalmore: Fix sharp 25x16 power on/off

- lp-00 before wake-up
- disable ulpm.
- add stabilization delays.

Bug 1341152

Change-Id: I8120aba4bd305480a6e1bdaa23c48ac82091ea55
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/258166
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agodma: Add GCOV_PROFILE
Konsta Holtta [Mon, 5 Aug 2013 10:49:54 +0000]
dma: Add GCOV_PROFILE

Include dma in GCOV profiling when enabled by defconfig.

Change-Id: Ia3a55f0d985370c3d4c740039318f9bb5e74b32b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/258178
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra12: actmon: Fix EMC count_weight for T124
Vikas Jain [Wed, 17 Jul 2013 10:53:49 +0000]
ARM: tegra12: actmon: Fix EMC count_weight for T124

T124 will burn 4 emcclks for a request of
any size up to the max request size of 64B,
so for T124 emc-clock-per-atom is 4.

Bug 1326781

Change-Id: I1646cb41f52cb6b879e44998ed49a17d659e8533
Signed-off-by: Vikas Jain <vjain@nvidia.com>
Reviewed-on: http://git-master/r/258073
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dc: Get rid of the 'Unsupported dithering' message
Chao Xu [Fri, 2 Aug 2013 17:51:34 +0000]
video: tegra: dc: Get rid of the 'Unsupported dithering' message

Most panel files do not provide the default dithering mode, which causes
error message of 'unsupported dithering mode'. Set the mode to disable
if not set.

Change-Id: I5daeb6e2d8079f0675e5502e135e568a4c473c40
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/257620
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoinput: touchscreen: raydium v60.2 touch driver
Xiaohui Tao [Fri, 2 Aug 2013 17:09:32 +0000]
input: touchscreen: raydium v60.2 touch driver

raydium code drop

[1] Add additional info for regulator event msg

[2] Add RM_PLATFORM_A010 for Ardbeg AVC sensor

[3] Fix no touch function in Pluto platform with RM31081 from idle mode

[4] Refine Pismo touch direction

[5] Fix idle mode problem with Ardbeg AVC sensor

Bug 1330952

Change-Id: Ib282bec3f07a16eb657314ee5127824f02a89d02
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/257604
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agomisc: nct1008: adjust reported temp via offset table
Diwakar Tundlam [Thu, 25 Jul 2013 01:33:46 +0000]
misc: nct1008: adjust reported temp via offset table

Add support to specify a table of temperature dependent offsets
that will be added to the measured temperature before reporting
it to the thermal zone. Actual temperature is still reported in
'temperature'.  We only adjust the temperature reported to
thermal zone via the xxx_get_temp() API.

This is done only for external sensors as requested.

Bug 1330895

Change-Id: I419aa62b2a69f9a96b1fab401fc53e791386b300
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/257044

5 years agomisc: nct1008: move debug regs to I2C driver dir
Diwakar Tundlam [Wed, 24 Jul 2013 01:16:19 +0000]
misc: nct1008: move debug regs to I2C driver dir

With multiple NCT devices support, we cannot have a single
debugfs node to display device registers. Remove /d/nctxxx and
move it to the I2C device driver directory which exists
separately per device.

Bug 1330895

Change-Id: I92feb281a3eaa599d85ad052e4d2c54609fa42e3
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/257043
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: dc: Update LVDS power up sequence
Chao Xu [Wed, 31 Jul 2013 00:35:26 +0000]
video: tegra: dc: Update LVDS power up sequence

Change-Id: I03f5fa4097b9c3a1979d440b78e7bdcaef505c60
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/257030
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: ardbeg: Change to use the right platform ID
Xiaohui Tao [Thu, 1 Aug 2013 17:03:39 +0000]
ARM: tegra: ardbeg: Change to use the right platform ID

Bug 1330952

Change-Id: I5c177ab7b6e41923a793e95150c35675c0deb89e
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/256923
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: dalmore: Add sharp 25x16 suspend seq
Animesh Kishore [Thu, 1 Aug 2013 12:59:38 +0000]
arm: tegra: dalmore: Add sharp 25x16 suspend seq

Bug 1341152

Change-Id: I8d98bed73503e2257f0025c2044077b6d6d1ef45
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/256836
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dsi: Fix dsi suspend sequence
Animesh Kishore [Thu, 1 Aug 2013 12:44:43 +0000]
video: tegra: dsi: Fix dsi suspend sequence

- explicitly disable backlight before suspend
- power gate pad after panel power gate

Bug 1341152

Change-Id: Ibf664efc3db371d09ac6f380706528b139eafce5
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/256835
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: board:disable the unaligned dma buffer
Rakesh Bodla [Tue, 30 Jul 2013 08:01:40 +0000]
ARM: tegra: board:disable the unaligned dma buffer

Disable usb h/w alignment fix.

Bug 1289107

Change-Id: Ice6c9b6d561bea3ef629e12fe9c5773512a9df04
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/255419
(cherry picked from commit 949ac7681ee99dae5ad75fba6903ece3690700a1)
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/256763
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: ardbeg board file change for cpu edp init
Xue Dong [Tue, 23 Jul 2013 00:03:11 +0000]
arm: tegra: ardbeg board file change for cpu edp init

bug 1330937

Change-Id: I70216a8cb8007912670b7a403eb1736ad5ee4b9e
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/256487
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: enable CPU EDP
Xue Dong [Tue, 23 Jul 2013 00:01:00 +0000]
arm: tegra: enable CPU EDP

bug 1330937

Change-Id: I20a15c8d17d734c0cf82ba038534a6726380285a
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/256486
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agosecurity: tlk_driver: result_origin consistency
Aaron Gamble [Fri, 28 Jun 2013 20:17:14 +0000]
security: tlk_driver: result_origin consistency

For the sake of consistency with other projects, change:
OTE_ERROR_ORIGIN_*
return_origin
error_origin

to match result_origin

Change-Id: I571c81a387ab35ed05cc3002371bc5d6ae606178
Signed-off-by: Aaron Gamble <jgamble@nvidia.com>
Reviewed-on: http://git-master/r/243549
(cherry picked from commit 1a1e6ac1e74a2594662f4601f7a37baf4d4b78bd)
Reviewed-on: http://git-master/r/256381
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: James Zhao <jamesz@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

5 years agovideo:tegra: enable cyclestats by default
Kirill Artamonov [Wed, 31 Jul 2013 11:56:35 +0000]
video:tegra: enable cyclestats by default

This feature is also going to be used in perf analysing tools
which shouldn't require special build.

Fix build errors happening in cyclestats code.

bug 1154464
bug 1324403

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Idc36b7af00a6dd6a928712113f530c9b1c998c0a
Reviewed-on: http://git-master/r/256316
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agomisc: bluedroid_pm: add delay for setting gpio
Om Prakash Singh [Mon, 22 Jul 2013 16:27:10 +0000]
misc: bluedroid_pm: add delay for setting gpio

Bug 1329474
Bug 1275395

Change-Id: I6350cef509a496ba4165f55aa3ad29fd46190367
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: http://git-master/r/252001
(cherry picked from commit db753932750b33e7c29ff4619928cf98c8a44159)
Reviewed-on: http://git-master/r/256293
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomisc: bluedroid_pm: Set minimum CPU frequency
Shobek Sam Attupurath [Tue, 2 Jul 2013 10:25:51 +0000]
misc: bluedroid_pm: Set minimum CPU frequency

For A2DP, if current frequency is lower than the one required
glitches may be heard.
Set minimum frequency 204MHz during BT activities.

Bug 1302427

Change-Id: Id29dc004bdd5cd18af9298742663aa073ed19d4c
Signed-off-by: Shobek Sam Attupurath <sattupurath@nvidia.com>
Reviewed-on: http://git-master/r/244298
(cherry picked from commit 912b388337c2b6703ddaabd95250afac95fee303)
Reviewed-on: http://git-master/r/256292
GVS: Gerrit_Virtual_Submit
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agotty: serial8250: Add interrupt handler for tegra
Pradeep Goudagunta [Wed, 31 Jul 2013 09:16:44 +0000]
tty: serial8250: Add interrupt handler for tegra

Tegra UART IIR sometimes not consistent with its IRQ signal
which will generate continous spurious interrupts, inorder to
recover from this, generate legal modem interrupt and handle it.
So add a seperate interrupt handler for tegra.

Bug 1229695
Bug 1339412

Change-Id: I1e8145fea015ece24150d3ef8a640695576b5826
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/256273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: ardbeg: Add flash strobe to IMX135
Pablo Ceballos [Fri, 26 Jul 2013 01:48:18 +0000]
arm: tegra: ardbeg: Add flash strobe to IMX135

Bug 1330958

Change-Id: Ieda1d86994b2605808250e9b7545e2bc5e575209
Signed-off-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-on: http://git-master/r/255747
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agovideo: tegra: host: enable power gate for msenc on t124
Mayuresh Kulkarni [Tue, 30 Jul 2013 15:10:02 +0000]
video: tegra: host: enable power gate for msenc on t124

Change-Id: Ic490357b05cb0c6b74fef4f02852a1328787fb7c
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/255641
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agovideo: tegra: host: Use actmon clock on T124
Arto Merilainen [Tue, 30 Jul 2013 14:35:17 +0000]
video: tegra: host: Use actmon clock on T124

This patch modifies actmon code to use correct clock on T124. In
addition, this patch also modifies sample period calculation to work
with kHz clocks.

Bug 1328068

Change-Id: I969fcda899974ae10db4f220b501a7bae90a7d5d
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/255635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: correct suspend path for camera
Sri Krishna chowdary [Fri, 19 Jul 2013 12:37:03 +0000]
video: tegra: host: correct suspend path for camera

return error if tegra_camera_suspend fails

Bug 1289898

Change-Id: I9e9c4abca451693e5a67047aa812d6a979b77445
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/251339
(cherry picked from commit 23107aacafd598b8c41f21c289cb03577d31f2d7)
Reviewed-on: http://git-master/r/254904
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agovideo: tegra: host: Use actmon_readl/writel
Terje Bergstrom [Fri, 26 Jul 2013 11:10:34 +0000]
video: tegra: host: Use actmon_readl/writel

Use actmon_readl() and actmon_writel() to access actmon registers.
This allows tracing all register writes.

Change-Id: Iafedb2a6208b68e9afa8c2b61e1f23ec7f7873bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/254244
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra12: Add actmon clock to host1x
Terje Bergstrom [Fri, 26 Jul 2013 07:59:13 +0000]
ARM: tegra12: Add actmon clock to host1x

Add actmon clock for host1x driver.

Bug 1328068

Change-Id: I6174a8c1beb237a100ae1070afadfdbd68ffacd0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/254074
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoARM: tegra: Add CHIMEI LVDS panel support
Chao Xu [Wed, 24 Jul 2013 00:25:08 +0000]
ARM: tegra: Add CHIMEI LVDS panel support

Bug 1331024

Change-Id: I6e112aadb1bd8c565e940af54890623f7bcfb02b
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/252988
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agotegra: host: vi: Add ioctl to VI driver
Pablo Ceballos [Wed, 10 Jul 2013 19:08:42 +0000]
tegra: host: vi: Add ioctl to VI driver

Adds an ioctl to the vi driver ctrl node. It is used for setting the
CSI clock source.

Bug 1315446

Change-Id: Ic12dc8b55a390778aba51e9b604ad2fb556ce508
Signed-off-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-on: http://git-master/r/252196
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chien-Yu Chen <chichen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: Check force update in fb pan display
Jong Kim [Thu, 1 Aug 2013 23:49:24 +0000]
video: tegra: Check force update in fb pan display

Now we'll not update the dc if the x & y offset are not changed
in fb pan display.

But this doesn't work for console switch(e.g: switch from a X server
to a fbcon). The x/y offset will not change but we still need to
update the dc to show the framebuffer console.

So add one more check here: if the update is forced, we'll keep
going to update the dc.

bug 1259633

Change-Id: Ibbb1216151ba34729e438ada62f90eba38758088
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/234082
(cherry picked from commit 9caec7df0ec01890b0d9186456867f8dc099d6ed)
Reviewed-on: http://git-master/r/251729
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agoarm: tegra: add tskin throttling table with PID governor
Diwakar Tundlam [Thu, 25 Jul 2013 21:33:22 +0000]
arm: tegra: add tskin throttling table with PID governor

Bug 1315460

Change-Id: I239830dde83ac37dbaef948619f060a69d920eee
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/251107
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>

5 years agoarm: tegra: enable nct72 device for skin temp sensing
Diwakar Tundlam [Sat, 13 Jul 2013 01:33:57 +0000]
arm: tegra: enable nct72 device for skin temp sensing

Enable discovery of NCT72 connected to skin Diode.

Bug 1315460

Change-Id: Ied846d55d17e4466b781a73ac6c4fd4d365ce02a
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/250908
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>

5 years agomedia: video: tegra: as364x: add edp client
Charlie Huang [Tue, 18 Jun 2013 18:44:20 +0000]
media: video: tegra: as364x: add edp client

enable edp support on as364x.

ported from http://git-master/r/#change,236030, which was submitted
already but cannot be simply cherry picked due to other differences.

bug 1299134

Change-Id: Iee54b554ae2b6cffef2cab31f23b6b5ffa2293d4
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/239840
(cherry picked from commit fa919f0b3405eafde052483faa82ec66ef8e93da)
Reviewed-on: http://git-master/r/250881
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agomedia: video: tegra: max flash/torch current
Charlie Huang [Mon, 8 Jul 2013 22:29:27 +0000]
media: video: tegra: max flash/torch current

the peak flash/torch current can be set from the board file.
devices: as364x, lm3565, max77387, max77665.

bug 1322024

Change-Id: I3121e39e07c1ff9a7e7dc76ff76f41df84868983
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/246319
(cherry picked from commit d2520eb46fea2885271aabda1ecb0ff547042b82)
Reviewed-on: http://git-master/r/250874
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agomedia: tegra_v4l2: add i2c_camera_ctrl struct
Bryan Wu [Thu, 30 May 2013 22:35:59 +0000]
media: tegra_v4l2: add i2c_camera_ctrl struct

I2C devices should be dynamically created/removed by VI driver. This
is required by making VI/CSI and V4L2 drivers as modules.

Bug 1240806

Change-Id: Ia0218ecaab18cc3df27047663177291ccdd2cc15
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246264
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: export txx_vi_info for VI driver
Bryan Wu [Thu, 28 Feb 2013 02:17:37 +0000]
video: tegra: host: export txx_vi_info for VI driver

Export these nvhost_device_info for VI driver modulization and let
board file to access these data structs via nvhost.h header file.

Bug 1240806

Change-Id: Ifae11b0cebf56385f2dc2879fd220e1ceb4079f3
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246263
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

5 years agodevfreq: Add stub functions to governor.h
Arto Merilainen [Tue, 2 Jul 2013 11:21:56 +0000]
devfreq: Add stub functions to governor.h

Due to the kernel update we lost devfreq stub functions from
governor.h which effectively prevents compilation of the kernel
when devfreq is disabled.

This patch adds stub functions to governor.h to allow the kernel
to compile when there are devfreq users and devfreq is disabled.

Change-Id: Ica543ef05ffeb0ba0258363087f9427d871f8e1f
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/244668
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Regenerated gk20a headers
Terje Bergstrom [Mon, 5 Aug 2013 10:08:02 +0000]
video: tegra: host: Regenerated gk20a headers

Regenerating gk20a headers causes the ordering to change a bit. In
this patch there's only reordering changes and no functional
differences.

Change-Id: I4b40a87a8798522baf3f59ccacf4527e7bbef6a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/258150
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agovideo: tegra: host: Update LTC reg definition
Terje Bergstrom [Mon, 5 Aug 2013 09:55:59 +0000]
video: tegra: host: Update LTC reg definition

Two definitions are off between the hardware header and the generated
header. This synchronizes the value.

Change-Id: I2b6634f49e91a81b5fd4d8891299aacde52da8c2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/258149
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>

5 years agoARM: tegra: edp: remove unused code
Deepak Nibade [Mon, 5 Aug 2013 09:28:12 +0000]
ARM: tegra: edp: remove unused code

- fix Coverity issue
  Coverity id : 23764

Bug 1329327

Change-Id: I8adc5c72dab7e0e55d6173fde332ade0d7da710d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/258132
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: Tegra: Add residency stats for MC clock stop
Matthew Du [Sat, 3 Aug 2013 01:35:38 +0000]
ARM: Tegra: Add residency stats for MC clock stop

Added MC clock stop print to residency stats

Change-Id: Iec78cab1fbe7a66ea0ae674bbcf039e60af7d889
Signed-off-by: Matthew Du <matthewd@nvidia.com>
Reviewed-on: http://git-master/r/257800
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: tegra14: BGBIAS cells cannot be in DPD when entering LP0
Alex Waterman [Wed, 31 Jul 2013 22:13:22 +0000]
ARM: tegra14: BGBIAS cells cannot be in DPD when entering LP0

For low frequencies that use Schmitt mode triggering in the EMC the
BGBIAS cells are not needed and can be turned off. However, if the
system is at a low frequency and goes into LP0 (i.e when the BBC is
in airplane mode) the bootrom will fail to read memory on wake up.
This occurs because the bootrom boots at the max EMC frequency (787
or 921 MHz) which requires the BGBIAS cells to be alive.

To fix the problem the BGBIAS cells are taken out of DPD when the
system goes into LP0.

Bug 1332120

Reviewed-on: http://git-master/r/256523
(cherry picked from commit e59834d3649eb0e022d0d9cadc2a172c5b43e519)
Change-Id: Iab8082f946c6094b65b1fd17fb162ff7553436fb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257648
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: emc: Remove fake clock switch
Alex Waterman [Fri, 12 Jul 2013 00:50:54 +0000]
ARM: tegra14: emc: Remove fake clock switch

This support is no longer needed.

Reviewed-on: http://git-master/r/248130
(cherry picked from commit d6710dafcf24f0b3c729c48703df1560ee1d6d5a)
Change-Id: I4d7201a963fcd7cc9d168b051793b130272f6efa
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257644
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: config: tegra12: enable CONFIG_INPUT_CFBOOST
Yogish Kulkarni [Fri, 2 Aug 2013 13:09:38 +0000]
ARM: config: tegra12: enable CONFIG_INPUT_CFBOOST

Enable input event CPU frequency booster.

Bug 1229219

Change-Id: I1c424221dc311eeb43870b4c48ab3be8b0619e67
Signed-off-by: Yogish Kulkarni <yogishk@nvidia.com>
Reviewed-on: http://git-master/r/257560
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agobcmdhd: Add support for channel 165
bibhayr [Fri, 21 Jun 2013 07:40:36 +0000]
bcmdhd: Add support for channel 165

channel 165 is not the side band of 40MHz 5G channel

Bug 1298751

Change-Id: I9f29d11d30b1394ab097c82f97b177acd98149a2
Signed-off-by: bibhayr <bibhayr@nvidia.com>
Reviewed-on: http://git-master/r/240198
(cherry picked from commit 95e0bfd5949e8bcfb2513a06bd0467d94fe84a92)
Reviewed-on: http://git-master/r/257438
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: config PWRGOOD_MASK in SOC_THERM
Sivaram Nair [Wed, 17 Jul 2013 15:24:57 +0000]
ARM: tegra: config PWRGOOD_MASK in SOC_THERM

In T148, battery OC is signalled by max77660 though PG_OC. But this same
pin is also used to signal CPU_PWRGOOD.

The PWRGOOD_MASK describes the behavior of the OC alarm wrt the
CPU_PWRGOOD signal. If SW sets this bit to 1, it means that OC alarm
will not be asserted until CPU_PWRGOOD is also asserted.

This patch lets the throttle vector to specify the power-good mask.

Bug 1313669

Change-Id: If12d868de181ab6f0581686763ddcb748819301c
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/250308
(cherry picked from commit 47096226a35a9f64608654c6a82a8b7bc52dd15c)
Reviewed-on: http://git-master/r/256826
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agopower: max77660: add BAT to SYS OC alert
Sivaram Nair [Wed, 17 Jul 2013 15:20:20 +0000]
power: max77660: add BAT to SYS OC alert

Configure max77660 to generate OC alert signal to SOC via PG_OC

Bug 1293751

Change-Id: Ic434b0f4974aa69c5115fe6246280b8551336e20
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/250307
(cherry picked from commit 30737eb73317385e9b4df34b4bdbe0383d87907f)
Reviewed-on: http://git-master/r/256825
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: tegra: adding CPU EDP support for T124
Xue Dong [Mon, 22 Jul 2013 23:57:48 +0000]
arm: tegra: adding CPU EDP support for T124

bug 1330937

Change-Id: I70a6ba631a1035a2648a2e8de8ebdbbb07b22865
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/256483
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm:tegra:dvfs: API to extract GPU DVFS info
Mihir Thakkar [Wed, 31 Jul 2013 17:02:54 +0000]
arm:tegra:dvfs: API to extract GPU DVFS info

This change will extract the gpu dvfs table. We can access it from
adb shell cat /d/clock/gpu_dvfs

Bug 1311067

Change-Id: If305b0d1b24f0929ca66c85c635e9d5d93048084
Signed-off-by: Mihir Thakkar <mthakkar@nvidia.com>
Reviewed-on: http://git-master/r/256402
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: host: remove epp clock from isp
Daehyoung Ko [Wed, 24 Jul 2013 23:34:46 +0000]
video: tegra: host: remove epp clock from isp

to remove epp from the isp channel's clock list
in order to get rid of conflict for epp clock
between 2d and isp

bug 1331777
bug 1322046

Change-Id: I5625aae7b693b00668d97839c0ae5cf21bf8f460
Signed-off-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-on: http://git-master/r/253117
(cherry picked from commit 3a32a3734838030fca830b4da42cbde1210b1114)
Reviewed-on: http://git-master/r/256320
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agousb: host: tegra: reduce delay in driver remove
Rohith Seelaboyina [Thu, 25 Jul 2013 11:52:56 +0000]
usb: host: tegra: reduce delay in driver remove

Following are taken care:
1. Add check conditions before updating the pm_qos nodes
2. Reduce delay in driver remove path to sync
ehci_bus_resume, ehci_bus_suspend, ehci_remove

Bug 1316354
Bug 1331078

Change-Id: I51e251474a9def65286e7a6f8099ad9cdc40d0ea
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/253405
(cherry picked from commit ce7b1404c080c71580aa0d6b0f944c398c36d7b4)
Reviewed-on: http://git-master/r/256295
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: fix Coverity issues
Deepak Nibade [Wed, 31 Jul 2013 09:45:34 +0000]
video: tegra: host: fix Coverity issues

- fix dereference of NULL return value. Add a NULL check
  Coverity id : 23335
- fix logically dead code
  handle function return values and use them for error checking
  Coverity id : 23733
- fix write to pointer after free
  free the pointer only after all operations are performed on it
  Coverity id : 23719
- fix dereference before NULL check
  check for NULL before dereferencing the variable
  Coverity id : 22918
- fix out of bounds read
  first check if value of variable 'i' is within range and
  then only use it as array index
  Coverity id : 23662

Bug 1329327

Change-Id: I70c9d6b00672211c7aaecc023ff2229efb52517f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/256283
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: host: Attach comptags to nvmap allocation
Lauri Peltonen [Sun, 21 Jul 2013 20:54:16 +0000]
video: tegra: host: Attach comptags to nvmap allocation

Attach comptags to the nvhost private part of the nvmap allocation.
This is needed for sharing compressed buffers across address spaces.

When mapping a buffer to gk20a, we check if comptags have already
been attached to the allocation. If not, we request them to be
allocated.

Bug 1290753
Bug 1174439

Change-Id: I8e1bc6cfef1da66134227a9a55c38bb21c6d9e99
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/255015
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: gk20a: Use nvhost_memmgr_pin
Lauri Peltonen [Tue, 9 Jul 2013 08:29:00 +0000]
video: tegra: host: gk20a: Use nvhost_memmgr_pin

Using the nvhost_memmgr_pin function will take care of smmu mapping
automatically. Those smmu mappings are also automatically released
lazily when the allocation goes away.

Bug 1174439
Bug 1339218

Change-Id: Ia95659efb05e0789192d891244f4edf41bb9dcfe
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/255014
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Support multiple asids in nvhost pin
Lauri Peltonen [Fri, 19 Jul 2013 22:40:26 +0000]
video: tegra: host: Support multiple asids in nvhost pin

Store mapping information per ASID.

Bug 1174439
Bug 1309863

Change-Id: I2f80e40567ed2f0bb13c92ecaf1e8086d4cfb203
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/255013
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: Support querying smmu asid from device
Lauri Peltonen [Fri, 19 Jul 2013 22:02:13 +0000]
ARM: tegra: Support querying smmu asid from device

Add tegra_smmu_get_asid(struct device *) to allow drivers to query
which smmu asid a particular device is using. This is useful if
the drivers want to cache mappings for multiple devices that might
not use the same asid.

Bug 1174439

Change-Id: Iaa5d0d1d773d9d5bb72282d67d640e5c99000daa
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/255012
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoarm: tegra: laguna: set suspend mode to lp0
Kerwin Wan [Thu, 1 Aug 2013 08:10:49 +0000]
arm: tegra: laguna: set suspend mode to lp0

Change-Id: Ie71a0195c11b9427b15c50175763a4cdd9e46be1
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/256731
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: dp: Don't disable dp which is already disabled
Kerwin Wan [Thu, 1 Aug 2013 08:08:55 +0000]
video: tegra: dp: Don't disable dp which is already disabled

Bug 1341098

Change-Id: I4736950ed2111493e42a4cc64041cf995134cd85
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/256730
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Check clk_m divider
Kaz Fukuoka [Tue, 18 Jun 2013 01:11:00 +0000]
ARM: tegra12: clock: Check clk_m divider

Ported from http://git-master/r/194426 (change for Tegra14)

Change-Id: I71217b7428efe4418afd00832b52cf98153a17e2
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256578
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Fix PMC_PLLM_WB0_OVERRIDE
Kaz Fukuoka [Fri, 14 Jun 2013 00:59:09 +0000]
ARM: tegra12: clock: Fix PMC_PLLM_WB0_OVERRIDE

In case if bootloader doesn't initilize PLLM, the reset default value
of APBDEV_PMC_PLLM_WB0_OVERRIDE_FREQ_0 is left uninitialized.
Because this reset default value doesn't make sense, it has to be
initialized by kernel.

Ported from http://git-master/r/204827 (change for Tegra14)

Change-Id: I47aa99da205bb6fb7024ae5e83546bca379e609e
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256576
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Relax CPU rate increase warning check
Kaz Fukuoka [Fri, 14 Jun 2013 00:34:45 +0000]
ARM: tegra12: clock: Relax CPU rate increase warning check

Ported from http://git-master/r/203621 (change for Tegra14)

Change-Id: I4de304a52f2eefe20feb046570f8a1d4af7154f5
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256575
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Force out-of-table shared bus max limit
Kaz Fukuoka [Tue, 11 Jun 2013 22:36:05 +0000]
ARM: tegra12: clock: Force out-of-table shared bus max limit

Ported from http://git-master/r/199170 (change for Tegra14)

Change-Id: I0fdf2d8dc70ce24e7906af6c2ee6b51f54699966
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256574
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Update shared bus operations
Kaz Fukuoka [Tue, 11 Jun 2013 21:45:00 +0000]
ARM: tegra12: clock: Update shared bus operations

Ported from http://git-master/r/195661 (change for Tegra14)

Change-Id: If23e2a728e3e3a17ae0ad87e5e6b77dfc7fbf902
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256573
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Add duplicate clock for clk_m
Kaz Fukuoka [Fri, 7 Jun 2013 23:19:36 +0000]
ARM: tegra12: clock: Add duplicate clock for clk_m

Create a duplicate for clk_m with connection id "apb_pclk". This is
to be used by components, such as coresight ETB and PTM, which
are accessed through APB interface, thus requires APB clock. Since
APB clock should never be turned off, connect "apb_pclk" to "clk_m"
instead, because "clk_m" operators don't do anything when being
enabled or disabled.

Ported from http://git-master/r/190227 (change for Tegra11)

Change-Id: I2dcfa1c2c51616e5e4e798a10e2b0587b2e1fec8
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256571
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra: clock: Rename CONFIG_TEGRA_CLOCK_DEBUG_FUNC
Kaz Fukuoka [Wed, 31 Jul 2013 23:53:42 +0000]
ARM: tegra: clock: Rename CONFIG_TEGRA_CLOCK_DEBUG_FUNC

Rename CONFIG_TEGRA_CLOCK_DEBUG_MODS to more generic name
CONFIG_TEGRA_CLOCK_DEBUG_FUNC.

Change-Id: I6c48aef5842b400c16ba28e9216b68efd5b3d84f
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256549
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra12: clock: Fix build warning
Kaz Fukuoka [Wed, 31 Jul 2013 23:09:51 +0000]
ARM: tegra12: clock: Fix build warning

Explicitly add "UL" for large unsigned long constant.

Change-Id: I460135036e990b3811f86e5f8cfd4ef624b7fe31
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256536
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: gk20a: Measure GPCCLK rate
Kaz Fukuoka [Wed, 31 Jul 2013 22:34:39 +0000]
video: tegra: gk20a: Measure GPCCLK rate

Add /d/gk20a/monitor to measure GPCCLK rate.

Change-Id: If8f72c5ca56999c6db9c5538f2fefb4dc38e85fa
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/256521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dtv: memory allocation size error
Jun Su [Fri, 28 Jun 2013 12:12:15 +0000]
video: tegra: dtv: memory allocation size error

when we allocate memory for stream buffer, the size should
by sizeof(dtv_buffer), not size(dtv_buffer *)

Bug 1314904
Bug 1061456
Bug 1258577

Change-Id: I81a16ead5f232c28ae572d9bffe75ca4ac6aa45e
(cherry picked from commit e0bfe6f1b5202b5b61b69681a05513dc6dd3a776)
(cherry picked from commit f59922ee826ffbb708c5250ab2c65bd73cd26fdd)
Signed-off-by: Jun Su <juns@nvidia.com>
Reviewed-on: http://git-master/r/#change,243434
Reviewed-on: http://git-master/r/256197
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dtv: Add runtime profile switch
Adam Jiang [Tue, 14 May 2013 09:14:24 +0000]
video: tegra: dtv: Add runtime profile switch

Typical application requires the capability of switching between
various profiles including different buffer sizes, counts and minimum
CPU frequencies on DTV device. This patch adds new ioctl commands to
support this.

Bug 1061456
Bug 1258577

Change-Id: Ia3e7ab8d4c05cce4bd1fe10b28f075493a512748
(cherry picked from commit 9e66b3e419ae6bd24cb3b58f4a5f676efd09e111)
(cherry picked from commit fe859e9af336712786d5251f027dafddebad3f36)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/#change,237446
Reviewed-on: http://git-master/r/244488
Reviewed-on: http://git-master/r/256196
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>