5 years agoarm: tegra: la: la and ptsa updates for t14x.
Krishna Reddy [Tue, 5 Feb 2013 17:50:35 +0000]
arm: tegra: la: la and ptsa updates for t14x.

Change-Id: I31ede6f4f3e98b26f1ac1d96068cb6c0c6d0ad15
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/197530
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: T14x: Use wfi for CPU power gating
Seshendra Gadagottu [Wed, 9 Jan 2013 20:39:51 +0000]
ARM: tegra: T14x: Use wfi for CPU power gating

For T14x, use wfi instead of wfe for CPU power gating
and CPU hot un-plug.

Change-Id: Ib55832112d8eceb57f5a3035c9fbd5fb76d5359c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198587
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: clock: Initialize soc_therm clock
Kaz Fukuoka [Thu, 7 Feb 2013 01:49:22 +0000]
ARM: tegra14: clock: Initialize soc_therm clock

Initialize soc_therm clock in the same way as Tegra11.

Change-Id: Icca77970c22fac5c7b7222f435d65e20d7cdb972
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/198214
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoASoC: Tegra: Add voice call support for ceres
Ravindra Lokhande [Mon, 28 Jan 2013 16:52:30 +0000]
ASoC: Tegra: Add voice call support for ceres

Change-Id: I00739695e81ed076e963e361288e1462b49d0cde
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/194737
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stefano Sarghini <ssarghini@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agommc: core: Set HS timing if host support HS mode
rrajk [Thu, 7 Feb 2013 19:33:32 +0000]
mmc: core: Set HS timing if host support HS mode

Set high spped mode and HS timing for the card and host only when
both card and host supports high speed mode.

Change-Id: Ia9459383e9a6c6e5b3dfc1a67663534ae1ef7930
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/198462
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: tegra: clocks: Correct the se_dev name passed
Shravani Dingari [Thu, 7 Feb 2013 14:40:15 +0000]
arm: tegra: clocks: Correct the se_dev name passed

Change-Id: I87f4c99afeb8c8bdaa3199e4bdec9ac94374db85
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/198402
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomisc: tegra-cryptodev: Extend DRBG support to t148
Shravani Dingari [Thu, 7 Feb 2013 15:54:49 +0000]
misc: tegra-cryptodev: Extend DRBG support to t148

Change-Id: If8f6a47d961cdba36c8f1275a06bc6a2bf759c54
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/198422
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: ceres: change csi/cilcd clock
Jihoon Bang [Fri, 8 Feb 2013 00:06:37 +0000]
ARM: tegra: ceres: change csi/cilcd clock

Remove cilcd clock in T148.
Change max clock for csi to 102MHz from 100MHz.

Bug 1180011

Change-Id: Id12ec0039477c6cf1f4cedd34b54382e1578a39b
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198572
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agomedia: video: tegra_camera: remove cilcd
Jihoon Bang [Fri, 8 Feb 2013 00:05:10 +0000]
media: video: tegra_camera: remove cilcd

Remove cilcd clock.
T148 doesn't need cilcd.

Bug 1180011

Change-Id: I25815170538671a0ab89577e61422c70c89be6e9
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198571
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: max77660: add set sim config
shawn joo [Thu, 7 Feb 2013 09:04:06 +0000]
regulator: max77660: add set sim config

initialize sim1, sim2 config.
BAT_REMOVED is ignored and it should be enabled if requried.
if BAT_REMOVED is enabled, e1680' sim does not work correctly.
SIM detect debounce is calculated with count 16.

Bug 1177376

Change-Id: I118f711abc073044f976aac9f2c493d8cb30fae3
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/198304
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14x: kconfig: Remove relic ARM_SMP_TWD
Seshendra Gadagottu [Thu, 7 Feb 2013 22:01:11 +0000]
ARM:  tegra14x: kconfig: Remove relic ARM_SMP_TWD

Change-Id: I4aff4b9a1e96f8d0c59a34b4ddc1954891df6733
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198522
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: cldvfs: Update tune parameters
Seshendra Gadagottu [Thu, 7 Feb 2013 21:58:23 +0000]
ARM: tegra14: cldvfs: Update tune parameters

Updated new safe tune0 parameter for cldvfs

Change-Id: Ia07974d6d56d07119718709260e33ec7dd63710f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoARM: tegra14: clock: Fix max rate
Hoang Pham [Thu, 7 Feb 2013 20:31:01 +0000]
ARM: tegra14: clock: Fix max rate

Fix max rate for clocks: owr, clk_out_1, clk_out_3 and clk72mhz

Change-Id: I247de8d993673c99e539d7a5ecd688c1b3c3afe3
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/198194
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra: remove PHERIPH_NO_ENB in vi_sensor2
Jihoon Bang [Thu, 7 Feb 2013 02:52:39 +0000]
ARM: tegra: remove PHERIPH_NO_ENB in vi_sensor2

Bug 1180011

Change-Id: I4f02f668d763b3cd91ff21f9748327eb2348c85f
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/198231
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agomedia: video: tegra: enable t14x config
Sudhir Vyas [Mon, 4 Feb 2013 19:53:19 +0000]
media: video: tegra: enable t14x config

Bug 1180011

Change-Id: Ide51c3927f8699b8d186f6f3eda87609c1d872a1
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197082
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra: ceres: Enable vim2_clk for camera
Sudhir Vyas [Tue, 5 Feb 2013 13:25:19 +0000]
ARM: tegra: ceres: Enable vim2_clk for camera

Sensor input clock (cam_mclk) is sourced from vi_sensor2
on ceres, which needs vim2_clk enable.

Bug 1180011
Bug 1180015

Change-Id: I061d43926eaa378e44cbdd00f93fff6b8210a2ec
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197467
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: dvfs: Add core dvfs safe entries
Prashant Malani [Thu, 7 Feb 2013 05:03:00 +0000]
ARM: tegra14: dvfs: Add core dvfs safe entries

Add safe entries for camera and display modules.

Bug 1217326

Change-Id: Id0c25d1f4070f7ff13d040c951259b22ca524180
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/198251
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agommc: core: don't modify ext csd raw fields
rrajk [Thu, 7 Feb 2013 16:45:55 +0000]
mmc: core: don't modify ext csd raw fields

Not touching raw fields in ext csd register in order to not break
the raw ext csd comparison check

Change-Id: I7ab01cd280288c5e7ea319d0e87b4acd1fd1fdf0
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/198429
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomfd: max77660: Remove Global LPM config
Pradeep Goudagunta [Thu, 7 Feb 2013 06:45:13 +0000]
mfd: max77660: Remove Global LPM config

Max77660 doesn't support Global low power mode configuration.

Change-Id: Ife3211d6843b21f2b126d5bbe9fd17baed55eca6
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/198266
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopinctrl: max77660: add init flag for pins which is configured as gpio
Laxman Dewangan [Thu, 7 Feb 2013 13:15:23 +0000]
pinctrl: max77660: add init flag for pins which is configured as gpio

If any pin is configured as gpio and if it is require in gpio output
mode then provide provision to set the initial state of the pins.

bug 1232806

Change-Id: Ibdf34518a22c3d6b3c02d86f10186fc4be89bab4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198371

5 years agoregulator: fix disable_dvfs for buck
shawn joo [Wed, 6 Feb 2013 09:11:52 +0000]
regulator: fix disable_dvfs for buck

fix Disable DVFS for buck, POR is enable.
this feature will be set on board power.

Bug 1231220
Bug 1230814

Change-Id: I25176d733a38b84ec32d43734bfec5aee2e4e50f
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/197826
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm: tegra: tegra_bb: clock enable
shawn joo [Tue, 5 Feb 2013 06:25:05 +0000]
arm: tegra: tegra_bb: clock enable

BBC clock enables on tegra_bb.
remove BBC clock setting from clk init table.

Change-Id: I002cc2e4408a03a1065dcd6dd563628e7c6a096c
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/197324
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: max77660: fix voltage range for buck4
shawn joo [Thu, 7 Feb 2013 00:13:04 +0000]
regulator: max77660: fix voltage range for buck4

buck4 voltage range is 0.6 ~ 1.5v.
fix min voltage from 0.8 to 0.6.

Bug 1177376

Change-Id: I7ded8fbfe46d3e749e04008becee3d56f7f0d2f4
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/198178
Reviewed-by: Neil Patel <neilp@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: dvfs: Fix voltage resolution issue
Seshendra Gadagottu [Wed, 6 Feb 2013 22:05:44 +0000]
ARM: tegra: dvfs: Fix voltage resolution  issue

Maximum volatage should be in steps of PMIC
voltage resolution.

Change-Id: I78bc8d7665b417e924895816eafc0d1ffe1eb1c2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/198135
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoASoC: Change codec_name in dai_link
Ravindra Lokhande [Wed, 6 Feb 2013 08:38:16 +0000]
ASoC: Change codec_name in dai_link

For T14x codec_name in dai_link is changed.

Change-Id: I7addef240355b2170f23a5447df83d23ee5c5ce4
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/197813
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agomfd: max77660: do not write invalid bits in GLBLCNFG0
Laxman Dewangan [Wed, 6 Feb 2013 19:27:01 +0000]
mfd: max77660: do not write invalid bits in GLBLCNFG0

As per ES1.0 errata, do not write any invalid bits/value in the
GLBLCNFG0 register.

bug 1228630

Change-Id: Ib4442ce9f89cce984c58039a6f26aa4fd53b1493
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198068
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Disable auto discharge of LDO1 in normal mode
Laxman Dewangan [Wed, 6 Feb 2013 19:25:44 +0000]
regulator: max77660: Disable auto discharge of LDO1 in normal mode

As per ES1.0 errata, disable the auto discharge of LDO1 when LDO1 in
normal mode.

bug 1228630

Change-Id: I92006c77d9c6dd97b3a2865027cb89b6a46a8247
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198067

5 years agogpio: max77660: do not implement debaunce for GPIO1 for ES1.0
Laxman Dewangan [Wed, 6 Feb 2013 19:24:16 +0000]
gpio: max77660: do not implement debaunce for GPIO1  for ES1.0

As per ES1.0 errata, debaunce of GPIO1 does not work. Returning the error
in this case.

bug 1228630

Change-Id: I836951d6e9cf7d11679226abb2b4add7f4f03268
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198066

5 years agostaging: iio: adc: max77660: ignore ADC0 channel for ES1.0
Laxman Dewangan [Wed, 6 Feb 2013 19:21:46 +0000]
staging: iio: adc: max77660: ignore ADC0 channel for ES1.0

As per ES1.0 errata, do not do ADC conversion for ADC0 channel.

bug 1228630

Change-Id: I7602ce0fdbef9acbd2c3ecd7da770126c7571212
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198065

5 years agomfd: max77660: reflect correct ES minor version
Laxman Dewangan [Wed, 6 Feb 2013 17:42:47 +0000]
mfd: max77660: reflect correct ES minor version

CID5 Register tells direct ES minor version and so no need to
add any value in this minor version.

ES1.0 is device revision 1.
ES1.1 is device revision 2.
ES1.2 is device revision 3.

Also prints all CIDs register and add api to direct check whether device is
ES1.0 or not to implement the ES1.0 erratas.

Change-Id: Ie1bddfe936cafd20213bdc72f8238c15fc39607c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198064

5 years agoarm: tegra: ceres: Fix backlight for smart panel
rrajk [Wed, 6 Feb 2013 15:29:22 +0000]
arm: tegra: ceres: Fix backlight for smart panel

pinmux and platform data changes

Change-Id: I86c29cf47b4cc2f1ad667cee38a97b1ba26aef37
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/197989
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dc: WAR of SHIFT_CLK_DIV update.
Kevin Huang [Tue, 29 Jan 2013 23:12:52 +0000]
video: tegra: dc: WAR of SHIFT_CLK_DIV update.

Bug 1225291
Bug 1161019

Change-Id: I699e64a1f6464eeddae5275a55cd2b285badc698
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/195272
(cherry picked from commit 880d4dc1ce348e66509f6cb50fcd1683856e0f26)
(updated cherry-pick to correct build failure)
Reviewed-on: http://git-master/r/196541
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agomfd: max77660: add api for getting version
Laxman Dewangan [Wed, 6 Feb 2013 16:17:54 +0000]
mfd: max77660: add api for getting version

Read CID5 register for getting device Revision and API to get
revision number which can be used by different sub modules of
this device.

Change-Id: Ie9394d4e36b4b8e6e15fa4af7cbebaafc3fb7e42
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198013

5 years agoARM: tegra: Enable cl_dvfs clocks by default
Chaitanya Bandi [Wed, 6 Feb 2013 14:49:01 +0000]
ARM: tegra: Enable cl_dvfs clocks by default

cl_dvfs clock is required on for PWR_I2C

Bug 1230603
Bug 1231822

Change-Id: Ic1e41e7204b583640fb0ef782e6efb583a21aa03
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/197982
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomedia: video: tegra: Enable vim2_clk for cam_mclk
Sudhir Vyas [Tue, 5 Feb 2013 13:13:18 +0000]
media: video: tegra: Enable vim2_clk for cam_mclk

Program vim2_clk, which is needed to enable cam_mclk on
t148 ceres.

Bug 1180011
Bug 1180015

Change-Id: I2593a35fc0ab9c8ab4ff8ea1f5d0e259ec2da0db
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/197466
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14: clock: Fix vi_sendor and cam_mclk
Hoang Pham [Wed, 6 Feb 2013 06:43:24 +0000]
ARM: tegra14: clock: Fix vi_sendor and cam_mclk

- cam_mclk is enable bit of vi_sensor
- cam-mclk2 is enable bit of vi_sensor2

Change-Id: I2cb483d2651e09129c29160ef4ca1bcdee86cfb4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/197759
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Fix order in clk_init_table
Kaz Fukuoka [Tue, 5 Feb 2013 02:58:06 +0000]
ARM: tegra14: clock: Fix order in clk_init_table

Change-Id: I511bfe90acd919a0184069eff91180f032607c4d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/197246
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: dvfs: Add safe dvfs table for isp
Kaz Fukuoka [Tue, 5 Feb 2013 03:13:50 +0000]
ARM: tegra14: dvfs: Add safe dvfs table for isp

On Tegra14, isp became independent from vi.

Change-Id: I16346fb70ee709f0534b1d7b0cf79f509ef4556d
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/197252
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agodrivers: staging: nvshm: Add flow control on TX
Martin Chabot [Tue, 29 Jan 2013 12:49:04 +0000]
drivers: staging: nvshm: Add flow control on TX

Flow control on TX
Change spin lock in iobuf alloc/free for irq use

Bug 1226213
Bug 1227082

Change-Id: Ic5fa063bc43689b1d543b8cbd81207b5aee1f04f
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/195115
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Greg Heinrich <gheinrich@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoregulator: max77660: register all regulators
Laxman Dewangan [Sat, 2 Feb 2013 08:23:14 +0000]
regulator: max77660: register all regulators

Whether the regulator plaform data is available or not for max77660 regulators,
register all regulator of max77660.

Change-Id: Id71411a6d7909720e1c0c2070c9a636a89604b56
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196735
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Pass regulator platform data pointers in array
Laxman Dewangan [Sat, 2 Feb 2013 08:06:38 +0000]
regulator: max77660: Pass regulator platform data pointers in array

In place of passing the limited regulator platform data and number
of platform data, pass platform data of all regulators in array. The
regulator id will direct relate to index of array. If any regulator is
unused in the given platform then NULL can be passed in place of valid
pointer.

Change-Id: Ib9f896e0b2f71c120da3a0348c00bfd8eb41862e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196734

5 years agomfd: max77660: move regulator and battery charger platform data to core
Laxman Dewangan [Tue, 5 Feb 2013 12:53:50 +0000]
mfd: max77660: move regulator and battery charger platform data to core

It is require to reference the definition from regulator header
to core header, it is better to keep all definition in one place
in place of scattering informations.

Change-Id: Ia418a40d75c408887ea96f0efa7445e929c88b00
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196733

5 years agomfd: max77660: cleanups in header
Laxman Dewangan [Sat, 2 Feb 2013 07:24:57 +0000]
mfd: max77660: cleanups in header

Run the checkpatch and fix the error/warnings. Also remove unused variable/definition
from header.

Change-Id: Ia5f0c338e07516523354164a49814ac1935ae7a6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196732
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra148: uncompress: PLLP bypass for UART
Bitan Biswas [Mon, 4 Feb 2013 15:14:31 +0000]
ARM: tegra148: uncompress: PLLP bypass for UART

Fix the PLLP frequency to 408MHz in place of reading it from PLLP register.

Change-Id: I484901f01271d0f67b30ae10df13eb1d84a10718
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/197017

5 years agoARM: tegra14: clock: Fix common clock initialization
Alex Frid [Mon, 4 Feb 2013 13:48:43 +0000]
ARM: tegra14: clock: Fix common clock initialization

Change-Id: I48a2650eccbf4275ea88aa95d4e2f258fd8c705d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196997
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: correct the clock for spi
Kunal Agrawal [Mon, 4 Feb 2013 11:25:40 +0000]
ARM: tegra14: clock: correct the clock for spi

changed from tegra14-spi to tegra11-spi as
the spi driver is named tegra11-spi

Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Change-Id: I1f08f19c346bb640404ebc95dac078d41af30288
Reviewed-on: http://git-master/r/196953
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: Correct I2C5 memory size to 256
Chaitanya Bandi [Mon, 4 Feb 2013 10:42:45 +0000]
ARM: tegra: Correct I2C5 memory size to 256

Change-Id: I5b138eadb38841dc0c31355e9ed4363fe7e9a805
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/196951
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: config: Move EDP_LIMIT to tegra14x defconfig.
Gaurav Sarode [Sat, 2 Feb 2013 01:17:53 +0000]
ARM: tegra: config: Move EDP_LIMIT to tegra14x defconfig.

Change-Id: Ibe34e368980052613929422a28e1de711113cb8f
Signed-off-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-on: http://git-master/r/196662
Reviewed-by: Jean Huang <jeanh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm: tegra: tegra_bb: add variable on bb structure
shawn joo [Sat, 2 Feb 2013 00:14:02 +0000]
arm: tegra: tegra_bb: add variable on bb structure

add buck4 and ldo8 variable on tegra bb structure

Change-Id: I1be04acbd4f190c4397b8d260ab3b6900d74c7e5
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/196641
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: add enable input(En3)
shawn joo [Fri, 1 Feb 2013 06:02:06 +0000]
regulator: add enable input(En3)

add enable input control for EN3.
when calling regulator_enable() for buck4 or ldo8, en3 will be enabled.
otherwise buck4 and ldo8 will be off.
by calling regulator_disable() for buck4 and ldo8, it will be off.
add disabling dvfs condition for buck 1-5

Bug 1177376

Change-Id: I303b0ae6acf9139ef9d6b566191d607652206f02
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/196590
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra14x: Disable PLLP lock status bit
Prashant Malani [Wed, 30 Jan 2013 23:04:19 +0000]
ARM: tegra14x: Disable PLLP lock status bit

After LP0 entry, PLLP lock status bit, stored in
FLOW_IPC_STS register, should be cleared.

Bug 1160000

Change-Id: Ie14c5684e8b673dacdcd66f853aae5e9408f6373
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/195715
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agotegra: soctherm: disable thermals init for tegra14x bringup
Jean Huang [Thu, 31 Jan 2013 02:58:06 +0000]
tegra: soctherm: disable thermals init for tegra14x bringup

Change-Id: I3a1466d4b42f29b211701edf4d7854726df64815
Signed-off-by: Jean Huang <jeanh@nvidia.com>
Reviewed-on: http://git-master/r/195802
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agopm: EDP: enable EDP framework and EDP_LIMIT for tegra14x
Jean Huang [Wed, 30 Jan 2013 01:51:17 +0000]
pm: EDP: enable EDP framework and EDP_LIMIT for tegra14x

Change-Id: I2b8183fc26347e1b9d4454d55e1e5431e3ba7996
Signed-off-by: Jean Huang <jeanh@nvidia.com>
Reviewed-on: http://git-master/r/195358
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoARM: tegra14: clock: Add safe DVFS table
Kaz Fukuoka [Thu, 31 Jan 2013 04:19:57 +0000]
ARM: tegra14: clock: Add safe DVFS table

bug 1213494

Change-Id: I60f31845af6cc03e1489678a71cb19fb72e5443b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/195823
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: la: Add bootup LA values for T14x
Krishna Reddy [Fri, 1 Feb 2013 06:51:38 +0000]
arm: tegra: la: Add bootup LA values for T14x

Bug 1219767

Change-Id: I6930dc942418b494a3674f754f4e5b8201579434
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/196312
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Add MC clock chain gate
Kaz Fukuoka [Thu, 31 Jan 2013 20:06:55 +0000]
ARM: tegra14: clock: Add MC clock chain gate

bug 1056728
bug 1213494

Change-Id: Icab2a458f15a3a9d281e475717c1526f2fffdcce
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/196118
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: tegra_bb: add regulator enable/disable
shawn joo [Fri, 1 Feb 2013 06:43:22 +0000]
arm: tegra: tegra_bb: add regulator enable/disable

Add regulator enable on proble and disable on remove for buck4 and ldo8.
once the regulator is enabled, en3 will be enabled so that bb_pwr_req can control them.
buck4 is set to 1.1v and ldo8 to 0.9v.
Enable clock for pll_p_bbc and mc_bbc.

Bug 1177376
Bug 1226031

Change-Id: I7cdb4421e8cdebeee398767b7749c7888103b008
Signed-off-by: shawn joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/194722
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoASoC: Integrating DMIC in ALSA.
Ankit Gupta [Thu, 31 Jan 2013 07:51:30 +0000]
ASoC: Integrating DMIC in ALSA.

This is a set of crude changes which will help in integrating
DMic drivers with ALSA framework. Following are the major changes:

o DMic ASoC machine driver.
o DMic Platform driver.
o Added support for S20_3LE format as per DMic POR.
o Added support for DMic rates and format in dummy DMic codec.
o AHUB: added the functionality to use stereo conversion.
o Config file changes to enable DMic driver build.
o To build with new sound card, run this command:

$ ksetup tegra_dolak_android_defconfig
$ krebuild

Note : In this change, a separate card is registered for DMIC.
This will be helpful in bringing-up DMic. Later on, DMic CPU
dai's can be binded with other codec drivers (e.g. max98091)

Change-Id: I0c68d21786cbba42f0829590fe2d7585f0fdb5b3
Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com>
Reviewed-on: http://git-master/r/195892
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoARM: tegra: add tegra_bbc_proxy driver
Neil Patel [Mon, 28 Jan 2013 20:50:39 +0000]
ARM: tegra: add tegra_bbc_proxy driver

The Tegra BBC Proxy driver handles EDP, ISO BW, and LA related
initialization for the BBC core

Bug 1177400

Change-Id: Iaf1e000a235f01f9ff543e8966daa94980f1ab16
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/194816
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: pinmux: ceres: fix pinmux warnings
Ashwini Ghuge [Fri, 1 Feb 2013 08:44:48 +0000]
ARM: tegra: pinmux: ceres: fix pinmux warnings

Update GPIO_PINMUX macro to take default od
settings, remove od field from ceres header file
for GPIO_PINMUX's. Update fsafe values in t148
pinmux table. Remove support from board file
to non tristate gpio pins.

Bug 1178627

Change-Id: I8fa02b32992ab800a887ffc5473f1e9bcb48938e
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/196347
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agousb: gadget: tegra: Fix usb device mode post LP0
Suresh Mangipudi [Thu, 31 Jan 2013 15:26:00 +0000]
usb: gadget: tegra: Fix usb device mode post LP0

adb was not working after device resumed from LP0. Added support
for the same.

Bug 1178651

Change-Id: I4605ff2c6b5c63eaf1398ac7011d04baaef8d122
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/196033
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agomfd: max77660: Fix power off cfg register address
Pradeep Goudagunta [Fri, 1 Feb 2013 08:32:52 +0000]
mfd: max77660: Fix power off cfg register address

Bug 1225365

Change-Id: I5ef7f18370e50e0f2f50beb17fad01a52ea615a2
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/196340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: Remove GPIO request for HDMI HPD
Chaitanya Bandi [Thu, 31 Jan 2013 08:50:15 +0000]
ARM: tegra: Remove GPIO request for HDMI HPD

Removed GPIO request for HDMI HPD from board files
as it is moved to hdmi driver.

Bug 1221130

Change-Id: I95de09eaf61bcb9f387b924ff78fbcbcaeec5038
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/195919
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dc: Move hpd GPIO request to hdmi driver
Chaitanya Bandi [Thu, 31 Jan 2013 08:16:16 +0000]
video: tegra: dc: Move hpd GPIO request to hdmi driver

Made these changes:
1. Moved hpd GPIO request to hdmi driver
2. Use Threaded irq to support PMIC gpio for hpd
3. Use rt_mutex instead of spinlock to allow sleepable calls
 while determining GPIO value through I2C PMIC.

Bug 1221130
Bug 1180971

Change-Id: I6eae4da484a34bcae873eabc2455389d46cc6c60
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/195900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: move panel board IDs to tegra-board-id.h
Bitan Biswas [Thu, 31 Jan 2013 19:26:18 +0000]
ARM: tegra: move panel board IDs to tegra-board-id.h

Relocated board ID for panels to fix build error due
to redefinition.

Change-Id: I849beaf57cc980d82ba93fb5b2f50ee8228f283d
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/196100
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra11: config: enable MAX77660_ADC driver
Laxman Dewangan [Fri, 1 Feb 2013 05:29:11 +0000]
ARM: tegra11: config: enable MAX77660_ADC driver

Change-Id: I3beb08dbb58c2bbe237bb3843e7b22648b3d5eac
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196274

5 years agoARM: tegra: t14x: PL310 data and tag Latency
Seshendra Gadagottu [Wed, 30 Jan 2013 00:53:10 +0000]
ARM: tegra: t14x: PL310 data and tag Latency

Set the safe PL310 data and tag latencies for
T14x silicon bringup.

Change-Id: I35a07d714f7993608699a6348cfa89b527d7c9a3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/195328

5 years agoARM: tegra: emc: Disable ACPD during MRRs
Alex Waterman [Wed, 23 Jan 2013 20:59:39 +0000]
ARM: tegra: emc: Disable ACPD during MRRs

During mode register reads, disable ACPD.

bug 1170170

Change-Id: I4ca25af3e2808a70cf943d224735c5c26ed6d471
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/195773
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: tegra14: clock: Fix new clocks
Kaz Fukuoka [Thu, 31 Jan 2013 03:55:54 +0000]
ARM: tegra14: clock: Fix new clocks

- Added "isp" register offset.
- Removed duplicated "mipibif".

bug 1213494

Change-Id: Ib7e60c8d2b3191b37cff3e4cc6a6963aa672f790
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/195819
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: t14x: Update powergate partition header
Seshendra Gadagottu [Tue, 29 Jan 2013 05:30:44 +0000]
ARM: tegra: t14x: Update powergate partition header

Update power gate partition header for t14x.
Updated some of the missing partitions and
total number of partitions.

Change-Id: I7d569ac254cf7e4db6be3ded882a6a727e4fcb1e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/194815
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra14x: add BB checking in pm code
Prashant Malani [Thu, 1 Nov 2012 18:50:57 +0000]
ARM: tegra14x: add BB checking in pm code

Add condition checks to query IPC registers
and conditionally branch to LP0 or LP1BB.

Bug 1160000

Change-Id: I3a7e151a5523a338cef7e83302af460e12323c14
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/195637
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agostaging: iio: adc: max77660: add adc driver
Laxman Dewangan [Thu, 31 Jan 2013 15:06:13 +0000]
staging: iio: adc: max77660: add adc driver

Add adc driver for MAXIM MAX77660 PMIC. This device support 13 channels
12 bit ADC.

Change-Id: I63779ea032d2e6f576a481c9fd6b499aa0c0858f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196022

5 years agomfd: max77660: add max77660-adc as mfd device
Laxman Dewangan [Thu, 31 Jan 2013 15:05:23 +0000]
mfd: max77660: add max77660-adc as mfd device

Change-Id: I8347e0fda539ad255e635633c3d99438ea0ce2d0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/196021

5 years agomfd: max77660: Update dependency flags
Pradeep Goudagunta [Thu, 31 Jan 2013 13:36:21 +0000]
mfd: max77660: Update dependency flags

max77660 depends on regmap irq also.

Bug 1222358

Change-Id: I631c5f2a6da174970ab6ab85d83f188a33b2eb03
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/196005
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agowatchdog: max77660: correct dependency flag
Pradeep Goudagunta [Thu, 31 Jan 2013 13:09:28 +0000]
watchdog: max77660: correct dependency flag

Bug 122235

Change-Id: Iebc1c97d0c973db9d17749f70099458b94e9079b
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/196004
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: Enable PIN_CTRL for T14x
Pradeep Goudagunta [Thu, 31 Jan 2013 13:07:55 +0000]
ARM: tegra: Enable PIN_CTRL for T14x

Bug 1222358

Change-Id: Id2eefdb1488cd46ec2f4f3b7d473be299b7d993a
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/196003
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: max77660: charger: add vbus regulator
Laxman Dewangan [Thu, 31 Jan 2013 08:30:09 +0000]
power: max77660: charger: add vbus regulator

MAX77660 charger module is capable of generating the VBUS supply.
Add regulator for VBUS supply control through regulator driver.

bug 1225498

Change-Id: Id2941b91b27aca3fd7136f7c0434f7e217a8dc37
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/195904

5 years agomipi_bif: Fix build error
Bitan Biswas [Wed, 30 Jan 2013 16:31:21 +0000]
mipi_bif: Fix build error

pm_runtime header file added to fix build error

Change-Id: I7403b7ea937c57c7a170bfa764026e0c81200581
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/195593
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: tegra_bb: add sysfs node state
Vinayak Pane [Thu, 27 Dec 2012 21:21:22 +0000]
arm: tegra: tegra_bb: add sysfs node state

The sysfs node "state" will show state of BB2AP_MEM_REQ signal.
This essentially shows BBC's current power state as hibernate/active.

Bug 1160000

Change-Id: I40451552cbe4c8c13e8855788e59c15a821fad87
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/194842
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agodrivers: staging: nvshm: fix all warnings
Martin Chabot [Tue, 29 Jan 2013 12:44:42 +0000]
drivers: staging: nvshm: fix all warnings

Now warning raises error (-Werror)

Bug 1226209

Change-Id: I73314db7911b12efb57d1141cdf1aefe2ae3cb23
Signed-off-by: Martin Chabot <mchabot@nvidia.com>
Reviewed-on: http://git-master/r/195114
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Greg Heinrich <gheinrich@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoUSB: gadget: tegra: Remove SW WAR for mem_align
Rohith Seelaboyina [Tue, 29 Jan 2013 13:11:51 +0000]
USB: gadget: tegra: Remove SW WAR for mem_align

Remove S/W WAR for mem_alignment and cohrency as
it is Fixed in T148

Bug 1195770

Change-Id: I38c774c5c4befd6712fc637c5c82dda6b8d7910b
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/195128
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: usb_phy: enable coherency and mem_alignment
Rohith Seelaboyina [Tue, 29 Jan 2013 14:03:28 +0000]
ARM: tegra: usb_phy: enable coherency and mem_alignment

Enable coherency and mem_alignment as this issue is
fixed for T148.

Bug 1195770

Change-Id: Idd0e1e5bd044a9a87a1d6a3d029cef955aa7d256
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/195127
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: pinmux: update pinmux-t14-tables.c
Ashwini Ghuge [Wed, 30 Jan 2013 07:06:59 +0000]
ARM: tegra: pinmux: update pinmux-t14-tables.c

Bug 1178627

Change-Id: Ie38847d6615c40f21e49bd35c9be40b659c2be2d
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/195084
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agowatchdog: max77660: initialize driver early
Laxman Dewangan [Wed, 30 Jan 2013 10:33:21 +0000]
watchdog: max77660: initialize driver early

Initialize watchdog time early so that it can handle the watchdog timer
expire effectively.

Bug 1225350

Change-Id: I7338863639bbc3c634a891ff418b3c486410779e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/195510
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoregulator: max77660: Add support for pwm dvfs
Pradeep Goudagunta [Tue, 29 Jan 2013 05:56:16 +0000]
regulator: max77660: Add support for pwm dvfs

BUCK4 is capable of PWM based control.

Bug 1225360

Change-Id: Ic7e46600d04cc1974550e35c8dfc37082c84e129
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/194984
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agostaging: iio: light: max44005: Correct CLEAR_ENABLED flag
Sri Krishna chowdary [Tue, 29 Jan 2013 10:49:04 +0000]
staging: iio: light: max44005: Correct CLEAR_ENABLED flag

CLEAR channel is enabled if clear or temp is being used.

Bug 1190013

Change-Id: If6c804ea9dc38777cadbd4a22f01b5277e459c0c
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/195077
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoASoC: tegra: Make use of max97236 audio amplifier
Ravindra Lokhande [Mon, 28 Jan 2013 18:11:20 +0000]
ASoC: tegra: Make use of max97236 audio amplifier

Change-Id: I87ae237f8430170bfab0dd99b7e5410253833a3d
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/194768
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoASoC: Add max97236 driver
Ravindra Lokhande [Mon, 28 Jan 2013 17:55:06 +0000]
ASoC: Add max97236 driver

Add driver for max97236 audio amplifier driver.

Change-Id: I7e62fa1bd6fee7fe57fde83ba649b288e784f145
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/194757
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Gaurav Sarode <gsarode@nvidia.com>

5 years agoARM: tegra: t14x: Default speedo value
Seshendra Gadagottu [Tue, 29 Jan 2013 05:15:39 +0000]
ARM: tegra: t14x: Default speedo value

Set the safe default speedo vale for T14X CPU DVFS

Bug 1217329

Change-Id: I26fcba21953e31a7dcf227f59f3137e39fe564d8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/194967
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>

5 years agoARM: tegra: fix dolak_sim build
Seshendra Gadagottu [Tue, 29 Jan 2013 06:47:11 +0000]
ARM: tegra: fix dolak_sim build

Fixed the issue with unused functions/variables

BUG 1164711

Change-Id: I72c3fa6f3db0d4681a3df05e86f07b5bfd04647b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/194998

5 years agoARM: tegra: t14x: Populate safe CPU DVFS tables
Seshendra Gadagottu [Tue, 29 Jan 2013 05:04:31 +0000]
ARM: tegra: t14x: Populate safe CPU DVFS tables

Updated CPU DVFS tables from the safe cvb coefficients provided.
This is for bring-up and actual tables will be updated once
real characterization data available after Silicon bring-up.

Bug 1217329

Change-Id: I052eab9ef8e6b61e1e75e056aa8e62dbcbd0a255
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/194965
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agousb: otg: tegra: add vbus detect through PMU
Rakesh Bodla [Tue, 29 Jan 2013 08:54:39 +0000]
usb: otg: tegra: add vbus detect through PMU

Adding the support to detect usb device cable
using PMU.

Bug 1178651

Change-Id: I20ab1f3339cd6fc781ade684d566b3f4ca0fa224
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/194759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoalarmtimer: Do not check for wake capability in registration
Chaitanya Bandi [Tue, 29 Jan 2013 12:34:04 +0000]
alarmtimer: Do not check for wake capability in registration

Removed the check if device has wakeup capablity
while registration as the wakeup policy has to come from
user space as per Documentation/power/devices.txt

Bug 1219152

Change-Id: I4994c603aac0afd54381dcaec239f2315831849f
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/195109
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agogpio: tegra: add tegra148 compatibility to of_match_table
aghuge [Tue, 29 Jan 2013 06:33:31 +0000]
gpio: tegra: add tegra148 compatibility to of_match_table

Bug 1178629

Change-Id: Iba2dff0ce54150b93c7f9389f5b43c190d4130d7
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/194995
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoi2c: tegra: Add CONFIG_LOAD register setting for T14x
Chaitanya Bandi [Mon, 28 Jan 2013 13:48:16 +0000]
i2c: tegra: Add CONFIG_LOAD register setting for T14x

Added CONFIG_LOAD register setting for T14x.

Change-Id: Ib667362cd8881d50f24c0942d3acbb40f7fbf9c5
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/194696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoi2c: tegra: Use IMMEDIATE option for I2C Bus Clear
Chaitanya Bandi [Mon, 31 Dec 2012 11:11:22 +0000]
i2c: tegra: Use IMMEDIATE option for I2C Bus Clear

Use Immediate option instead of Threshold in case of
I2C bus clear logic.

Bug 1210176

Change-Id: Idc1bd977cd0ac79092117ace5f3283d9219b1eb1
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/188220
(cherry picked from commit 3bf0ba5303b976bf94f147300b5a9132a8d8195b)
Reviewed-on: http://git-master/r/194668
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agommc: tegra: use gpio_get_value_cansleep
Naveen Kumar Arepalli [Tue, 29 Jan 2013 04:14:42 +0000]
mmc: tegra: use gpio_get_value_cansleep

use gpio_get_value_cansleep instead of use gpio_get_value

Bug 1178644

Change-Id: I6a56608396bb36b8dc5567aedbd6c5a807f7c7f6
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/194746
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: t14x: Default speedo value for FPGA
Seshendra Gadagottu [Tue, 29 Jan 2013 04:54:33 +0000]
ARM: tegra: t14x: Default speedo value for FPGA

Set the safe default speedo vale for T14X CPU DVFS
simulation testing.

Bug 1217329

Change-Id: I0955c12e0d4acb5e35fdc9395c09d66b3916ac2c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/194961

5 years agopower: max77660: change USB-HOST to USB
Rakesh Bodla [Mon, 28 Jan 2013 18:00:07 +0000]
power: max77660: change USB-HOST to USB

Currently support added is only for device cable.
Changing USB-HOST cable to USB device cable

Change-Id: Ib0f5b46f971c9a0a6cf359aedff2639b249298d9
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/194758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agogpio: max77660: exchange mask and val bits argument sequence
Laxman Dewangan [Mon, 28 Jan 2013 15:58:46 +0000]
gpio: max77660: exchange mask and val bits argument sequence

The argument of max77660_reg_update() take the val first and
then mask. Pass parameters in correct sequence.

Change-Id: Ieb2d20a78eb0afd798dcdfa6b99442a56fc95e87
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/194730