6 years agovideo: tegra: dtv: Add ioctl for buffer size query
Adam Jiang [Wed, 24 Apr 2013 06:56:27 +0000]
video: tegra: dtv: Add ioctl for buffer size query

Userspace has to know the exact buffer size of DTV driver. Export it
with new ioctl() command.

Bug 1061456
Bug 1258577

Change-Id: I7676d0ab90775399245ffa0724bb34845151c680
(cherry picked from commit f88099b4f579e77e7b1defc404ff924caa70b79d)
(cherry picked from commit bedee58c6744784771e7bcbd55b7a0707f89a345)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224685
Reviewed-on: http://git-master/r/244474
Reviewed-on: http://git-master/r/256190
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Replace misleading warnings
Adam Jiang [Wed, 24 Apr 2013 06:48:39 +0000]
video: tegra: dtv: Replace misleading warnings

The original "overflow" warning was misleading because when there are
pending DMA transferring it does not necessarily mean buffer had been
filled too much data. Instead, if transferred bytes are more than the
byte numbers required by DTV, driver should report this situation for it
indicates DMA queue-up is too slow.

Bug 1061456
Bug 1258577

Change-Id: I1c39076a1e4b9c018d4a67c08d0ff71c761fbbd5
(cherry picked from commit a5d313823a0daecd6596f8e7ac99cc95bcc17de6)
(cherry picked from commit 6bddd41af496e2c48e7ed676e051e45328fbedba)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224684
Reviewed-on: http://git-master/r/244473
Reviewed-on: http://git-master/r/256189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: push only one DMA request on read
Adam Jiang [Tue, 23 Apr 2013 08:40:43 +0000]
video: tegra: dtv: push only one DMA request on read

Each read() call on tegra_dtv device should only enqueue one DMA request
into DMA controller. In this way, DTV driver could avoid to waiting on
previous DMA-queued buffers to be finished. Thus, DMA buffer overlapping
could be ease. It also allows user-land run a tighten read() loop.

Bug 1061456
Bug 1258577

Change-Id: I75033c5cef43368636307093890422c1718f44ce
(cherry picked from commit b35f49d61559d336bab5efad6ab333152d80b63f)
(cherry picked from commit 1c71579a99a0dddfa4fc6a3a89a0a5d47782bc32)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224683
Reviewed-on: http://git-master/r/244472
Reviewed-on: http://git-master/r/256188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Make buffers configurable
Adam Jiang [Thu, 21 Mar 2013 04:09:41 +0000]
video: tegra: dtv: Make buffers configurable

Make DMA buffer count and size configurable via module parameters.

Bug 1061456
Bug 1258577

Change-Id: I45b188e09fb94add00c95cc6013e46a8af8636b0
(cherry picked from commit 9dc27fd2395fb46d4cc644e145aaa3c20f35e3d3)
(cherry picked from commit aab314b14d2c7971adaae5e9d5f23ff08ddcb58d)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224682
Reviewed-on: http://git-master/r/244471
Reviewed-on: http://git-master/r/256187
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Move swizzling into ioctl
Adam Jiang [Mon, 15 Apr 2013 09:21:09 +0000]
video: tegra: dtv: Move swizzling into ioctl

Move swizzling options into ioctl for providing a unique interface of
hardware configuration.

Bug 1061456
Bug 1258577

Change-Id: I6c9d9b171a170fbe9e9df78b4dac07347d63861e
(cherry picked from commit 25371c35ddf720fc2b975d5c20d81c32eec4ecf1)
(cherry picked from commit 8d408223cd6f26db34adb434ee54e2bf7a47b9e6)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224681
Reviewed-on: http://git-master/r/244470
Reviewed-on: http://git-master/r/256186
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarch: arm: tegra: Move DTV resources into mach
Adam Jiang [Mon, 8 Apr 2013 07:29:06 +0000]
arch: arm: tegra: Move DTV resources into mach

For management of the diversity on register definitions of DTV module,
move those definitions into mach/dtv.h.

fix Bug 1258577

Change-Id: I6d5ad063ba3ed44fb7ef6313f33946e261ad7f5b
(cherry picked from commit 899cb78401467cd6605d2151ca90c581383236c9)
(cherry picked from commit b83746e4b928daa773c025ba98a3ccdedca3f90c)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/217592
Reviewed-on: http://git-master/r/244469
Reviewed-on: http://git-master/r/256185
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Add warnings to buffer overflow
Adam Jiang [Fri, 19 Oct 2012 04:56:35 +0000]
video: tegra: dtv: Add warnings to buffer overflow

Application should always be notified if buffer overflow happened.

Bug 1061456
Bug 1258577

Reviewed-on: http://git-master/r/160891
(cherry picked from commit e23db607457e8435f86b32b48d55cbbff42e4cd1)

Change-Id: Iaa17470840a3c5817834aa20c7264f19b9ded6a9
(cherry picked from commit 656480eb88d030a26eaab9f75bf4486632f2d433)
(cherry picked from commit 7d38b09b7cfefedff7582b40400adb7e6870c1e2)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224680
Reviewed-on: http://git-master/r/244468
Reviewed-on: http://git-master/r/256184
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Add shared clock support
Adam Jiang [Mon, 22 Oct 2012 11:59:47 +0000]
video: tegra: dtv: Add shared clock support

DTV interface could run with 0-20MHz synchronizing clock. When DTV runs
with high speed, it is necessary to ensure system bus and EMC running on
higher frequency to support data transferring between the interface and
memory.

Bug 1061456
Bug 1258577

Change-Id: Id5af7cd8f8aa0373a5c45c9f9f884cd2b755e146
(cherry picked from commit 3370a67507a5ea08b0fe03943345dc34bde8fd7c)
(cherry picked from commit e4bb9378786655898c2f62a57319bdc05bd8e410)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224679
Reviewed-on: http://git-master/r/244467
Reviewed-on: http://git-master/r/256183
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dtv: Add DTV_STATUS into debugfs
Adam Jiang [Wed, 10 Oct 2012 09:04:51 +0000]
video: tegra: dtv: Add DTV_STATUS into debugfs

Expose DTV_STATUS register in debugfs which could be read by user land
applications.

Removed read operation over DTV_FIFO registers which may cause data
loss.

Bug 1061456
Bug 1258577

(cherry picked from commit e262f13e59e716d12a29116d24931af430909dd8)
(cherry picked from commit a7668922b555aca4ca0f5ca0569e4aa45383cb81)
(cherry picked from commit d14000d021e65b34735a167b2f313695b984e54c)
(cherry picked from commit 6a43783d1f9ce050b330eec42f1f77636073157d)

Change-Id: If4b5bd94fe8cc62f8a9695ec114345bd7cdd90a0
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/144430
Reviewed-on: http://git-master/r/224678
Reviewed-on: http://git-master/r/244466
Reviewed-on: http://git-master/r/256182
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agocpufreq: interactive: init default values at compile time
Todd Poynor [Fri, 21 Dec 2012 23:32:21 +0000]
cpufreq: interactive: init default values at compile time

Conflicts:
drivers/cpufreq/cpufreq_interactive.c

Bug 1329805

(cherry picked from commit 24942b269cc29f249b7e137f7a37c92c487e5a39)

Change-Id: I6d384940d432bdfb0214d44fd8a2730f509df852
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/254337
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agomfd: tps65090: do not provide num_reg_defaults_raw for regmap init
Laxman Dewangan [Thu, 1 Aug 2013 13:12:55 +0000]
mfd: tps65090: do not provide num_reg_defaults_raw for regmap init

There is no default data for tps65090 which is provided during
regmap init and hence it is not require to provide the information
about .num_reg_defaults_raw for caching. Cachign of register will
be done during access of registers.

This will avoid the warning
 tps65090 4-0048: No cache defaults, reading back from HW

bug 1249589

Change-Id: I4883a1b19e44fb93069871e70f39e2ea732d9a51
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/256853

6 years agoARM: tegra: laguna: configure overcurrent of GPU/Core rails for AMS
Laxman Dewangan [Thu, 1 Aug 2013 10:57:22 +0000]
ARM: tegra: laguna: configure overcurrent of GPU/Core rails for AMS

bug 1329929

Change-Id: If5714585c570a7ae328c3cc60683235919698c2b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/256816
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

6 years agovideo: tegra: host: Add ftrace for debug output
Terje Bergstrom [Wed, 31 Jul 2013 09:46:57 +0000]
video: tegra: host: Add ftrace for debug output

Allow redirecting nvhost_dbg() output to ftrace.

Change-Id: I5b5a556982713ec7a19bbdc51217c5a4bf6b419f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/256281
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Ken Adams <kadams@nvidia.com>

6 years agovideo: tegra: host: Preserve iova across PDE boundary
Terje Bergstrom [Wed, 31 Jul 2013 09:44:07 +0000]
video: tegra: host: Preserve iova across PDE boundary

When creating PTEs for GMMU, we have an outer loop for PDEs and inner
loop for PTEs. We cleared iova address at the beginning of outer loop,
which made the pages going to second PDE to have page addresses
starting from 0.

Bug 1339218

Change-Id: Ife7c8c191060c22d3af164852e35f20817b495e5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/256280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agommc: tegra: HS200 mode disable
Bitan Biswas [Fri, 26 Jul 2013 18:46:51 +0000]
mmc: tegra: HS200 mode disable

Kernel config MMC_SDHCI_TEGRA_HS200_DISABLE introduced
to disable default HS200 mode on EMMC devices.

bug 1330807

Change-Id: I4237c159c642a81b859c6559f9fbdac7c3593ed1
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/254480
(cherry picked from commit 82a7c2b88e765857a65840050f5ae0d4327f4055)
Reviewed-on: http://git-master/r/256256
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra12: clock: Fix mux inputs
Kaz Fukuoka [Wed, 31 Jul 2013 00:44:29 +0000]
ARM: tegra12: clock: Fix mux inputs

Change mux inputs to match with the latest Tegra12 spec.

Ported from http://git-master/r/192597 (change for Tegra14)

Change-Id: Ic40a339bd9bb6b39a6b927f22a39d7634f66751c
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/255831
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoiommu/tegra: Use 34-bit phys addresses on Tegra12
Terje Bergstrom [Tue, 30 Jul 2013 15:54:35 +0000]
iommu/tegra: Use 34-bit phys addresses on Tegra12

For Tegra12, physical addresses in SMMU PTEs are 34-bit. Change the
SMMU_PFN_MASK to cover PTE fields PA and RESERVED.

Bug 1322760

Change-Id: I722c43033c24e6eb7637dfc7eb8821a8ea90fcf6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/255650
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: enable cache maint optimizations on T124
Krishna Reddy [Fri, 26 Jul 2013 21:57:17 +0000]
arm: tegra: enable cache maint optimizations on T124

Change-Id: Ia1573355de07a3fc987b9b248ba51c504ab1b809
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/254533
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoCpufreq: interactive: Check actual freq before setting new freq
Puneet Saxena [Mon, 15 Jul 2013 09:27:12 +0000]
Cpufreq: interactive: Check actual freq before setting new freq

In case Actual freq is not updated till next timer interrupt
and new target freq comes same as actual freq.
Don't go for setting same frequency again.

Bug 1316765

Reviewed-on: http://git-master/r/249103
(cherry picked from commit d5a4d9622c27db40334ba2df3503c2d2e7457bcb)

Change-Id: If81786911fd85adb8469b49c59f2ab70ae12f96a
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/254352
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoARM: tegra: mc: Add updated T124 support for mcerr
Alex Waterman [Tue, 23 Jul 2013 22:12:21 +0000]
ARM: tegra: mc: Add updated T124 support for mcerr

The default info print function now supports T124 physical addresses.

Change-Id: I5b8b91bed508008221bff67a48462f01dd935287
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/252618
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra: mc: Make error handling make more sense
Alex Waterman [Tue, 23 Jul 2013 19:12:30 +0000]
ARM: tegra: mc: Make error handling make more sense

On T114 and later the errors being reported by the MC are starting
to grow in complexity. This takes that complexity and boils it down
into something more manageable for developers debugging SMMU and
other faults generated by the MC.

The aim of this patch is to make the errors more understandable and
correctly reflect the errors actually generated. The previous
approach to error handling was mis-representing certain errors.

Change-Id: Ie5b96d1a0ead344a3d1fa120e30b3152bfe23b70
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/252617
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agovideo: tegra: host: Return error on invalid handle
Terje Bergstrom [Wed, 31 Jul 2013 12:41:24 +0000]
video: tegra: host: Return error on invalid handle

When we get an invalid handle form user space, return error instead
of ignoring it.

Change-Id: I7e294df1b12d813bc6da536b953f2fa14a8d6c9c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/256334
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoinput: touchscreen: raydium add detection of AVC sensor
Xiaohui Tao [Tue, 30 Jul 2013 23:50:49 +0000]
input: touchscreen: raydium add detection of AVC sensor

Change-Id: I32db26ebfa18d219f2df05b75dcd5e45250c9b23
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/255809
Reviewed-by: Mitch Luban <mluban@nvidia.com>

6 years agoARM: tegra: powergating: Add reference count to displayB
Chao Xu [Mon, 29 Jul 2013 23:32:24 +0000]
ARM: tegra: powergating: Add reference count to displayB

Audio driver also plays with powergate/unpowergate of display,
so need to add reference count to displayB as well.

Bug 1332587.

Change-Id: I9033f72dadfc3918c78b1585781021d7167ef227
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/255270
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoiommu/tegra: smmu: set SDMMC client write ordered
Hiroshi Doyu [Fri, 5 Jul 2013 07:49:47 +0000]
iommu/tegra: smmu: set SDMMC client write ordered

Set SDMMC client write ordered.

Bug 1319012

Change-Id: I83abd891e9759a31778e7e4badf7d5a7ca8b5b8c
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/254824
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: fb: Make offset comparison android specific
pdabade [Thu, 6 Jun 2013 09:58:31 +0000]
video: tegra: fb: Make offset comparison android specific

Making current x and y offset comparison android specific.

Bug 1216329

Change-Id: Ie28d81fc2bff06237528fba56a348a442233e6c7
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/236257
(cherry picked from commit c1318d792c772d7faec437783a9513669bee54b4)
Reviewed-on: http://git-master/r/254450
Reviewed-by: Jong Kim <jongk@nvidia.com>
Tested-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agovideo: tegra: dc: fix the print information
Kerwin Wan [Tue, 16 Jul 2013 05:58:18 +0000]
video: tegra: dc: fix the print information

Change-Id: Icd50c383f7cfe619cf60a76c6ca74d616179eb8b
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/253140
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoARM: tegra: Filter common si/fpga clocks
Jeff Smith [Sat, 10 Nov 2012 05:29:34 +0000]
ARM: tegra: Filter common si/fpga clocks

Determine which clocks to init at run time for FPGA or silicon.

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ida42227136bfaff45013adb724354a1023f360a6
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252555
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM tegra: port non-clock common code to pre-si
Jeff Smith [Fri, 9 Nov 2012 07:37:14 +0000]
ARM tegra: port non-clock common code to pre-si

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ic895704c684ac131c4c6bbdcfed6901211d1e490
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: Move clock/power to pre-si
Jeff Smith [Fri, 9 Nov 2012 07:20:17 +0000]
ARM: tegra: Move clock/power to pre-si

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I93c215fff80e35767593918ffe88e7bb3e6e9f9a
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: Move panel config to pre-si
Jeff Smith [Fri, 9 Nov 2012 06:20:13 +0000]
ARM: tegra: Move panel config to pre-si

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Icf7a6f4a595dd3b7fdf26b61d348f0289f6f190c
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252552
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: Include dvfs/edp for pre-si build
Jeff Smith [Fri, 9 Nov 2012 00:34:04 +0000]
ARM: tegra: Include dvfs/edp for pre-si build

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I1fe2d6a603a1ade2cfeda220e81628b116c8df6f
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/252551
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Chetan Kumar Nagamangala Govindaiah <chetankumarn@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: Stub speedo at run time for pre-si
Jeff Smith [Thu, 8 Nov 2012 22:11:00 +0000]
ARM: tegra: Stub speedo at run time for pre-si

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ia4af498a5db8be9718cf417f3822cf3cd956e841
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252550
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agoARM: tegra: Use common board name for sim
Jeff Smith [Wed, 22 Aug 2012 05:43:07 +0000]
ARM: tegra: Use common board name for sim

Remove the _sim postfix on the board name. The sim
mode is now visible to user mode tests via sysfs.

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Id2ef2a0428112ef6dd2d5f577f769e43f7c05f0f
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252549
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agousb: tegra: Move to tegra pre-si config
Jeff Smith [Wed, 7 Nov 2012 07:19:23 +0000]
usb: tegra: Move to tegra pre-si config

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ia0b559545f8c71dc929d29878b1569d9f6209904
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

6 years agousb: xhci: tegra: enable SATA PADPLL clock if enabled
Ajay Gupta [Fri, 26 Jul 2013 17:25:29 +0000]
usb: xhci: tegra: enable SATA PADPLL clock if enabled

Enabled SATA PADPLL clock when xusb is owner of SATA lane.
Clock is being enabled inside driver based on feedback from clock
team as mentioned in bug.

Bug 1331741

Change-Id: I365a462281c4b8afe4af809a2a3d726bbb174e30
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/254517
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agousb: xhci: tegra: fix tcrtl/rctrl for t124
Ajay Gupta [Mon, 22 Jul 2013 16:55:20 +0000]
usb: xhci: tegra: fix tcrtl/rctrl for t124

TCTRL/RCTRL values cab be calculated either using xusb PADCTL registers
or using SNPS registers. As per latest discussion with HW team, we must
use SNPS registers when any of UTMIP port is owned by SNPS controller and
use XUSB PADCTL registers only when all UTMIP ports are owned by XUSB.

TCTRL/RCTRL is alwasy needed to be programmed on T114 due to a HW bug but
on T124 it needs to be programmed only during ELPG entry when PMC is being
ARMed. Refer table below on this.

T114 T124
1) Init Yes No
2) ELPG entry Yes Yes
3) LP0 exit Yes No

Bug 1334159

Change-Id: I8458598e8b0c74104e66d2452ebfbc8ffd982fda
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/252629
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agoarm: tegra: init tn8 and ardbeg as separate devices
Ahung Cheng [Mon, 29 Jul 2013 10:06:40 +0000]
arm: tegra: init tn8 and ardbeg as separate devices

Need to call DT_MACHINE_START for each platform so that
ro.hardware property is set according to platform name.
This also enforces one dts file per platform.

Bug 1328162

Change-Id: I368669af638ec2ee237fe090ad70c0d63375fef1
Signed-off-by: Ahung Cheng <ahcheng@nvidia.com>
Reviewed-on: http://git-master/r/255003
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agousb: xhci: tegra: save dfe value to ss port registers
Ajay Gupta [Wed, 24 Jul 2013 18:22:30 +0000]
usb: xhci: tegra: save dfe value to ss port registers

Bug 1333330

Change-Id: I8bd1f826ef6526e5116c09a2677ae67259bfff92
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253581
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agoARM: tegra: ardbeg: fix gpio expander number
Ajay Gupta [Wed, 24 Jul 2013 00:10:53 +0000]
ARM: tegra: ardbeg: fix gpio expander number

GPIO expander numbers are indexed as 0-7 and then 10-17 so
P11 maps to base + 9

Bug 1338745

Change-Id: Iddce1a4468257f31da27a48c4b94140e002cbf7a
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253580
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agousb: xhci: tegra: program SATA PAD PLL
Ajay Gupta [Mon, 22 Jul 2013 18:13:49 +0000]
usb: xhci: tegra: program SATA PAD PLL

Needed as per updated BCT from hw team

Bug 1338745

Change-Id: I9d2dd57ef5d91d02fa6226abd9bfc8bf7c7de145
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agoARM: tegra: decide UTMIP1/2 ownership based on odmdata[25]
Ajay Gupta [Fri, 19 Jul 2013 18:07:49 +0000]
ARM: tegra: decide UTMIP1/2 ownership based on odmdata[25]

XUSB should own UTMIP1/2 when odmdata[25] is set.

Bug 1338735

Change-Id: I19d26859e969d04d261f01c1e6d873fced853076
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/253578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agovideo: tegra: gk20a: turn on cya15 bit in l1c_dbg
Ashish Srivastava [Tue, 16 Jul 2013 08:41:39 +0000]
video: tegra: gk20a: turn on cya15 bit in l1c_dbg

Setting the CYA15 bit to 1 in the L1C_DBG register.
Note: we'll re-code this without the magic when the register
makes it into the hw_gr_gk20a.h file.

Change-Id: I7337bef1d86db3a584d6bec0563068a37a6d3723
Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com>
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/256377

6 years agoARM: tegra: bbc: call pm_wakeup_event() in IRQ if going to suspend
Hervé Fache [Fri, 7 Jun 2013 12:43:31 +0000]
ARM: tegra: bbc: call pm_wakeup_event() in IRQ if going to suspend

If an IRQ is fired as we are going to suspend then we want to abort
and make sure voltage and frequency remain high enough for BB to
operate.

The suspend function must not ack the IRQ as the handler shall be
fired and do it.

Bug 1294872

Change-Id: I20e3872b58814402e5ee5945bb6d91c2651eaacb
Signed-off-by: Hervé Fache <hfache@nvidia.com>
Reviewed-on: http://git-master/r/239765
(cherry picked from commit 022b42d27f9dcd3614cd44d297326c8778c66840)
Reviewed-on: http://git-master/r/256176
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: host: gk20a: use correct dma_len during gmmu map/unmap
Krishna Reddy [Tue, 30 Jul 2013 23:15:52 +0000]
video: tegra: host: gk20a: use correct dma_len during gmmu map/unmap

Bug 1339218

Change-Id: I90c8680b3b4bfb3306789b785069066b83a0793d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/255788
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra: clocks: Remove always ON for SDMMC clk
Pavan Kunapuli [Tue, 30 Jul 2013 10:54:17 +0000]
ARM: tegra: clocks: Remove always ON for SDMMC clk

SDMMC clocks need not be enabled by default for T12x.

Bug 1328858

Change-Id: Id8283c83f0e520275125128e822e7960a288f9a9
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255601
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agommc: sdhci: Enable host clock before reg access
Pavan Kunapuli [Tue, 30 Jul 2013 10:51:16 +0000]
mmc: sdhci: Enable host clock before reg access

Some SDMMC controllers require host clock to be enabled before accessing
the controller registers. Define SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK to
handle this behavior.

Ensure clock is enabled before register accesses in suspend/resume path.

Enabled SDHCI_QUIRK2_REG_ACCESS_REQ_HOST_CLK for Tegra SDMMC controllers.

Bug 1328858

Change-Id: I732d0597a715c96bc546beb4bba1beb86e51c302
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255600
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agommc: core: set mmc signal voltage after clk is turned on
Kerwin Wan [Mon, 15 Jul 2013 22:29:57 +0000]
mmc: core: set mmc signal voltage after clk is turned on

The controller clk will be turned on then turned off when mmc does
power up setting. System will hang if signal voltage is set with clk is off.
After mmc does power on settings, the controller clk will be on so it's safe
to set signal voltage at that time.

Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/249393
(cherry picked from commit bcf30d2b52713acb87fef895635521ac3d3d2855)

Bug 1328858

Change-Id: I992ebd01794574e6236c4bf67480d343b3cfc24a
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/255599
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>

6 years agoasoc: tegra: fix NULL pointer dereference
Deepak Nibade [Tue, 30 Jul 2013 08:42:20 +0000]
asoc: tegra: fix NULL pointer dereference

- fix Coverity issues
- fix dereference of null pointer
  Coverity id : 23721
  Coverity id : 23735

Bug 1329327

Change-Id: I877959ab5446e09648a52fd18fd4a219c3f01e7e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/255453
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sri Krishna Chowdary <schowdary@nvidia.com>
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

6 years agoARM: dma-mapping: Fix crash w/o IOMMU enabled
Hiroshi Doyu [Tue, 30 Jul 2013 08:41:44 +0000]
ARM: dma-mapping: Fix crash w/o IOMMU enabled

Allow kernel to boot w/o TEGREA_IOMMU_SMMU

Bug 1285960

Change-Id: I8a8adac713ca0e76ca410a1f8cd4345488aae774
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/255451
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra: ardbeg: configure overcurrent of GPU/Core rails for AMS
Laxman Dewangan [Wed, 31 Jul 2013 05:56:03 +0000]
ARM: tegra: ardbeg: configure overcurrent of GPU/Core rails for AMS

bug 1329929

Change-Id: I1974815d55255fab0c96f5f2343ddbde4b69c14a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/254940
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoregulator: as3722: add support for overcurrent configuration
Laxman Dewangan [Mon, 29 Jul 2013 09:07:48 +0000]
regulator: as3722: add support for overcurrent configuration

Add support for overcurrent configuration on as3722 PMIC.

bug 1329929

Change-Id: I777fa3a6616da027e2d742d22f99739c921293b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/254939
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: clock: add DC2 to iso usage table
Jihoon Bang [Wed, 10 Jul 2013 17:22:13 +0000]
ARM: tegra: clock: add DC2 to iso usage table

Consider DC1 and DC2 as separate iso client.
If DC1 and DC2 are on at the same time, use lower
iso efficiency as DC is on with other client.

Bug 1320063

Change-Id: Id2060339b50899a4507df0e6dee62648a3a9bd2f
Reviewed-on: http://git-master/r/247282
(cherry picked from commit e2fba905182737c73446f5d989b22cb5d886963a)
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/247251
(cherry picked from commit f6111cb1ab843c60a6265610d686deb6475b8f36)
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/254364
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: ardbeg: Corrected dsi_csi power rail sources
Mallikarjun Kasoju [Mon, 22 Jul 2013 15:34:46 +0000]
ARM: tegra: ardbeg: Corrected dsi_csi power rail sources

Bug 1325539

Change-Id: Ia7576485ba1b1041bf88fe1926600b8cc49cadea
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/253962
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agovideo: tegra: Control PLLP_OUT5 in gk20a driver
Kaz Fukuoka [Thu, 11 Jul 2013 18:33:23 +0000]
video: tegra: Control PLLP_OUT5 in gk20a driver

- In drivers/video/tegra/host/gk20a/gk20a.c,
PLLP_OUT5 is controlled as "pwr" clock.
(This part is already done by earlier changes.)

- Also in kernel/arch/arm/mach-tegra/common.c,
"pll_p_out5" is enabled in lower frequency.
This is necessary for gk20a.c driver to initialize registers,
before the "pwr" clock is enabled in gk20a.c

bug 1323688

Change-Id: Icb1c10562af3da5f60fe92a4a2b563d131df0c19
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/247978
(cherry picked from commit 50741c7f2011a4bf388836dff594266dce839960)
Reviewed-on: http://git-master/r/253661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo:tegra: fix cyclestats bugs
Kirill Artamonov [Wed, 10 Jul 2013 04:46:15 +0000]
video:tegra: fix cyclestats bugs

Free memory buffers allocated for cyclestats when channel is freed.
Fix format of callback buffers to match format used in userspace.
Fix names of callback operations.

bug 1154464
bug 1324403

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I0540275d180236b1bcc67013f542f359398ff907
Reviewed-on: http://git-master/r/252674
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>

6 years agoarm: configs: t124: add profiling configs
Donghan Ryu [Tue, 30 Jul 2013 11:35:53 +0000]
arm: configs: t124: add profiling configs

Enable PROFILING and OPROFILE

Bug 1325300

Change-Id: I35a8d791c5a1bfc9e52cd23d5d5c0d97398881be
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/255576
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: mc: Reduce code for debugfs node
Alex Waterman [Mon, 29 Jul 2013 20:49:30 +0000]
ARM: tegra: mc: Reduce code for debugfs node

Use the convenience macro for simple debugfs nodes instead of the long
complete definition for debugfs nodes.

Change-Id: I17ce8d53871a6dad88c24710cd9cf09259bed2bc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/255215
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agomedia: video: tegra: imx091: Auto detect support
Frank Chen [Thu, 20 Jun 2013 00:39:16 +0000]
media: video: tegra: imx091: Auto detect support

Read imx091 sensor ID during probe time. Sensor
ID will be used for sensor auto detection later.

Bug 1306878

Change-Id: I32da93266b6aa0c0ec2bffc7a5156c21083cb069
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/243657
(cherry picked from commit 854ff318b7ec483b81960b753440cf2cb7dc18ee)
Reviewed-on: http://git-master/r/254467
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra14: soctherm: fix handling cl-dvfs voltage range
Diwakar Tundlam [Sat, 27 Jul 2013 01:03:35 +0000]
ARM: tegra14: soctherm: fix handling cl-dvfs voltage range

Fixed check which was inverted. Also added check for possibility of
cpu-temp being lower than pll-temp, which causes unnaturally large
offset getting programmed resulting in spurious (huge) temperatures,
which will lead to sperious shutdowns.

Bug 1332999
Bug 1329597
Bug 832603

Change-Id: I3b720ae73e1816922f51c1431bcbca1760aa31d0
Reviewed-on: http://git-master/r/254639
(cherry picked from commit 290a2507b4247919776af8ffa76573dc37eb4e30)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/255205
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agodrivers: misc: therm_est: Fixed factory reset issue
Hyungwoo Yang [Wed, 10 Jul 2013 02:14:04 +0000]
drivers: misc: therm_est: Fixed factory reset issue

Thermal Estimator tries to access device no more usable during factory reset.

Bug 1320678

Change-Id: Ic56f550c029ad5b9d9a117ad79ccf5bd03292f86
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/246962
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit e06ae462d514f61f28d5fd7f82d927bbeb0c8607)
Reviewed-on: http://git-master/r/255172
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: thermal: change names of zone devices
Hyungwoo Yang [Mon, 13 May 2013 22:47:46 +0000]
ARM: tegra: thermal: change names of zone devices

Changed names of zone devices to be measuring device independent.

nct_ext -> Tdiode
nct_int -> Tboard

Bug 1261182

Change-Id: I11fda2288857142332c4c37c5505c23a95656480
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/247413
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit b178dcefa3c72d1927c390e3de4d8cd9d5aa8fee)
Reviewed-on: http://git-master/r/255159
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agomisc: nct1008: change names of zone devices
Hyungwoo Yang [Wed, 10 Jul 2013 21:19:36 +0000]
misc: nct1008: change names of zone devices

Changed names of zone devices this driver creates.
New names are based on where the device probe.

nct_ext -> Tdiode
nct_int -> Tboard

Bug 1261182

Change-Id: I147ae07992b3e0efa32671a47bb8c395faa24ff7
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/247344
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 74213e3e26148eb63c9f311a74206ba253e65ee6)
Reviewed-on: http://git-master/r/255157
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: dsi: Interleave dsi controllers ganged init
Animesh Kishore [Fri, 26 Jul 2013 14:21:51 +0000]
video: tegra: dsi: Interleave dsi controllers ganged init

With panels operating in ganged mode, initialization of both
DSI controllers happens one after the other sequentially.
Due to this some of panels are showing abnormal behaviour.

Enabling interleaved initialization of both dsi controllers.

Change-Id: I9de1f51fea4f7e930cad09e6258eb64b0514d4d7
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/254359
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agoARM: tegra14: soctherm: handle cl-dvfs voltage range notification
Diwakar Tundlam [Tue, 2 Jul 2013 21:18:15 +0000]
ARM: tegra14: soctherm: handle cl-dvfs voltage range notification

Adjust soctherm cpu zone configuration when CL-DVFS is crossing
boundary between high/low voltage ranges.

Bug 832603

Change-Id: Ic1bfbd5506dee496dc2c7308ab550ac5c7770429
Reviewed-on: http://git-master/r/246327
(cherry picked from commit 59daa04571e595b7b6d6a089091b9735f26708f3)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253753
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoarm: tegra: soctherm: fix heavy throttling on GPU zone
Diwakar Tundlam [Thu, 23 May 2013 21:57:46 +0000]
arm: tegra: soctherm: fix heavy throttling on GPU zone

Fixed initialization of GPU throttling config in board files

Bug 1169070

Change-Id: I43cc7edaa4adf5a3527ff16332b7755682fc5d74
Reviewed-on: http://git-master/r/239453
(cherry picked from commit 80605ae69b8f1f5a9a5b20e3a74384a18ab75f41)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253752
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoarm: tegra: EDP: Allow enforcing max-freq caps based on tables
Diwakar Tundlam [Mon, 3 Jun 2013 21:40:06 +0000]
arm: tegra: EDP: Allow enforcing max-freq caps based on tables

In addition solving for max-freq using leakage/dynamic formula, some
platforms require capping based on EDP tables published in the spec.
Adding support for this.

Added T114 fixed-capping table entries.

Bug 1281159

Change-Id: Ia159281db0ca72e74002b526b3b9e6f54b271646
Reviewed-on: http://git-master/r/239512
(cherry picked from commit d2ad4ba3de666f3fd299a8b95b1685e2f6da0d21)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253751

6 years agoarm: tegra: soctherm: show temperature log in debug output
Diwakar Tundlam [Fri, 21 Jun 2013 20:02:31 +0000]
arm: tegra: soctherm: show temperature log in debug output

Added new debugfs node to show temperature log with one-line summary
of temperatures of various TSOSCs with time-stamp.

The TSOSCs temperatures order is CPU0, CPU1, CPU2, CPU3, GPU, PLLx.

Also temporarily resume soctherm if it was suspended for the duration
of the debugfs call. Useful for logging purposes.

Bug 1165644

Change-Id: I695b7f8ab15fe9f5dcd2bc38b26c87a1938b3efb
Reviewed-on: http://git-master/r/241145
(cherry picked from commit b538aa0a38894dad2fe83a9decbe3c4702471438)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253750
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: update edp parameters init for t11x
Diwakar Tundlam [Mon, 10 Jun 2013 23:09:43 +0000]
arm: tegra: update edp parameters init for t11x

Updated leakage and dynamic parameters to compute EDP table fro T114
based on latest characterization data.

Bug 1304350

Change-Id: I503e7942c0f5c8bd401df086037694cba0e52bf6
Reviewed-on: http://git-master/r/241601
(cherry picked from commit f46bdb0f8a0b89e21cf1929a6eae354180141019)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253749
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: Tegra: Floor the calculated CPU leakage current
Diwakar Tundlam [Wed, 6 Mar 2013 21:08:08 +0000]
ARM: Tegra: Floor the calculated CPU leakage current

Also handle leakage calculation failure as an error in EDP-init

Bug 1251570

Change-Id: Ia5f0495f3019c54d1c56701f289618b82a100e05
Reviewed-on: http://git-master/r/239861
(cherry picked from commit 5ed581841d235cb2d0154002f457da668012d32e)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253748

6 years agoarm: tegra: EDP: Config to enable fixed EDP freq caps
Diwakar Tundlam [Wed, 5 Jun 2013 22:12:51 +0000]
arm: tegra: EDP: Config to enable fixed EDP freq caps

Added the config option for T11x. Default is disabled.

Bug 1281159

Change-Id: I7477e121f23304ca4234390906101e1829cb2803
Reviewed-on: http://git-master/r/239513
(cherry picked from commit e1975755f51bb86fcdd947c8550c4c235e3a1913)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253747
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoarm: tegra: refactor edp parameters init
Diwakar Tundlam [Sat, 8 Jun 2013 00:33:03 +0000]
arm: tegra: refactor edp parameters init

Move common numeric values to be macro-based to avoid duplicates

Bug 1304350

Change-Id: I470e135715a7226225b09213748783fc9dff70ae
Reviewed-on: http://git-master/r/239511
(cherry picked from commit 90326769802790cf2bac4ebdc8c6f307b0d1d1f5)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253746

6 years agoedp: tegra: table show support for T40DC
Diwakar Tundlam [Tue, 18 Jun 2013 00:38:42 +0000]
edp: tegra: table show support for T40DC

Bug 1300607

Change-Id: Iafaab450fd88a41b6384256ad2c6aaf2ebb9f360
Reviewed-on: http://git-master/r/239500
(cherry picked from commit fb715d4a3cb28547c274c648ecd43c87b33a1ec2)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253745
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: edp: table show support for T40DC
Diwakar Tundlam [Wed, 12 Jun 2013 23:52:31 +0000]
arm: tegra: edp: table show support for T40DC

Bug 1300607

Change-Id: I19a5381e3e68632f2f06deb7400a33419f320590
Reviewed-on: http://git-master/r/239497
(cherry picked from commit 4f484e2e0fdbdd5d1eeabdc4d39fa888dfd400d0)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253744

6 years agoarm: tegra: soctherm: Only error on improper FUSE_BASE
Diwakar Tundlam [Fri, 7 Jun 2013 23:22:17 +0000]
arm: tegra: soctherm: Only error on improper FUSE_BASE

FUSE_CALIB values can be zero and should not trigger init error.

Bug 1284859

Change-Id: I0a9b0dcaaf166adb2dba604e0ca5e430cfcecb1e
Reviewed-on: http://git-master/r/239457
(cherry picked from commit fc2ba2a5d235b67109eeae32aee9edf445c55dda)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/253743
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Anand Bhatia <anandb@nvidia.com>

6 years agomisc: nct1008: specify polling delay in plat struct
Diwakar Tundlam [Mon, 15 Jul 2013 23:25:43 +0000]
misc: nct1008: specify polling delay in plat struct

Bug 1315460

Change-Id: I6fa760a01103f34d9f2bc9551025cbaadadf4eb2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/250907
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoThermal: sys node to read and write polling_delay
Diwakar Tundlam [Mon, 15 Jul 2013 23:26:05 +0000]
Thermal: sys node to read and write polling_delay

Bug 1315460

Change-Id: I7dca29c63d5238522b1cd9df680dc7c019674066
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/250905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>

6 years agoARM: tegra: pcie: fix Coverity issue
Deepak Nibade [Mon, 13 May 2013 10:34:17 +0000]
ARM: tegra: pcie: fix Coverity issue

fix Coverity issue of reading from pointer after free
Coverity id : 23084

Bug 1046331
Bug 1329327

Change-Id: I17916ad2c0cfee828c50fe148927513a262a7c43
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/227923
(cherry picked from commit ebba5239ddcea9f9d4c94a4eaf68a9ac2468206c)
Reviewed-on: http://git-master/r/255377
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agovideo: tegra: gk20a: Fix GPCPLL VCO max
Kaz Fukuoka [Sat, 27 Jul 2013 00:35:57 +0000]
video: tegra: gk20a: Fix GPCPLL VCO max

- Fix VCO max (old=1700MHz, new=2000MHz).
- Because of this bug, 984MHz caused error.

Change-Id: Iebb1c1cb2da212244ef051ee758bc3965e3ab3c9
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/254617
(cherry picked from commit 22ba27f9545ef78e82384972c50a2720c54d77c0)
Reviewed-on: http://git-master/r/255256
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoarm: config: tegra12: Enable BCM43341 wifi driver
Nagarjuna Kristam [Mon, 29 Jul 2013 11:02:20 +0000]
arm: config: tegra12: Enable BCM43341 wifi driver

Bug 1310572

Change-Id: Ic099cec1b2ff810a5fa6fcdbd8e0789d41b823cd
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/254222
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoarm: config: tegra12: Actually enable SMMU
Robert Morell [Mon, 29 Jul 2013 21:22:17 +0000]
arm: config: tegra12: Actually enable SMMU

Commit ca1c4ca6fc enabled CONFIG_PLATFORM_ENABLE_IOMMU, but not
CONFIG_TEGRA_IOMMU_SMMU.

Signed-off-by: Robert Morell <rmorell@nvidia.com>
Change-Id: Ib9b6db7fa7fb1917095afe743a8ac928f1d6fdc2
Reviewed-on: http://git-master/r/255273
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoiommu: tegra: fix incorrect iova used during tlb/ptc flush
Krishna Reddy [Mon, 29 Jul 2013 21:56:24 +0000]
iommu: tegra: fix incorrect iova used during tlb/ptc flush

Change-Id: I13ed5d9c426e1b421283e0261fe397f79034e808
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/255236
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

6 years agoARM: tegra: thermal: Use exact_freq only if thermal_throttling is on
Diwakar Tundlam [Mon, 29 Jul 2013 20:10:54 +0000]
ARM: tegra: thermal: Use exact_freq only if thermal_throttling is on

EXACT_FREQ was forced ON in absence of THERMAL_THROTTLE prerequisite.
This breaks some kernel configurations such as MODS, which disable CPU
frequency scaling so TEGRA_THERMAL_THROTTLE is disabled. This is fixed.

Bug 1338672
Bug 1174096
Bug 1200111

Change-Id: I9571aa1295cd99a3ece75cbb823019e6352149b1
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/255200
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>

6 years agoARM: tegra: Fix throttle_count malfunction
Hyungwoo Yang [Wed, 3 Jul 2013 01:49:45 +0000]
ARM: tegra: Fix throttle_count malfunction

Bug 1288550

Change-Id: I4baba118331d579d1522a63b26ffeef3027cd28e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/244600
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 659b49aff7238b1d5c859940c4fa2f753d809912)
Reviewed-on: http://git-master/r/255175
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: laguna: Fix voltage range for ldo6 rail
Johnny Qiu [Wed, 10 Jul 2013 00:55:27 +0000]
ARM: tegra: laguna: Fix voltage range for ldo6 rail

ldo6 power rail min voltage should be 1.8V

Bug 1323354

Reviewed-on: http://git-master/r/246936
(cherry picked from commit 77ae8456c00701f150aad727ae90ff7709b367c8)
Change-Id: I44a30e7f81feb2aafd0d37915aebf1b5d92ce0d4
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/254851
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Shanker S <shs@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoarm: tegra14: bb: use mem_req_soon for emc dvfs
Vinayak Pane [Tue, 16 Jul 2013 00:33:29 +0000]
arm: tegra14: bb: use mem_req_soon for emc dvfs

Use mem_req_soon signal instead of mem_req signal to
remove EMC clock request. This prevent EMC drops for
short BB hibernate periods.

Bug 1323192

Change-Id: I6dc2e6a4069e5fcbfad0481860b8a9a691e3c0ab
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/249419
(cherry picked from commit a23b66a54bc335e426cebf2441ec8382b5b50e06)
Reviewed-on: http://git-master/r/254496
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoarm: tegra14: bbc: update core suspend about EMC rate
Vinayak Pane [Thu, 6 Jun 2013 23:07:11 +0000]
arm: tegra14: bbc: update core suspend about EMC rate

Inform LP1BB entry part about the current BBC emc floor and
the corresponding voltage required. These EMC parameters can
be used by LP1 entry low power routine to set optimal values
before entering in LP1BB hw state. The EMC parameter should
also be used by lp1bb exit routine to set the required EMC
frequency and voltage to minimize suspend-resume latency.

Bug 1270116
Bug 1301005

Change-Id: I1a979ae92fd4d579cd5ecc293f5c40203b440e4d
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/238239
(cherry picked from commit 6b083a4101c7d30dd14b391b2381ed91b938306f)
Reviewed-on: http://git-master/r/254495
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoarm: tegra14: bbc: prepare for lp1bb state
Vinayak Pane [Fri, 24 May 2013 23:54:16 +0000]
arm: tegra14: bbc: prepare for lp1bb state

There is window when BBC driver may not be aware of upcoming
paging event. During LP1BB suspend the EMC rate is used whatever
the system was using before suspend. That EMC rate may not be well
suited for BBC to operate in LP1BB state. Changing the emc clock
rate to set at the maximum floor for BBC. The LP1BB entry part
should reduce it down to the actual frequency floor.

Also for RPC request during LP1BB this new minimum floor gives a
safeguard against the resume time to raise EMC frequency.

Bug 1294872

Change-Id: I3b98cfac174f9dac12307923a1ef54c2c9430bad
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/238238
(cherry picked from commit 36a3bffaf90209f1a6b607a2a3bf581e9731ae49)
Reviewed-on: http://git-master/r/254494
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoarm: tegra14: bb: abort suspend when IPC is pending
Vinayak Pane [Wed, 12 Jun 2013 00:06:19 +0000]
arm: tegra14: bb: abort suspend when IPC is pending

If BBC has asserted IPC interrupt then abort the system
suspend. This is to reduce the wakeup latency for BBC
requests.
Also, add function to check for pending BB IPC interrupt.

Bug 1304608

Change-Id: Ie3766ab82c9e7f359cc9866dcf7ee163ab1aabc6
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/237796
(cherry picked from commit 7d65d264cae1810faa3e8193125a0da61da8dfce)
Reviewed-on: http://git-master/r/254492
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agovideo: tegra: host: fix gk20a rail gate/ungate sequence
Mayuresh Kulkarni [Fri, 12 Jul 2013 16:53:55 +0000]
video: tegra: host: fix gk20a rail gate/ungate sequence

bug 1324512

Change-Id: I6d95c5ae454be6e5a3c377a23fc0283d576aa016
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/253397
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: host: Use dma_map_sg()
Terje Bergstrom [Thu, 25 Jul 2013 05:08:14 +0000]
video: tegra: host: Use dma_map_sg()

Use dma_map_sg_attrs() for mapping in nvhost_memmgr.c. Also remove
touching sg fields. This causes dma_address to be set to only the first
chunk, so gk20a memory management code was adjusted to deal with that.

Also sets maximum dma chunk size to biggest possible number.

Bug 1325300

Change-Id: Icf76e01d6cc5464d98e5907cdefc40cc7ae59d14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/253308
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: host: Reimplement nvmap_pin in nvhost
Terje Bergstrom [Thu, 4 Apr 2013 12:31:50 +0000]
video: tegra: host: Reimplement nvmap_pin in nvhost

Reimplement mapping buffer to device memory in nvhost. This allows
separating memory areas of devices from each other.

Adds also dma parameters for each host1x device.

Bug 1259839
Bug 1174439

Change-Id: I0029756d84c455faacbbe27791e0e8f1190352ee
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/251931
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agodrivers: tegra: gk20a: Add debugfs node for load
Prashant Malani [Tue, 9 Jul 2013 00:30:54 +0000]
drivers: tegra: gk20a: Add debugfs node for load

Add a debugfs node to provide load measurements
for gk20a.
This uses counters in the PMU to measure the busy
and total cycles, and calculates load using this.

Bug 1320968

Change-Id: Id66d9002b49ec787d8dc957d19826a3433415bd0
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/250476
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra: move cpu-based timers out of timer.c
Peng Du [Tue, 16 Jul 2013 03:40:52 +0000]
ARM: tegra: move cpu-based timers out of timer.c

This change cleans up timer.c by pulling out cpu-based timers
(ie. arch & twd) into their own files. timer.c now hosts code
only for the Tegra SOC timers and common init code.

Also relocated deep power down (DPD) code from timer.c to pm.c
so that it can be shared by other chip family.

Change-Id: I247e514270e5a81a5eb1bde6d7f75692cbede1f0
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/250353
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

6 years agoarch: config: tegra enable support to debug clocks in mods config
Vivek Aseeja [Mon, 29 Jul 2013 18:04:56 +0000]
arch: config: tegra enable support to debug clocks in mods config

enable CONFIG_TEGRA_CLOCK_DEBUG_MODS support in mods defconfig

Change-Id: I781c090056075bb31732b033c96ecbe6d0ab13b9
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-on: http://git-master/r/255152
Reviewed-by: Lael Jones <lajones@nvidia.com>
Tested-by: Lael Jones <lajones@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra12: clock: Update PLLC2/3 lock timeout message
Kaz Fukuoka [Fri, 26 Jul 2013 00:27:16 +0000]
ARM: tegra12: clock: Update PLLC2/3 lock timeout message

Since PLLC2/3 lock bits may fluctuate after the lock with no adverse
functional effect, report timeout as debug (not error) print. At the
same time expand information in the message for detailed debugging.

bug 1325603
Ported from http://git-master/r/223688 (change for Tegra14)

Change-Id: I9147692e3773a56cd59c797301c7c66f911e396b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/253878
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra12: Change resistor value based on reworked/nonreowrked
Rohit Vijayaraghavan [Thu, 25 Jul 2013 22:45:11 +0000]
ARM: tegra12: Change resistor value based on reworked/nonreowrked

Identify whether a reworked board or not. Then set the respective
resistors accordingly and proceed.

Bug 1325536

Signed-off-by: Rohit Vijayaraghavan <rohitv@nvidia.com>
Change-Id: I243c2e78db01b0f78c49f3053d1e89c260f4e57b
Reviewed-on: http://git-master/r/253772
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>

6 years agotlk_driver: use dma_alloc_coherent for uncached mem
Chris Johnson [Tue, 23 Jul 2013 18:20:34 +0000]
tlk_driver: use dma_alloc_coherent for uncached mem

Instead of relying on change page attribute calls, instead use DMA
routines to get uncached mem. This will go away in the near future
when we can map these buffers directly in the kernel.

Change-Id: I6a375f2b1b09f987deae8a61e0907209b90c870e
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/252523
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aaron Gamble <jgamble@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

6 years agosecurity: tlk_driver: return failure for IOCTL_FILE_NEW_REQ during suspend
Varun Wadekar [Tue, 2 Jul 2013 07:26:15 +0000]
security: tlk_driver: return failure for IOCTL_FILE_NEW_REQ during suspend

The user space daemon will retry 3 times whenever it receives errors for new
requests.

Bug 1314244

Change-Id: I57f1740d7b24d2f3f3f97e7e83a5434f54d05bdb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/244187
(cherry picked from commit 639efa238a01be8fd9debf4c8511c9eac942fc46)
Reviewed-on: http://git-master/r/249874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>

6 years agosecurity: tlk_driver: use local stack for context save/restore
Varun Wadekar [Tue, 25 Jun 2013 05:42:35 +0000]
security: tlk_driver: use local stack for context save/restore

With secure storage there is a situation when we getback from the SMC call,
but find that the stack is completely corrupted due to SVC handling in the
kernel. To avoid such scenarios, use a local stack to save/restore our context.

Bug 1291402

Change-Id: If7d4c336aa0cc664b7c7f7134becb68d03e22ece
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/241681
(cherry picked from commit 4fb8a5f59ce565cb684d9aaa816a465d7c3a5d04)
Reviewed-on: http://git-master/r/249872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Aaron Gamble <jgamble@nvidia.com>