5 years agoARM: tegra11x: CPUID virtualization support
Bo Yan [Sat, 13 Oct 2012 21:09:52 +0000]
ARM: tegra11x: CPUID virtualization support

This is the first patch to support CPUID virtualization. The goal is
to treat all CPUs as equal in software. In current implementation,
CPU0 is the anchor CPU, which must be the first one brought up, and
the last one taken down. This patch removes that restriction.

the cluster switch still has to start from CPU0 with this patch.

This can not coexist with secure OS

Reviewed-on: http://git-master/r/144610
(cherry picked from commit d32fba4be39e3f9a95ef5ab44d0c64dc6d2808a3)

Change-Id: Ib7fcaae751d17fee839a4f228f5ef5c3ee2390c2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/159486
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R09e29d45acf92b3ad2d909d5438c3375aa85e7dd

5 years agoARM: tegra: dalmore: add kbc interrupt for e1611
Ray Poudrier [Tue, 18 Sep 2012 23:33:47 +0000]
ARM: tegra: dalmore: add kbc interrupt for e1611

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Change-Id: I6bfc634b792170a81351f849d1eb9dd55572285b
Reviewed-on: http://git-master/r/133687
(cherry picked from commit 9f2f20d2fd40556c48644490d934d6841794fcef)
Reviewed-on: http://git-master/r/159483
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R929f948bb7634191ecec2d210527f3762e3577ec

5 years agoarm: tegra: usb: disable the mem-alignment WAR
Suresh Mangipudi [Thu, 27 Sep 2012 19:02:01 +0000]
arm: tegra: usb: disable the mem-alignment WAR

The mem-alignment issue is causing the modems not to
send/recieve packets properly.

Reviewed-on: http://git-master/r/139433
(cherry picked from commit a21561953fb81c238150fc88918458d4e4041443)

Change-Id: I327608ecbee1ed5fb005de044ec096c42149ef63
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/159480
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Ra3d054da9587b3438bfe1b56ce250bc51ea6770b

5 years agoasoc: tegra: cs42173: Fix to update clock variable
Dara Ramesh [Fri, 19 Oct 2012 06:56:41 +0000]
asoc: tegra: cs42173: Fix to update clock variable

Change-Id: I533e7c360e039fdfec277029d67b3da99d5f70b2
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on:  http://git-master/r/145866
(cherry picked from commit 06ba007018b63b6ffa97ee96536946791b9fef54)
Reviewed-on: http://git-master/r/159444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit

Rebase-Id: Rcb24d20343c9a7e45305c25ac633efcce2081ee7

5 years agoARM: tegra: replace tegra_cpu_wfi with cpu_do_idle
Bo Yan [Fri, 26 Oct 2012 16:33:53 +0000]
ARM: tegra: replace tegra_cpu_wfi with cpu_do_idle

Function "cpu_do_idle" is defined in ARM common code, there is no need
for "tegra_cpu_wfi" which has the identical implementation.

Change-Id: I8ca3ada171990148162276a76434aebd2bd188e2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/159157
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rd6a6fc2bab5af491f65b018cc4bd4cecfdd2b60b

5 years agoARM: mm: rename jump labels in v7_flush_dcache_all function
Lorenzo Pieralisi [Tue, 18 Sep 2012 15:29:44 +0000]
ARM: mm: rename jump labels in v7_flush_dcache_all function

This patch renames jump labels in v7_flush_dcache_all in order to define
a specific flush cache levels entry point.

Change-Id: If84ff442617cec67419dbc75fe1c6daa153ce537
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-on: http://git-master/r/147782
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rba4651e2fc3dec256e8f1453ac280e93235b8908

5 years agoARM: tegra: pluto/dalmore: power sequence updates
Charlie Huang [Tue, 9 Oct 2012 01:12:30 +0000]
ARM: tegra: pluto/dalmore: power sequence updates

use pinmux enable/disable ALT funtion to enable/disable MCLK/PBB0 sensor
mclk output.

modify imx091/imx132/ov9772 power on/off sequences according to their specs.

enable the AF regulator whenever a sensor is on (rear/front) as a workaround,
as this is required by the focuser ad5816 in the rear sensor module.

put gpio initialization into lateinit stage.

update the both dalmore/pluto board power files to adapt with the
sensor/focuser/flash kernel drivers.

bug 1060778
bug 1059684
bug 1054873

Change-Id: If67c1ad1d4ff15e04446f6d93dc75d07cda97052
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/147648
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R8459a4b199f526f509d15e23f5d6be93361f79f7

5 years agovideo: tegra: nvavp: Powergate VDE
Jaiprakash Khemkar [Tue, 16 Oct 2012 09:03:03 +0000]
video: tegra: nvavp: Powergate VDE

Bug 1059487

Change-Id: I55f51064070888007be6978b7317288bf5dc6c31
Signed-off-by: Jaiprakash Khemkar <jkhemkar@nvidia.com>
Reviewed-on: http://git-master/r/147483
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com>
Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-by: Vinayak Pore <vpore@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>

Rebase-Id: Rb5479bbb819d223310f1b0d325cab466fe7698f1

5 years agoARM: tegra: restructure cpuidle utility functions
Bo Yan [Thu, 25 Oct 2012 00:46:05 +0000]
ARM: tegra: restructure cpuidle utility functions

As more and more chips are supported, the conditional compilation
flags in cpuidle.h also grows, this is becoming unwieldy and
cumbersome. Let each chip register its own set of functions can
alleviate this problem.

Change-Id: I033d7aeb7a46869783a5c78058869920d81d070b
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/147420
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R1a350795453ebdbebad3f61a7f24e7f6a9eb4180

5 years agoarm: tegra: Removing an unused-var warning
Nitin Agrawal [Mon, 29 Oct 2012 09:14:58 +0000]
arm: tegra: Removing an unused-var warning

Variable "once" not defined within CONFIG_TEGRA_THERMAL_THROTTLE

Bug 1051967

Change-Id: I1bbe0ff661aea283f84c77ea511df1448f243d55
Signed-off-by: Nitin Agrawal <nitina@nvidia.com>
Reviewed-on: http://git-master/r/159496
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rfffc3e2523046c2a4cf4cf7d878a7b37b0a5aa2d

5 years agoARM: tegra11: clock: Combine DFLL usage controls
Alex Frid [Wed, 24 Oct 2012 02:50:05 +0000]
ARM: tegra11: clock: Combine DFLL usage controls

Replaced 2 boolean DFLL usage controls: use_dfll and use_pll_cpu_low
with one integer use_dfll parameter. Integrated this common control
into dfll.data structure as the following enumeration:

0 = DFLL_RANGE_NONE - DFLL is not used as CPU clock source

1 = DFLL_RANGE_ALL_RATES - DFLL is used as CPU clock source at all
rates

2 = DFLL_RANGE_HIGH_RATES - DFLL is used as CPU clock source at high
rates above use_dfll_rate_min, CPU source is automatically switched
from DFLL to PLL when use_dfll_rate_min threshold is crossed down,
and from PLL to DFLL when it is crossed upwards. In the latter case
do not clip target rate to pll mode maximum even though the switch
starts while CPU is on PLL.

Change-Id: Ide963e614d9b67f30872ec040f78d7dfab6d485a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147351
(cherry picked from commit 78733e5984ac08ed3667414dd3a770eb4f306a67)
Reviewed-on: http://git-master/r/159412
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R562147ded1e746829377c65e5457587947a8baff

5 years agoARM: tegra: clock: Keep CPU voltage above DFLL Vmin
Alex Frid [Tue, 23 Oct 2012 02:48:38 +0000]
ARM: tegra: clock: Keep CPU voltage above DFLL Vmin

Updated DFLL On/Off procedures to keep CPU voltage above DFLL Vmin
during transition. This change is necessary now, as it is no longer
true that dvfs voltage in pll mode is above dfll mode voltage at all
rates.

Change-Id: I2bdc42998c745e06b8fa5b32395cf7b26c0bc1b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147350
(cherry picked from commit 024210cfa6dd6173fe4edc4f0ed722a89ea370ce)
Reviewed-on: http://git-master/r/159411
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R9a7fcb7aa118ecc8bf51cf36836ac891bab25113

5 years agoARM: Tegra: Dalmore: Release PWM GPIO
Matt Wagner [Tue, 16 Oct 2012 01:53:22 +0000]
ARM: Tegra: Dalmore: Release PWM GPIO

Release PWM GPIO to allow the backlight pwm to function.

Bug 1159286

Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/144726
(cherry picked from commit eb2b2ec319aa18ec877b776f50b6429e9ddec97a)

Change-Id: I6d14007a41511d7605ca851188e12b6f69f327bd
Signed-off-by: naveenk <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147932
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R7349eeb742202308f056dc18457e5b5deeac0720

5 years agoarm: tegra: pluto: Fix the configuration for GMI_AD9
Kerwin Wan [Thu, 11 Oct 2012 21:48:37 +0000]
arm: tegra: pluto: Fix the configuration for GMI_AD9

GMI_AD9 is used as PWM1 not as a gpio for pluto with 4.7'' panel.

Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/143844
(cherry picked from commit f6bdfbc56d63bc79ed964e0146387bfa563dc94b)

Change-Id: I710e27f412fb7daa7d2a7bc73d3b248066098dfb
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147914
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R59964e6f79b06172b4227fdf47ad7a0fc9c7446a

5 years agoarm: tegra: pluto: Add support for Varuna
Gaurav Batra [Tue, 16 Oct 2012 01:06:27 +0000]
arm: tegra: pluto: Add support for Varuna

Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/144712
(cherry picked from commit 7f8d4fe2fb1d57c52de427bcdb684292014a8de8)

Change-Id: I85c627260d52a53bd14774d638e3168ca01a0417
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147883
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R09c8bbdb3173b9c2aa3111990c0ed8992476bd7a

5 years agoARM: tegra: usb: Remove WAR during resume
Vinod Atyam [Thu, 25 Oct 2012 07:01:19 +0000]
ARM: tegra: usb: Remove WAR during resume

Removing the WAR kept in T30
during resume code as it is not
needed for T114.

Change-Id: I73c8c7de3cca4af0ee7e0a36adb4d44c8693314a
Signed-off-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-on: http://git-master/r/147466
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R0f22dc238d8aed815d1af39a225a0fc968a68f44

5 years agoarm: tegra: pluto: remove clk_32k of blink
Johnny Qiu [Sat, 29 Sep 2012 03:02:30 +0000]
arm: tegra: pluto: remove clk_32k of blink

CLK_32K_OUT is input for VDD_CPU OC detect. It connects to
function mux SOC not BLINK. So it's not necessary to enable
clk_32k for it.

bug 1053368

Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/139911
(cherry picked from commit 5872d8a4df42389e3c8bdc28bf9813a9e798c837)

Change-Id: I444fb32e180796d980f319ec9ee8d0b61caac6d5
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147896
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

Rebase-Id: R822e78f658a7c09c42ce63f2c97e80f21cc4c9ee

5 years agoarm: tegra: pluto: set corereq polarity to active-high
Johnny Qiu [Fri, 21 Sep 2012 23:23:24 +0000]
arm: tegra: pluto: set corereq polarity to active-high

Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/134517
(cherry picked from commit 759633475b4eb02c56df4640c5df42898359f5e3)

Change-Id: I4b399a698f3b60ac9c3dc42ea26559bbb15ec4a1
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147894
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

Rebase-Id: Rf3a2b54b6e205ad9e2bc426ba89eb970373c765a

5 years agoARM: tegra: clocks: Lower EMC min frequency to 12.75MHz
Daniel Solomon [Sun, 30 Sep 2012 21:34:34 +0000]
ARM: tegra: clocks: Lower EMC min frequency to 12.75MHz

Lower EMC minimum frequency to 12.75MHz.

Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/143393
(cherry picked from commit 01a4ca3c4d8ed2ac83bb51b86e2f4c8d970336ff)

Change-Id: Iad94ec701e179eff4277e31f4fbed931860757c9
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/147881
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

Rebase-Id: Rd2a91739803bf8104a985147367509238adb7e7e

5 years agonet: usb: smsc: Enable VOH mode for SMSC ethernet compliance
Vishal Singh [Fri, 5 Oct 2012 11:05:22 +0000]
net: usb: smsc: Enable VOH mode for SMSC ethernet compliance

Adding config option that enables the VOH mode which is required
for SMSC compliance.

Bug 923110.
Bug 1045637.

Reviewed-on: http://git-master/r/73477

Reviewed-on: http://git-master/r/141562
(cherry picked from commit 4ab7f0342d1e17c4b19a69dc34e7cb6fd6332433)

Change-Id: Ifb1660272b36719abf6edd449193ceffea227511
Signed-off-by: Vishal Singh <vissingh@nvidia.com>
Reviewed-on: http://git-master/r/144089
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: Rffdfd0787b45c147c722089310df64af7e2377c8

5 years agoarm: tegra: Enable CPA for tegra11
Krishna Reddy [Tue, 9 Oct 2012 17:07:08 +0000]
arm: tegra: Enable CPA for tegra11

Change-Id: I4767ccd079810cdfbc2602317f884d1c89f36e7f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/142584
(cherry picked from commit a1ccaa5d11d9b71a722841faf1e62e18e5566b00)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/145378
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

Rebase-Id: Rb63ef9c1928b71ffd3b9fca97a968d9a0fc3fd8b

5 years agoarm: tegra: power: ignore duplicate reg_override values
Diwakar Tundlam [Wed, 17 Oct 2012 21:11:27 +0000]
arm: tegra: power: ignore duplicate reg_override values

and some clean ups

Change-Id: Ic5c239cea8921ae4b5639dd8439c569fa89cb1ec
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/159375
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Ra59d8e3a57782ac1f830243b94827aa1ff34a238

5 years agoarm: tegra: t11x: Changes for LP1
Seshendra Gadagottu [Thu, 18 Oct 2012 23:03:23 +0000]
arm: tegra: t11x: Changes for LP1

Bug 1053092

Change-Id: I6823c96677cf8d20878ea886bea51658132de2b3
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/141367
(cherry picked from commit 3355e38667dab60b801f5704ce77a28506798786)
Reviewed-on: http://git-master/r/159363
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

Rebase-Id: R8a6fd51cdf86de9d40a01c3fd0dd44c3099c1764

5 years agoARM: Tegra: Dalmore: Add Hall Effect Sensor
Matt Wagner [Wed, 10 Oct 2012 00:17:26 +0000]
ARM: Tegra: Dalmore: Add Hall Effect Sensor

Set up gpio-key wakeup with the Hall Effect sensor to be SW_LID
to enable lid open and close logic

Bug 1156171

Change-Id: I6334351b8caed1bf1cddc8525a3f2fa4a5641a7a
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/142805
(cherry picked from commit d6875d355ada98bcaf1785bd6e6f9afcc6890346)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/159360
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

Rebase-Id: R6b77e3185d0753f825105af9b4bc1774ba2dcc90

5 years agoARM: Tegra: XUSB: Add stubs for xusb_init calls
Krishna Monian [Thu, 11 Oct 2012 14:27:31 +0000]
ARM: Tegra: XUSB: Add stubs for xusb_init calls

- Fixes builds without USB support

Change-Id: I8b4e8b203a9a921df5faed489d05139e09ac9f8d
Signed-off-by: Krishna Monian <kmonian@nvidia.com>
Reviewed-on: http://git-master/r/143735
(cherry picked from commit 6fdd6c2c056062183529215da5de48c107c8f139)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/159359
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

Rebase-Id: R208774ca21472055c69bc14995f84e75a8a5e316

5 years agoarm: tegra: dalmore: enable headphone detect gpio
Jubeom Kim [Sun, 23 Sep 2012 04:01:47 +0000]
arm: tegra: dalmore: enable headphone detect gpio

Change-Id: Ic09ef69bdb53e219c1e73ab9aead7a80a7afd394
Signed-off-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-on: http://git-master/r/134646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
(cherry picked from commit 282ceed80d3b9f8b20bc94094453d55efd6c35eb)

Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Change-Id: I0088bc46ff07b64ac46294657ee2af90d61a03ce
Reviewed-on: http://git-master/r/159130
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R12da80159687b6fa9e677fd68bc0f005da3ff0f6

5 years agoARM: tegra11: dvfs: Update CPU DVFS tables
Alex Frid [Sat, 20 Oct 2012 02:38:01 +0000]
ARM: tegra11: dvfs: Update CPU DVFS tables

Updated new cvb coefficients, dfll tuning parameters, maximum
voltage to 1.25V.

Bug 1161126

Change-Id: Id720736dbb91261ad0fe3823ab22d6702aaae37d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/146109
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 351020d6e0a8b90faf60cd96a9f2d66bb48025fb)
Reviewed-on: http://git-master/r/147751
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb637692bdf21d68450eb79a50c1bed87c8193756

5 years agoARM: tegra11: clock: Fix cpufreq table construction
Alex Frid [Sat, 20 Oct 2012 07:53:23 +0000]
ARM: tegra11: clock: Fix cpufreq table construction

Fixed cpufreq table construction in case of overlapping LP and G CPU
frequency ranges: made sure minimum G CPU rate is inserted into the
table once (was inserted before each LP CPU frequency that exceeds
G CPU minimum).

Change-Id: I44a8d53ce40e51f99865fb0cee3d073b1eff0bee
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/146134
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit 5caf5eaff268b6f55ef5361b508d84c5ef6b862f)
Reviewed-on: http://git-master/r/147750
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rd572886e29660b8c6603816c22d5f64aab22d407

5 years agoARM: tegra11: dvfs: Use dfll below Fmax@Vmin
Alex Frid [Thu, 18 Oct 2012 04:39:54 +0000]
ARM: tegra11: dvfs: Use dfll below Fmax@Vmin

When CPU clock source switch from DFLL to PLL at low rate is enabled,
don't exit DFLL mode unconditionally for rates below Fmax@Vmin. If
required PLL voltage is above Vmin, stay on DFLL (and engage output
skipper to reach target rate).

Change-Id: I96d17adafcc9c282c659b25ac446efac0ac0fdb0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145843
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 1505458c08feabc60c2806c2f45ebdde62885b39)
Reviewed-on: http://git-master/r/147749
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Ra9e7ea8626cf763495b5deec3b365a575b182689

5 years agoARM: tegra: dalmore/pluto: sensor: enable flash
Charlie Huang [Sun, 16 Sep 2012 22:02:06 +0000]
ARM: tegra: dalmore/pluto: sensor: enable flash

Added AS3648 support in board-dalmore-sensors.c along with its
platform data.

Also added the power rail names for as3648 in the power rail table.
Modified the pinmux table by setting PBB4 to VGP4.

Enabled max77665 device in board-pluto-sensors.c, updated max77665-flash
platform data.

On pluto, modified GPIO_PBB3 mux setting to enable VGP3 output. Set
max77665 flash trigger-by-torch setting, so flash can be triggered
without board rework. At the mean time, the flash-over-camera is still
reserved.

bug 1048411
bug 1035551

Change-Id: Ie378c5b528ee9efc1c81dd2617baaa80a48756e0
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 8e7c01d3e297eada59fe32c9c7ad3810a17d3a39)
Reviewed on: http://git-master/r/#change,133126
(cherry picked from commit d3b940690c230c1c515533bd98bed67b76b0e580)
Reviewed on: http://git-master/r/#change,139122
(cherry picked from commit 27ff846a68dee8936820d48d50f71e4833a8b6ef)
Reviewed on: http://git-master/r/#change,139962
Reviewed-on: http://git-master/r/147073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R7ef2cd2d6b7a7875528b7f41e06675514bb924e3

5 years agoarm: tegra: pluto: configure SPDIF_OUT signal to high
Syed Rafiuddin [Tue, 23 Oct 2012 09:25:49 +0000]
arm: tegra: pluto: configure SPDIF_OUT signal to high

Configure SPDIF_OUT signal to high to detect the
bq20z45 chipset on dalmore platform

Change-Id: I7a9c1640f3caebc3989dc95a9a3a0d8854b36e18
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/146826
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb79ec65f4dd50ba03751917d7c86e4ef70231df9

5 years agoARM: tegra: USB: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 06:48:21 +0000]
ARM: tegra: USB: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I8ac12f89fd5aaf9f49b0a873bb921ed17f3c33ac
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146782
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rcca5eebdc163efe896090c27dc3346d3e31487a5

5 years agoarm: tegra: Add client error counters
Alex Waterman [Wed, 17 Oct 2012 20:50:54 +0000]
arm: tegra: Add client error counters

Add counters for each client that track the number of each type
of MC error the client generates. See the debugfs node:

    /d/mc/mcerr

BUG 1066896

Change-Id: Ibb1c28215346e0b4ee691a4c2e06778f13da0fb5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/145775
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd0ebf114313f6ddd7083a46d4aaf66c2963c9f0b

5 years agopluto: set smps6 to 1.1V by default
Neil Patel [Tue, 16 Oct 2012 00:16:32 +0000]
pluto: set smps6 to 1.1V by default

To be used until Modem DVFS support is ready.

Bug 1040101

Signed-off-by: Neil Patel <neilp@nvidia.com>
Change-Id: Ia93c3c596eedb83a3fc7990ae028bb104f118bce
Reviewed-on: http://git-master/r/143326
(cherry picked from commit ab390b196ca095831f1c2e6bdac0beb2d2ed081e)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159144
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rba9cd4a6495c2dccf6cfbfa5707a57cbb1c21af7

5 years agoarm: tegra: pluto: enable wakeup0/32 for T11x
Neil Patel [Tue, 25 Sep 2012 23:42:37 +0000]
arm: tegra: pluto: enable wakeup0/32 for T11x

Wakeup sources are used for Pluto onboard modem

Bug 1040101

Change-Id: I7b3b81ae4e01af8c3098c515d1189a444e9cbeca
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/138763
(cherry picked from commit de2889693758f20e3dbf6155b12b75d19380ec0a)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

Rebase-Id: R70c30ce15d2c713f2ec5d335574bd2d3420b2962

5 years agoarm: tegra: t11x: cpu rail power good timer
Seshendra Gadagottu [Fri, 12 Oct 2012 19:07:06 +0000]
arm: tegra: t11x: cpu rail power good timer

TPS65913 PMU spec says power good value for rail
powerup is  175us(typical) 225us(max). Considering
other board factors, changing cpu rail power good
value as 300us from 200us.

Bug 1056598
Bug 1053092

Change-Id: I1df27eff75dee6bebd0cb294cc8ffa1582a5e884
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/144138
(cherry picked from commit b101fa6865be10db406adb57a398762634feed11)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159137
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R6498436237a764d688e9b67d781fe326c41671ca

5 years agoarm: tegra: t11x: cpu rail power good timer
Seshendra Gadagottu [Thu, 11 Oct 2012 23:08:56 +0000]
arm: tegra: t11x: cpu rail power good timer

From the HW team experiments, maximum CPU rail ram-up time is
175us. So updated core rail power good timer as 200us for
pluto/dalmore platforms.

Bug 1056598
Bug 1053092

Change-Id: Ia6815227bccf64eb3d10df2df6c506a27a03e8bb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/143874
(cherry picked from commit 810698740caeb1a802198ae908e290496cb15828)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R63728dde00aa5993e351a2c6a52ecc332857d28f

5 years agoARM: tegra11x: Do not enable CPUPWRGOOD_EN
Seshendra Gadagottu [Sat, 29 Sep 2012 00:13:44 +0000]
ARM: tegra11x: Do not enable CPUPWRGOOD_EN

In T114 A01 HW, CPUPWRGOOD_EN feature is not enabled.
Enabling this feature in SW causing problems with
cluster switch after LP0.

Bug 1051517

Change-Id: Ie3195dce2068f1ccc5b7f951e45e38fda7cae20d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/139861
(cherry picked from commit 1f03be4d77f3b715d97073c9269c6ad28c914da8)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159133
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R120f687ea07cd3ee8304865461f14606d2c74b9c

5 years agoRevert "ARM: tegra: t114: Pinmux LP0 entry/exit sequence"
Seshendra Gadagottu [Sun, 23 Sep 2012 19:35:46 +0000]
Revert "ARM: tegra: t114: Pinmux LP0 entry/exit sequence"

This reverts commit 1ed7829f840fd2b94b37724ec98dd0a9a7456990.

Change-Id: Ib905af92e290dcaadc290df7b640c79f8e6b33dc
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/134658
(cherry picked from commit adcaf4480b0963de154d27d63bfe5a77add7ab43)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159132
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R4e9dc5761d2d78438e83c801d45d8170c481fa8e

5 years agoARM: tegra: Pluto: add backlight regulator
Xin Xie [Sun, 30 Sep 2012 21:22:02 +0000]
ARM: tegra: Pluto: add backlight regulator

Change-Id: I6f0427dce70a44033427ade2b713bff6b1f4aea3
Signed-off-by: Xin Xie <xxie@nvidia.com>
Reviewed-on: http://git-master/r/140021
(cherry picked from commit 6abc48eb4d5db6e6727e3a41b3a5967b3c005401)
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159131
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3cfb2f22d06daf224e381fd852fd4aa0478d80d7

5 years agoARM: tegra: configs: validate l4t on t114
Jong Kim [Thu, 27 Sep 2012 21:04:13 +0000]
ARM: tegra: configs: validate l4t on t114

Validate l4t on t114 by adapting options from tegra11_android_defconfig.

Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/139458
(cherry picked from commit 256da49026d97bfa0bc29bf8cdd1a2665874bac9)

Change-Id: I8c8f92e60200522d9c54e442cb9b07c9e0ed785c
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/147900
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: R79a71a5f4eefbc49e29f6053d66670d8761c0a28

5 years agoarm: linux: WAR for spurious ARBITRATION_EMEM intr
Alex Waterman [Thu, 25 Oct 2012 19:21:53 +0000]
arm: linux: WAR for spurious ARBITRATION_EMEM intr

Fix a race condition in the MC interrupt handler that was
causing a lot more spurious interrutps to fire than otherwise
necessary.

Change-Id: I619304959f9cb2a5ace71f4767ca5b3e643d7091
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/147672
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R0b0430f987bdeca8f25379061e8b116de20a8c94

5 years agoasoc:tegra: disable ext1 and enable codec bias off
Dara Ramesh [Tue, 16 Oct 2012 09:47:05 +0000]
asoc:tegra: disable ext1 and enable codec bias off

a) disable extern1 clock during OSIdle and suspend
b) enable codec idle bias off

Bug 1158489
Bug 1052069
Bug 1054060

Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/144820
(cherry picked from commit 777bbde281ede62a847c3eeb3252957c0a5ee99c)

Change-Id: I8102ece58ca2d208e38fcf2dc72320dfb5d030a1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/146966
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Re183a030d6ff807cf9b092338b9a46b13ea3f6cb

5 years agoasoc: tegra: cs42l73: Support voice call
ScottPeterson [Fri, 28 Sep 2012 21:36:50 +0000]
asoc: tegra: cs42l73: Support voice call

Add support for voice calls on pluto platform.

Bug 1056501

Signed-off-by: ScottPeterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/139823
(cherry picked from commit 9a18bc54326a603b46bd15f500a08b6149f6b70c)

Change-Id: I100497338b9cdb7ec66627151e4c7e7840f059fa
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/146965
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R9cc8b2953610cd4eeb239890be3e7d404bd00652

5 years agoasoc: tegra: cs42l73: slave mode support
Rahul Mittal [Thu, 11 Oct 2012 06:52:23 +0000]
asoc: tegra: cs42l73: slave mode support

I2S changed to slave mode
Add Schmidt trigger enable for DAP2
Add devid and conid for sync clock lookup
Configured DAP direction to INPUT
Audience configured for PORTA -> PORTC passthrough

Bug 1062554

Change-Id: I9e7cc40e4ce4e165685d9081242f181d5bd5d6d8
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/141123
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit f329532f3b76a276c2f1219ff6422510b5a8ed9d)
Reviewed-on: http://git-master/r/147928
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rbaf64f3b6a710c637a342d148240cf594892976e

5 years agoARM: tegra: dalmore: add nfc support
Rakesh Goyal [Thu, 20 Sep 2012 13:36:37 +0000]
ARM: tegra: dalmore: add nfc support

add nfc_board_info and register with i2c

Bug 982624

Reviewed-on: http://git-master/r/134087
(cherry picked from commit 2cd5f9247ed47f492d1de42a39429427f088be5e)

Change-Id: I48d18bafc38a38559a996c008f53a7d7af8efdf9
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/147858
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf944fbaab4901e692261d06324e5866a84c5f6e5

5 years agoarm: tegra: dalmore: add userspace regulator consumer for gps
Nagarjuna Kristam [Wed, 26 Sep 2012 07:47:14 +0000]
arm: tegra: dalmore: add userspace regulator consumer for gps

Bug 982624

Change-Id: I0927d4cb91c2cc5c347d8e9b0c405a8268397a6e
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
(cherry picked from commit 798601b66944ee712302acff3c1db0b5bb82b597)
Reviewed-on: http://git-master/r/147826
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R0535356a7b940f31b805f3c0e9d276d067533420

5 years agoARM: tegra: pluto: increase dsi max frequency
Rakesh Iyer [Thu, 27 Sep 2012 22:20:03 +0000]
ARM: tegra: pluto: increase dsi max frequency

Increase dsi maximum frequency to 500Mhz.

Change-Id: I0739f434122541335bfd141c8949154daea7bfaf
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/139474
(cherry picked from commit 5fa0c69175a1a4ebb81d5686d5b0c4e4b883726f)
Reviewed-on: http://git-master/r/147613
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R69c680b1d28932ab128451d1f1fe4cb130237571

5 years agoarm: tegra: Enable cpu power gate, rail gate during LP1
Krishna Reddy [Wed, 26 Sep 2012 00:28:20 +0000]
arm: tegra: Enable cpu power gate, rail gate during LP1

Change-Id: I1d72d354e5a83d0355ada65dcda01d842bc8b592
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/138760
(cherry picked from commit bb0dea85a32905e5c3f29c94bdb2ed3d2a164db8)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147609
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf30183321c8553141220afe4326cb0e4869cf148

5 years agoarm: tegra: dalmore: update ddc pinmux
Ray Poudrier [Fri, 21 Sep 2012 09:02:31 +0000]
arm: tegra: dalmore: update ddc pinmux

Bug 1052024

Reviewed-on: http://git-master/r/134326
(cherry picked from commit ce3e29f56c28fdcb1e831820263257a5d7e5c64e)

Change-Id: Ibc7b65e7945cbcd4bb57b73a5e53404dcc0c8b05
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/147592
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R42434c9aee17d1cfb6a11c31b2ec850edb83cc4d

5 years agoARM: tegra: pinmux: add rcv_sel functionality
Ray Poudrier [Fri, 21 Sep 2012 08:48:23 +0000]
ARM: tegra: pinmux: add rcv_sel functionality

Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH

Bug 1052024

Reviewed-on: http://git-master/r/134325
(cherry picked from commit 572bb757c9c7d867b92531d2fb8428f819e2a586)

Change-Id: I164311ddcf16dea31df9c04a0c33ca08537b5d22
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/147530
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R4e5f91ba548172c1a1e7af3bfd74aad77b15fb31

5 years agoARM: Tegra: Add RCV_SEL pinconf param define
Graziano Misuraca [Sat, 22 Sep 2012 22:06:38 +0000]
ARM: Tegra: Add RCV_SEL pinconf param define

Reviewed-on: http://git-master/r/134619
(cherry picked from commit c6e65a71e4b42e5f46d1eb972d6174d9da546ce7)

Change-Id: I4c11f17a87f43e52758a4b64cea4498b87c8afb8
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/147525
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rb0447dce0ddafc455eb9ae26dd13ba444cd8cfc8

5 years agodc: mach-tegra: pass sd settings bl_device_name
Mitch Luban [Sat, 13 Oct 2012 00:09:49 +0000]
dc: mach-tegra: pass sd settings bl_device_name

We can't always pass the backlight device directly to
nvsd. This change gives the backlight device name
to nvsd (which is known at build time) and then at
runtime can lookup the backlight device.

Bug 1047558

Reviewed-on: http://git-master/r/144241
(cherry picked from commit f9b84c91ebc1d172a3ee9de0e578b0943d2cb13c)

Change-Id: I5c65317336e8f0497d90880e649e2e8cca0a222d
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/147278
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rbc80c3353edd329048dab5ba97d6a3d26dde1ce2

5 years agoARM: tegra: pluto: set pmic irq type to LEVEL_HIGH
Mallikarjun Kasoju [Mon, 22 Oct 2012 15:45:27 +0000]
ARM: tegra: pluto: set pmic irq type to LEVEL_HIGH

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/139684
(cherry picked from commit 0f14977653717a7070ac64d9884c4a42ab07f715)

Conflicts:

arch/arm/mach-tegra/board-pluto-power.c

Change-Id: I18b649fe99a33cfd34a53c9a32c7e9da68843661
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/146508
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R1fb206bc99062710916317a3b386c947519ea28d

5 years agoARM: tegra: dalmore: support disabling GRHOST
Jon Mayo [Wed, 19 Sep 2012 22:05:13 +0000]
ARM: tegra: dalmore: support disabling GRHOST

Fixes build to work if CONFIG_TEGRA_GRHOST is disabled.

Change-Id: I388a520895587d78d4cda5b5e04ec05aee708c0f
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/133895
(cherry picked from commit 70fe20172dc36eb766bb8657bf7b64a5aa865b8e)
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/145992
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3eb90482dbd8688d145b13623a6ee32aac4cf93c

5 years agoarm: tegra: dalmore: enable bluetooth support
Nagarjuna Kristam [Fri, 7 Sep 2012 03:39:03 +0000]
arm: tegra: dalmore: enable bluetooth support

Enable pinmux config for BT_EN, BT_RST and BT_EXT
Add bluesleep and rfkill platform resources

Bug 982624

Change-Id: I66f4b980d0060e3b203db588a07b179aa99a2993
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/132104
(cherry picked from commit f8049e3c050da317de04194bfe62ff2f355fa43a)
Reviewed-on: http://git-master/r/130095
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R067b9616ef4dbd44cbd7645d2e60c775a3be61ae

5 years agotegra: usb: disable interrupts when locking
Sang-Hun Lee [Tue, 15 May 2012 23:04:41 +0000]
tegra: usb: disable interrupts when locking

Problem description:
 - tegra_udc_irq uses udc->lock
 - Some functions running in the process context was not disabling
   interrupts when locking udc->lock
 - If a function gets interrupted by tegra_udc_irq after locking
   udc->lock, a deadlock occurs, as tegra_udc_irq would also try to
   lock

Fix description:
 - Use an interruption disabling variant of spin_lock

Bug 983958

Change-Id: Ib774847212da64f1f727a207a4821860ffa7b4a8
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/102693
(cherry picked from commit 168971ab0977d04e958671651c0be4be116fee01)
Reviewed-on: http://git-master/r/147718
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3270a9b2f31880c8a797ddf3ab9fe929cab46bfc

5 years agoarm: tegra: pluto: support onboard i500 modem
Jay Cheng [Thu, 13 Sep 2012 21:48:33 +0000]
arm: tegra: pluto: support onboard i500 modem

Inital patch for Pluto + onboard i500 modem bringup.

Bug 1040101

Change-Id: I5a1ac04061481ad19770e71f8ee9a21e8060c3a0
Reviewed-on: http://git-master/r/132681
(cherry picked from commit 5fa38cf848c0e462e17d02f8e12ab512a8387d26)
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/147488
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R6b1baf659fd0aa9a7db33fc9280c46e276e360f9

5 years agoarm: tegra: pluto: support i500 swd
Neil Patel [Fri, 14 Sep 2012 01:15:15 +0000]
arm: tegra: pluto: support i500 swd

Inital patch for Pluto + i500 SWD bringup.

Bug 1040101

Change-Id: I75787ff390ded87a8acdbdf1a86cbdc1be0d3f6a
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/132482
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/147487
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R06992e4051528188f20040e407e336a89f76ad70

5 years agoARM: tegra: Change CPU idle power state names
Bo Yan [Wed, 24 Oct 2012 21:09:15 +0000]
ARM: tegra: Change CPU idle power state names

LP3 means clock gating, so make it explicit.

Also changed the idle state name "LP2" to "powered-down".

bug 1034196

Change-Id: Icb2e8ba1aafa7b100cef96c7907940a251fd7e59
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/147280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R330175b25e1cc3a9d138f8376c670340d80e9429

5 years agoARM: Tegra: Dalmore: Enable PRISM
Matt Wagner [Sat, 29 Sep 2012 23:04:25 +0000]
ARM: Tegra: Dalmore: Enable PRISM

PRISM is enabled and tuned for 10.1" panasonic
panel.

Bug 1047558

Reviewed-on: http://git-master/r/139953
(cherry picked from commit c79dc602d82d6522de887474c940cd217dba3f53)

Change-Id: Ia9eb0ce4472fc9ae36e08e98f547705767486a84
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/147240
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R414fb243561dbb2fbf6e938c345a8bf65c317479

5 years agoARM: tegra: dalmore: define precision multiplier
Deepak Nibade [Thu, 25 Oct 2012 13:33:58 +0000]
ARM: tegra: dalmore: define precision multiplier

-Define precision multiplier as 1000 to consider
3 digit fraction precision of 'power_lsb'

Bug 1049224

Change-Id: Ibf677036ae81a6dcf87de24e762f6b03e991436d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/147593
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Raf5b01df561fd14e07c95badd80c8df1359b8d51

5 years agoCHROMIUM: config: set default hostname
Rhyland Klein [Tue, 23 Oct 2012 21:47:16 +0000]
CHROMIUM: config: set default hostname

Rather than wasting time in userspace running `hostname localhost`,
just boot the kernel with the default.

Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/34371
Reviewed-by: Olof Johansson <olofj@chromium.org>
(cherry picked from commit 8a1968a291abc47a0f05afd8967a4df6ae4da080)

This change fixes the issue where hostname was no longer working
on recent chrome nightlies.

bug 1164006

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Change-Id: I50318a1a6a1b9f7ed9bad4db968edda486e33904
Reviewed-on: http://git-master/r/147070
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: Ree11900fbd948b832c4c56a803485767663b6bb7

5 years ago ARM: tegra: configs: Add cryptodev support
Venkatajagadish [Thu, 20 Sep 2012 05:39:55 +0000]
 ARM: tegra: configs: Add cryptodev support

This config option enables the user space applications to
access the S.E.

Reviewed-on: http://git-master/r/133982
(cherry picked from commit d48570b439dfd6e5fe46e1ecf59d5bb53841930a)

Change-Id: I73a60321f99bda14f47059b23ea9dbed0ea47cb6
Signed-off-by: naveenk <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/146820
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Raeee57751cec1d0ff3ee9a3530a60173b9b90692

5 years agoarm: tegra: usb: HSIC re-enumerate fix
Suresh Mangipudi [Tue, 25 Sep 2012 23:30:55 +0000]
arm: tegra: usb: HSIC re-enumerate fix

If HSIC driver is load and unloaded repeatedly for 2 times the
device was freezing since the PHY clock was not up,
toggling the USB_SUSP_CLR would enable the PHY clock

Bug 1054019

Reviewed-on: http://git-master/r/138740
(cherry picked from commit c6019427d1fd248c3830f98f37261c8f33c506d4)

Change-Id: I087ba3be779378ff81123b09a8d49d397c629b35
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/146742
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R982ba4533b548c7809af4f8ca43e36465c998a5d

5 years agoarm: tegra: USB: PMC register offset
Suresh Mangipudi [Thu, 13 Sep 2012 08:12:58 +0000]
arm: tegra: USB: PMC register offset

Few of the register offsets for T114 have changed for PMC. Update the
T11x usb phy driver accordingly.

Reviewed-on: http://git-master/r/132183
(cherry picked from commit 79954c5bbe7414474ccfceb89e690255c50a9607)

Change-Id: I4b8541ea081b02c8568bdad56ad2e92eb5c5f4b8
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/146739
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R9bfca1b0fad5a54f19850a7c53bfecbb40a7c1a9

5 years agoarm: tegra: USB: Error checking
Suresh Mangipudi [Thu, 13 Sep 2012 12:43:20 +0000]
arm: tegra: USB: Error checking

Proper error checking for the usb_phy during regulator init.

Bug 1048288

Reviewed-on: http://git-master/r/132235
(cherry picked from commit 1658e70fb187be04408dbc268954d3e7ba5fbb75)

Change-Id: Iab8883e552e3e15eaaceb2be37695fa2828d9fab
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/146725
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R9e77765f98773aa923a6ae79d494ff0f1b820139

5 years agoARM: tegra: dalmore: add ina219 power monitor devices
Deepak Nibade [Wed, 26 Sep 2012 12:24:23 +0000]
ARM: tegra: dalmore: add ina219 power monitor devices

-add new board-dalmore-powermon.c file
-make according changes in Makefile,
 board-dalmore.c, board-dalmore.h
-this will provide support for dalmore in
 nvpm : command line tool for getting power rail data

bug 1049224

Change-Id: I9f0baca8a91931a1790275561a6bcc7e273e80cf
Reviewed-on: http://git-master/r/138952
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145590
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R5e199a188eb05c6edd015dc192b41811942f93a1

5 years agoarm: tegra: pluto/dalmore: Add mipi cal resource
Animesh Kishore [Tue, 23 Oct 2012 12:51:40 +0000]
arm: tegra: pluto/dalmore: Add mipi cal resource

Adding mipi calibration block as resource to display.

Bug 1054040

Change-Id: I6df0bbd3d05cd8c1e6641bed97d85495e97f88f0
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
(cherry picked from commit 203fc92eaf7932ac9662daaa27c75fb4e2d1ecb7)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146945
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R19c0bd2c81681b3d522ef69f0d7914e3da260cbd

5 years agoARM: tegra: dalmore: Fix temperature sensor vdd rail and i2c bus
Diwakar Tundlam [Wed, 19 Sep 2012 23:52:53 +0000]
ARM: tegra: dalmore: Fix temperature sensor vdd rail and i2c bus

Bug 1046108

Change-Id: I70057a4a06696f2e442c5893bcee204af4b414b7
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/133926
(cherry picked from commit ff20059d2f3d1136a85ea211f2eacd99df22e0df)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146666
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf13fb9cdf47f033433e3804bec3a3497943e3e9e

5 years agodrivers: power: max77665: modify otp settings
Syed Rafiuddin [Thu, 18 Oct 2012 08:48:31 +0000]
drivers: power: max77665: modify otp settings

Modify default input current limit opt settings to
resolve frequent usb cable plug/un-plug issue.

Bug 1154672

Change-Id: I6f17102f08dbeb62e58edc24c55730a96d7b597d
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/145233
(cherry picked from commit 7f64bb3f4d662c6c6da2b1ad0c9d6653fe70e764)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147061
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Ra019774c76d682a746c2ddf7d7b7c5f4184295ed

5 years agodrivers: misc: therm_est: add debug sysfs nodes
Joshua Primero [Wed, 17 Oct 2012 00:29:14 +0000]
drivers: misc: therm_est: add debug sysfs nodes

Added the ability change coefficients and offset during runtime.
This is found in /sys/devices/therm_est/coeffs and
/sys/devices/therm_est/offset.

Also, added the ability to view the history of temperatures
per device used by the therm_est driver. This is found in
/sys/devices/therm_est/temps.

bug 1158994
bug 1059470

Change-Id: Ie3441a2c9a613381d4e19c61479001975488fd76
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/145060
(cherry picked from commit ee1078d1262fd0f01d156796837c3c67f92d3873)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147060
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf68a5473fa9ebe40ff38c8337689b0b14ea04f63

5 years agoARM: tegra: soctherm: Enable clocks
Joshua Primero [Tue, 25 Sep 2012 23:31:47 +0000]
ARM: tegra: soctherm: Enable clocks

Initialized clocks to enable soctherm. Note soctherm is still
not enabled until CONFIG_TEGRA_SOCTHERM is enabled.

Change-Id: I99eaa7f1da3369b61354b8121586f3c374d6ea5e
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/138788
(cherry picked from commit 01fe3665c64a7cc0f11322c3a72d43fa67b0fbe5)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147058
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R7389d38e01157cebcbe46330b3119bbd4092e099

5 years agoARM: tegra: soctherm: Enable pulse skipper
Joshua Primero [Tue, 2 Oct 2012 22:09:55 +0000]
ARM: tegra: soctherm: Enable pulse skipper

Enable pulse skipper hardware throttling.

Change-Id: I00855d491e603270b8e81b7f7feb8e94e294b1fd
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/141035
(cherry picked from commit a42307516078f48c2b784158e84adcf3eaf4cd30)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147057
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Ra5ea66cebfa3998a379c651df9c05a79d0d8c9c1

5 years agoarm: tegra: pluto: Fix reset sequence
Animesh Kishore [Sat, 13 Oct 2012 03:02:57 +0000]
arm: tegra: pluto: Fix reset sequence

Fixing reset for 1080p Sharp panel.

Change-Id: I9778aa414adf34911db335e6c9c0eae00e9af8a9
Reviewed-on: http://git-master/r/144295
(cherry picked from commit 05ae8295189bf571a8d9335d512408d0ae543c13)
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
(cherry picked from commit 625576b0a2f89ffe176016adec07a34c765f5f18)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147056
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rfd6711359fb0e6401cb495d83d4756a5fa6adc08

5 years agoarm: tegra: pluto: Add support for Sharp 1080p LS050T1SX01(G) panel
Animesh Kishore [Tue, 23 Oct 2012 09:14:49 +0000]
arm: tegra: pluto: Add support for Sharp 1080p LS050T1SX01(G) panel

Bug 1156912

Change-Id: I0ccccd0c86822a948ea6a18ead25d36e64d56858
Reviewed-on: http://git-master/r/143956
(cherry picked from commit 9f728c192fb37007867fc9c80f5d4768332c7217)
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
(cherry picked from commit 1de4be6b8870c8fc8d4f24cc0f8bcbf4bd6f02a9)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147055
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Re3e5400ba0fdacbb070dcccde66f2e02a8c50321

5 years agoarm: tegra: power: check chip-id and select table or calculated edp
Diwakar Tundlam [Tue, 9 Oct 2012 23:08:44 +0000]
arm: tegra: power: check chip-id and select table or calculated edp

Change-Id: Ib1b6641095d3568e339c1e56a199157d8f25ad84
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/142786
(cherry picked from commit 8de620ebdaf0426bf64db2a0d3feb04f003b11f8)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146699
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Rc75b6c21137aa26c6bff2848d18b72c99f407b07

5 years agoarm: config: enable max77665 battery charging
Syed Rafiuddin [Wed, 10 Oct 2012 09:28:39 +0000]
arm: config: enable max77665 battery charging

enabling maxim max77665 battery charging driver

Change-Id: Idbb705fc070ebfc09d3a98d990a726aaebcd04c3
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135175
(cherry picked from commit bbcaf9349af5fd148ebaf3ae22310aa3366a5fd2)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146698
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R40f9a1bde1f5b57990f6a3f0581bd53a2d9741da

5 years agoarm: tegra: pluto: board changes for max77665 charger
Syed Rafiuddin [Wed, 10 Oct 2012 09:33:46 +0000]
arm: tegra: pluto: board changes for max77665 charger

board changes for maxim max77665 battery charger driver

Change-Id: I2ffd9dc9ec1cc4f7ed28cf246c58e2a8138c21ce
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135173
(cherry picked from commit d896ad00664cbf714c9fa3a494062c8a65336a5d)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146697
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R1f46bce97f9ad9ca3e476f198d8c226116fcb887

5 years agodriver: max77665: fix multiple issues in charger driver
Syed Rafiuddin [Fri, 28 Sep 2012 11:37:27 +0000]
driver: max77665: fix multiple issues in charger driver

- fix probe issue.
- differentiate between E1236 and E1587
- use late_initcall
- init charger values correctly

Change-Id: Iab11261dab084bd707dcd9d24d236d3c1b438b0e
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135174
(cherry picked from commit 7360d8753133ef15cd59264fd02613c42cacbd93)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146695
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb164179f576d0100652db9ef1c2c9ae8adb0dca7

5 years agodrivers: mfd: add bulk read in max77665 core driver
Syed Rafiuddin [Fri, 28 Sep 2012 11:42:28 +0000]
drivers: mfd: add bulk read in max77665 core driver

addition of bulk read api in maxim max77665 core driver

Change-Id: Iafb6ce4ae6918c027bbeacd9d243e0e38dd9f7e9
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135172
(cherry picked from commit 1e0dc1b22b5c7bff4f41e2c8c9745c53f0721dbf)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146694
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R54de7c51b17e76ed35ef54583cef5e7ede063b4b

5 years agoarm: config: tegra: enable max77665 fuel-gauge driver
Syed Rafiuddin [Fri, 28 Sep 2012 11:21:47 +0000]
arm: config: tegra: enable max77665 fuel-gauge driver

Enabling max77665 fuel-gauge driver for pluto platform

Change-Id: Ia24db1c5bfd9199dcc0a1935dd85a98d3abe9dd7
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135120
(cherry picked from commit 6642b37f9d27d83a5f923ca17d6f893669d3c727)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146693
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R043974e6f3c556e4b186154514c7d4046dcc1d40

5 years agoarm: tegra: pluto: board changes for max77665 fg driver
Syed Rafiuddin [Fri, 28 Sep 2012 11:20:07 +0000]
arm: tegra: pluto: board changes for max77665 fg driver

board specific changes for max77665 fuel-gauge driver

Change-Id: I513b4e4402df5f3ba45efd1684d4d64ccf97daf7
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135119
(cherry picked from commit 340ca387681fea1907748a9fcf562d7903a4f5bf)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146692
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb45a6264f96473ca0ecfdf5304046d08ec304f73

5 years agopower: max17042: update status contineously
Syed Rafiuddin [Fri, 28 Sep 2012 12:00:25 +0000]
power: max17042: update status contineously

update battery characterstics contineously so that
the status gets updated in gui

Change-Id: I50ccc6484825a730edf7e7b01f6ea187bf7215db
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/135118
(cherry picked from commit 7200ea672e9c4569bb26773ba5c68ca802fd2182)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146691
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb9660efd4fb91bfab523154bfbfdd8d2e17a84ad

5 years agoARM: tegra: Fix temperature trend control logic
Diwakar Tundlam [Sat, 6 Oct 2012 00:51:14 +0000]
ARM: tegra: Fix temperature trend control logic

Set tc2 correctly for thermal layer to assess trend

Bug 1057977

Change-Id: If92788d2b9438e5ff932407720d42d4a777b4279
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/142133
(cherry picked from commit 42f2e06818613e19a526c94646007d9919cecf6f)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146690
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R670fe1874715a38ac3dae6b14c2b714eff6c6f99

5 years agoarm: tegra: pluto: Fix LG panel init delay
Animesh Kishore [Thu, 4 Oct 2012 22:06:23 +0000]
arm: tegra: pluto: Fix LG panel init delay

Reduce panel init delay.

Bug 1054104

Change-Id: I516ec3d48a216a0e52b020314b59494ffb1ff1eb
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/141712
(cherry picked from commit c72fb7d781f6442d8b852d60adf20e04e3e82ee3)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146688
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb96b5e483a14c9083fd9228b680b0f4b065ac06f

5 years agoARM: tegra: thermal: Utilize hysteresis on nct
Joshua Primero [Fri, 5 Oct 2012 00:25:51 +0000]
ARM: tegra: thermal: Utilize hysteresis on nct

Added 1 degree hysteresis to edp thermal management trip points.

bug 1057977

Change-Id: I8a278cc3e4288ccc5f7cb7896382cb98e3c9b2a3
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/141776
(cherry picked from commit b0d89dd8c9488edf6c0e513606dc8cc3b24ac35d)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146687
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf795b5281973d25152172c9a295d197ae015ec07

5 years agodrivers: nct: Added hysteresis
Joshua Primero [Fri, 5 Oct 2012 00:24:54 +0000]
drivers: nct: Added hysteresis

Added hysteresis functionality to thermal trip points.

bug 1057977

Change-Id: I377fee3932fd5a9f264672a889eb438dcdcc99ab
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/141775
(cherry picked from commit 06d721750fcd31cceb277bb30685f86180fee326)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146686
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R1609c598bfe9b261653dfb480eee452f6866caad

5 years agoarm: tegra: dalmore/pluto: Copy bootloader fb to kernel
Animesh Kishore [Thu, 4 Oct 2012 22:29:42 +0000]
arm: tegra: dalmore/pluto: Copy bootloader fb to kernel

Change-Id: Iaa52db11e2f5281e2aaff737d3a648fdf74a3b7e
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/141740
(cherry picked from commit 8f9b7d2ecc8f1bbb5d0ca08fccc22a0ccacb5b70)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146685
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rc2ba6ab235abd96722ddff5391b2ab4455498f76

5 years agoARM: tegra: soctherm: Hook soctherm to sw throttle
Joshua Primero [Fri, 28 Sep 2012 23:00:26 +0000]
ARM: tegra: soctherm: Hook soctherm to sw throttle

Start integrating soctherm with the balanced throttling
software module.

Change-Id: I8d6f310ba7676672fb657c349b5b70462bddbb9a
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139847
(cherry picked from commit ca094f06dcfcf7ce46ed7c41c2b3a5bd9f399544)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146683
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R4a4ef52d47e8145752a28416de5f321b3f04d411

5 years agoARM: tegra: soctherm: Enable THERMTRIP
Joshua Primero [Fri, 28 Sep 2012 20:51:52 +0000]
ARM: tegra: soctherm: Enable THERMTRIP

Exposed platform data to cause CPU/GPU/MEM/TSENSE shutdown based on
thresholds

Change-Id: I3f53ea6ef062d61c86915af03360f703f3ee6257
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139828
(cherry picked from commit d5f29d91e4ed963c43bd61b0c8bbb31ccfbe2e75)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146682
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3bb844dbaf7e38c2c013673a3c473b76c2df11f2

5 years agoARM: tegra: soctherm: Enable interrupts
Joshua Primero [Fri, 28 Sep 2012 00:01:58 +0000]
ARM: tegra: soctherm: Enable interrupts

Enable interrupts on soctherm driver. Verified that it works.

Change-Id: Idd7fb87ebeda67ea50f8cf54b9a62e9843b7a095
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139507
(cherry picked from commit 95460f26f4a3ba623cceb65507471e8a6ac456ae)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146681
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Ra6156eccc6c1e7c566fdd34b970647f8942c81bc

5 years agoARM: tegra: thermal: Multiple sensor programming
Joshua Primero [Wed, 5 Sep 2012 02:21:59 +0000]
ARM: tegra: thermal: Multiple sensor programming

Enabled programming of the multiple sensors in soctherm.

Change-Id: I814a90742430d9ffd502f2bf9b34e1ce3e20513b
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/138787
(cherry picked from commit 6362b1868a610b6ee553b8e8b8291407d8c4da0a)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/130400
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R8e38f8cdc8b178e05a74816afb60dc6d6695412c

5 years agoARM: tegra: thermal: added soctherm to thermals
Joshua Primero [Tue, 7 Aug 2012 22:15:59 +0000]
ARM: tegra: thermal: added soctherm to thermals

Added soctherm to existing thermal infrastructure.

Change-Id: Id349aec9ae98f4f545d3f7f38d0b5e7d6aa7c979
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/138784
(cherry picked from commit 6637d00411babcab71a90ff15b7e1ef3087db523)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146679
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Re1b3c79acd3136716cad045da2511917014a9bff

5 years agoarm: tegra: power: fix dynamic VDD_CPU EDP capping granularity
Diwakar Tundlam [Tue, 2 Oct 2012 23:54:39 +0000]
arm: tegra: power: fix dynamic VDD_CPU EDP capping granularity

Changed freq-step to ensure EDP freq caps line up with actual cpufreqs
Also since min-cpufreq changes after bootup, don't use min, use 0.

Change-Id: I57498b719b06f7dd3bade5b2038277c2564c69cc
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/141055
(cherry picked from commit 37d92240720f40c0528188ec4409ac5055397e4b)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146678
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R0b740fe222bf61eb2aadb5356df878770414b3b2

5 years agoarm: tegra: power: enable dynamic VDD_CPU EDP capping
Diwakar Tundlam [Fri, 21 Sep 2012 08:02:42 +0000]
arm: tegra: power: enable dynamic VDD_CPU EDP capping

Using the model used to enforce max frequency for a given VDD_CPU EDP.
Enabled for dalmore and pluto.

Initialised edp_reg_override to 6A and increased default per-platform
edp-limit higher by 6A to allow users to override the limit up by upto
6A when needed for specific use-cases.

Change-Id: I2741ba7316cebe0ae2836b84c4b3bbbe0afefe5e
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/134306
(cherry picked from commit 9648d86f4a9a7b3b2557e98530e8265ea9f53467)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146677
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R41ff83ba9a5dd4c1799961cc00dc6e796a93c8ba

5 years agoarm: tegra: power: Update dynamic CPU EDP model
Daniel Solomon [Tue, 4 Sep 2012 02:09:43 +0000]
arm: tegra: power: Update dynamic CPU EDP model

Update the model used to calculate max frequency
for a given VDD_CPU EDP.

Change-Id: Id220f25b58880c936f621f07faae414be42e8971
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/133051
(cherry picked from commit eca6edfc4220c5d0a004e9655926ea805c485152)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/132941
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rc0a772f04ed867da313d2044f6bc6a26ae58cd57

5 years agodrivers: nct: tsensor: writeable trip points
Joshua Primero [Tue, 11 Sep 2012 23:23:41 +0000]
drivers: nct: tsensor: writeable trip points

Added nct functionality to change trip points. This
will be useful for EDP and thermal throttling.

Change-Id: I4fef643263261701164027f9bb13794b37e4907e
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139083
(cherry picked from commit 0dd4d083d4379752f7db241800d9501460b63d07)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146674
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb7977a58b4ae5e491cfe258b529aec054534fbd1

5 years agodrivers: nct: Fixed uninitialized variable
Joshua Primero [Mon, 10 Sep 2012 23:15:12 +0000]
drivers: nct: Fixed uninitialized variable

Initialized variable to 0

Change-Id: Ib05d83b5a06bf8e3ece4c4b1856f4e702f7f9494
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/139081
(cherry picked from commit 1df057920f583fe2c8f10fb37411420c52a91b5a)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146672
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rba2d17f5dbcc5eead53304f513f26a9e47a24392

5 years agoarm: tegra: power: add throttle_count sysfs
Diwakar Tundlam [Wed, 26 Sep 2012 22:22:24 +0000]
arm: tegra: power: add throttle_count sysfs

Added counter to show number of throttling instances

Change-Id: I3d1b4c0fe92aeb5b084edaea4051d48a3ce8b6d0
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/139094
(cherry picked from commit 8eb8dd9040260a7e703eff055994a8f5422ea062)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/146671
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R946eb680923d7b3d71959ed2e7717c01f1e92e99