5 years agoARM: tegra: mipi-cal: t148 specific clk72mhz
Charlie Huang [Wed, 28 Aug 2013 19:37:43 +0000]
ARM: tegra: mipi-cal: t148 specific clk72mhz

clk72mhz is t148 arch specific clock name, no need to request it for
t114, otherwise a kernel warn will be reported.

bug 1353722

Change-Id: Idcbf110dcbdb0f5dce61336bd4fa8ef659683b71
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/268733
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: tn8: change compass I2C add for tn8
Daniel Fu [Thu, 29 Aug 2013 06:46:58 +0000]
ARM: tegra: tn8: change compass I2C add for tn8

The sensor module of TN8 is different from ardbeg.
Change Compass I2C add to 0x0D.
Change Compass Power tree entries for TN8.

Bug 1348064

Change-Id: I75b9e9078da82c5ef61b7f772e1cc9dc56bea129
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: http://git-master/r/267799
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra12: Fix unpowergate sequence for GK20A
Prashant Malani [Thu, 1 Aug 2013 03:03:31 +0000]
ARM: tegra12: Fix unpowergate sequence for GK20A

Ensure that GPU partition reset is asserted
before we remove the clamp to gpu power
partition.

Bug 1339089

Change-Id: I6db01d1e4a4bba814a74b5f2881e3adc69f6b1ca
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/264099
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: add bq20z45 guage support for ardbeg
Andy Park [Mon, 26 Aug 2013 21:47:17 +0000]
arm: tegra: add bq20z45 guage support for ardbeg

Enable BQ20Z45 Fuel Guage in Ardbeg board file.

Bug 1344257

Change-Id: I0be05142a9d14a7b71f2b4bfe232d8f7467dc292
Signed-off-by: Andy Park <andyp@nvidia.com>
Reviewed-on: http://git-master/r/268059
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: add bq2471x charger support for ardbeg
Andy Park [Mon, 26 Aug 2013 21:44:44 +0000]
arm: tegra: add bq2471x charger support for ardbeg

Add necessary battery charger data to ardbeg board file to support
BQ24715/BQ24717 battery charger.

Bug 1344257

Change-Id: I0e01a60c5f75ef2eac05861876d948b457351004
Signed-off-by: Andy Park <andyp@nvidia.com>
Reviewed-on: http://git-master/r/268057
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: Remove legacy IOCTLs
Terje Bergstrom [Tue, 27 Aug 2013 06:38:13 +0000]
video: tegra: host: Remove legacy IOCTLs

Remove legacy calls. The old submit interface was deprecated a year
ago and the old GPU ioctl's were not used in main codeline.

Change-Id: I36b9815feed32efccac5c8c6f9bc0a27690cf3ee
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267182

5 years agopinctrl: palmas: remove unused member of pinctrl-palmas platform data
Laxman Dewangan [Fri, 30 Aug 2013 09:04:44 +0000]
pinctrl: palmas: remove unused member of pinctrl-palmas platform data

Change-Id: I904e31f19bab1a41eb76574c9ecafd79d35d76d8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/268422
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: ardbeg: Support E1792
Seema Khowala [Tue, 6 Aug 2013 23:26:14 +0000]
arm: tegra: ardbeg: Support E1792

E1792 is same as Sheild E1780 SKU1000 except
the Memory.E1792 has LPDDR3(EDFA164A2MA-JD-F,
LPDDR3 x32, 933Mhz, 16Gb) instead.
Default DDR voltage for E1733 and E1735 pmu
is 1.35V but lpddr3 supports 1.2V

Bug 1339736

Change-Id: Ie1e23e3512876940349ee6c4c915c890b5ebfdad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/263470
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agostaging: android: avoid memory access after free
Krishna Reddy [Fri, 30 Aug 2013 15:45:41 +0000]
staging: android: avoid memory access after free

driver data has to be set before destroyig device to avoid
accessing memory after free.

Change-Id: I03bbd35aaee293ffb52e3c3a43e179888b6ab91c
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/268588
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoswitch: avoid memory access after free
Krishna Reddy [Fri, 30 Aug 2013 15:38:41 +0000]
switch: avoid memory access after free

driver data has to be set before destory of device to
avoid accessing memory after free.

Change-Id: Id06a9239a26958917363c45721dc0bee1aba1ced
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/268587
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: nvmap: fix incorrect memory access
Krishna Reddy [Fri, 30 Aug 2013 15:27:29 +0000]
video: tegra: nvmap: fix incorrect memory access

fix incorrect memory access sequence in nvmap_dmabuf_release().
handle memory access after handle put can result in accessing
freed memory.

Change-Id: I824b348366c1737c9d5ec15cc58613938203fb0f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/268584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra12: ardbeg: turn off ldo1 of TPS65913
Wen Yi [Mon, 26 Aug 2013 22:29:25 +0000]
arm: tegra12: ardbeg: turn off ldo1 of TPS65913

The rail ldo1 supplies to 1v05 pll rails and should be
turned off when device is in LP0.

Bug 1355205

Change-Id: I2ecde33da725349cd866ec00664615e81cbe1e76
Signed-off-by: Wen Yi <wyi@nvidia.com>
Reviewed-on: http://git-master/r/266234
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoarm: tegra: laguna: enable cl_dvfs and correct the settings
Kerwin Wan [Wed, 7 Aug 2013 06:54:17 +0000]
arm: tegra: laguna: enable cl_dvfs and correct the settings

Change-Id: I8defc1e34f097ed843698684db042747696ec289
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/267757
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: configs: enable bq2471x as default on t12x
Andy Park [Mon, 26 Aug 2013 21:48:30 +0000]
arm: configs: enable bq2471x as default on t12x

Enable BQ2471X Battery Charger as default on T12X devices.

Bug 1344257

Change-Id: Ib10df6bb83db081b59a9f677075a020dcd77e278
Signed-off-by: Andy Park <andyp@nvidia.com>
Reviewed-on: http://git-master/r/268058
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: add bq2471x battery charger driver
Andy Park [Mon, 26 Aug 2013 21:41:51 +0000]
power: add bq2471x battery charger driver

Add BQ24715/BQ24717 battery charger driver.

Bug 1344257

Change-Id: Ia5bf9d3af7f836d937634b00043adef1c6391b0b
Signed-off-by: Andy Park <andyp@nvidia.com>
Reviewed-on: http://git-master/r/268056
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: pinmux: Fix GME, AT5 drive pinmux
Chaitanya Bandi [Thu, 29 Aug 2013 10:20:57 +0000]
ARM: tegra: pinmux: Fix GME, AT5 drive pinmux

Fixed the definitions of GME, AT5 drive pinmux
registers.

Bug 1347466

Change-Id: If30197a6cec9d7cb543c65619680d279fc99c549
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/267904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: Eliminate build warnings and errors
Mark Zhang [Thu, 15 Aug 2013 05:48:25 +0000]
video: tegra: Eliminate build warnings and errors

Eliminate build warnings and errors if "CONFIG_TEGRA_GRHOST_SYNC"
is not enabled.

Change-Id: I7157c56f041cc5593be0c3ea38046960ef7d65af
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/262328
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: fix nvhost block free
Kevin Huang [Thu, 29 Aug 2013 18:58:28 +0000]
video: tegra: host: fix nvhost block free

The pointer to the next block is accidentally freed when we free
current block.

Bug 1355842

Change-Id: I60a87825dab2a269fe67728d2b3fbebfc14a7b3b
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/268060
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agousb: xhci: tegra: enable otg with xusb host
Rohith Seelaboyina [Thu, 29 Aug 2013 05:00:13 +0000]
usb: xhci: tegra: enable otg with xusb host

enable switching between usb2.0 device and xusb host
on otg port

Bug 1307598

Change-Id: I19519d95de394386699f346ef4949278a7455ee6
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/265538
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: usb: support xusb on otg port
Rohith Seelaboyina [Wed, 28 Aug 2013 14:52:06 +0000]
ARM: tegra: usb: support xusb on otg port

platform data to support changing port ownership
to xusb when port 0 is in host mode

Bug 1307598

Change-Id: I3fd332b07ebfbb8b3baca400500a7e984c88a99e
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/265537
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agousb: tegra: xhci:Transfer utmi port to pmc in elpg
Rohith Seelaboyina [Thu, 22 Aug 2013 10:52:30 +0000]
usb: tegra: xhci:Transfer utmi port to pmc in elpg

Program pmc for transfer of utmip ports to pmc
during elpg entry or exit.

Bug 1307598

Change-Id: Iabc250202e7e3386b18889a136cdf2f04c27698f
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/265536
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: xusb:Transfer utmi port to pmc in elpg
Rohith Seelaboyina [Thu, 22 Aug 2013 10:06:04 +0000]
ARM: tegra: xusb:Transfer utmi port to pmc in elpg

Program pmc for utmip ports during elpg entry/exit.

Bug 1307598

Change-Id: I29803a053850418ca532c438cc390cdc5de12d25
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/265535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: tegra: use soctherm for thermal actions
Diwakar Tundlam [Thu, 29 Aug 2013 00:54:55 +0000]
arm: tegra: use soctherm for thermal actions

Check soctherm CP and FT fuse revision and if valid, switch thermal
trip points to use socthem thermal zones. We remove tegra-balanced
cooling device from NCT platform data and raise NCT's shutdown point
by 20C to effectively deactivate it.

With this change, thermal actions will use soctherm on properly fused
chips and use NCT on improperly fused chips.

Changed trip point thresholds to T148 values as recommended by HW
engg, until TSOSC and hotspot characterization is done. Enabled
throttling and therm-trip on CPU and GPU TSOSCs.

Bug 1291108

Change-Id: Ib43d1aa05371d67dc2edffd8936489198f688bc2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/267649

5 years agoarm: tegra: use fuse check rev api and init soctherm
Diwakar Tundlam [Thu, 29 Aug 2013 00:47:49 +0000]
arm: tegra: use fuse check rev api and init soctherm

Bug 1291108

Change-Id: Ic833e7618fc1f97dc79e7a060543960aa3844f75
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/267648

5 years agoarm: tegra: add api to check fuse revision
Diwakar Tundlam [Wed, 28 Aug 2013 21:31:16 +0000]
arm: tegra: add api to check fuse revision

Bug 1291108

Change-Id: Iff50cc37452ecc20164b35ad3ef8caec3a0551f8
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/267647
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: soctherm: fix invalid array index
Xin Xie [Tue, 25 Jun 2013 00:36:43 +0000]
arm: tegra: soctherm: fix invalid array index

We are using the -1 for the enum typed value and it is used for array
access.

bug 1312613

Change-Id: I52b31327e9c332616675cda30877737d42f23ac1
Signed-off-by: Xin Xie <xxie@nvidia.com>
Reviewed-on: http://git-master/r/241619
(cherry picked from commit 32ccb8129534e279702eacfa4789d05f93603470)
Reviewed-on: http://git-master/r/267646
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agovideo: tegra: nvmap: implement begin/end_cpu_access
Krishna Reddy [Thu, 29 Aug 2013 20:34:49 +0000]
video: tegra: nvmap: implement begin/end_cpu_access

realize begin_cpu_access, end_cpu_access interface in nvmap dambuf.

Change-Id: I9ad3476831237651420b3c005295058d8e0e9570
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/268087
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: nvmap: rename cache_maint function
Krishna Reddy [Thu, 29 Aug 2013 20:22:14 +0000]
video: tegra: nvmap: rename cache_maint function

rename cache_maint function to __nvmap_cache_maint and
expose it for other nvmap files.

Change-Id: Ieb12eb2c38dc3d226b10f5df71eea50c9d0bfa8e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/268086
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: Tegra12: Clocks: Update clocks frequency for display block
Krishna Sitaraman [Wed, 28 Aug 2013 23:19:20 +0000]
ARM: Tegra12: Clocks: Update clocks frequency for display block

Update the display clocks to support higher resolution displays.

Bug 1355253

Change-Id: I8c30d83d03efa17c9271d31778ff67625590279d
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/267600
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agotegra: Kconfig: Select shared pad config option
Anand Bhatia [Wed, 28 Aug 2013 18:58:22 +0000]
tegra: Kconfig: Select shared pad config option

Helper functions to enable or disable PCIE physical pads are not
available if USB support is disabled. Select TEGRA_USB_SHARED_PAD
if TEGRA_PCI is enabled OR if USB_SUPPORT is enabled.

Change-Id: Ic24f525442f093d4213dc497a0ae321ddbfbfcfd
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/267470
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoplatform: tegra: Use usb shared pad config option
Anand Bhatia [Wed, 28 Aug 2013 18:48:20 +0000]
platform: tegra: Use usb shared pad config option

Helper functions to enable or disable PCIE physical pads are not
available if USB support is disabled. Using TEGRA_USB_SHARED_PAD
compiles shared pad support when TEGRA_PCI is enabled OR if
USB_SUPPORT is enabled.

Change-Id: I1520d934fdefebbf8ddf2424b0d03072580bb6c9
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/267469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoUSB: Kconfig: Added config option for shared pad
Anand Bhatia [Wed, 28 Aug 2013 00:26:56 +0000]
USB: Kconfig: Added config option for shared pad

Helper functions to enable or disable PCIE physical pads are not
available if USB support is disabled. Created a separate config
option TEGRA_USB_SHARED_PAD to include these function based on
either USB or PCIE enable.

Change-Id: I6f0a31e7c4c43b13e7e41890b2586f67a247a9b8
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/266993
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: dc: Clean up dp/lvds code
Chao Xu [Wed, 28 Aug 2013 23:38:50 +0000]
video: tegra: dc: Clean up dp/lvds code

. Fixing errors with link training.
. Not setting pll_dp as the parent of sor_clk.
. Not enabling dc CRC (it was enabled for testing purpose).

Change-Id: I432e0d7f73f1df394ed4af90dcd1715ecf2dd4f9
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/267622

5 years agovideo: tegra: nvmap: validate handle correct
Krishna Reddy [Thu, 29 Aug 2013 04:43:10 +0000]
video: tegra: nvmap: validate handle correct

during nvmap_dmabuf_export validate the handle correct.

Change-Id: I2e06d652a716ca545ffe6dc4a87400bf6baaaa2d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/267697
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dsi2edp: add ASSR support
Ken Chang [Thu, 30 May 2013 06:09:19 +0000]
video: tegra: dsi2edp: add ASSR support

Enable TC358770A ASSR if eDP panel is connected
and the panel supports ASSR.

Bug 1295551
Bug 1211053

Change-Id: I99e831f060b64524f92643325472f346f42ff285
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/234379
(cherry picked from commit 5873bd15186d04c7941441854f3e64d9f8d9aed4)
Reviewed-on: http://git-master/r/263003
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra: la: set t148 bbc ptsa values are PROD values
Krishna Reddy [Thu, 15 Aug 2013 00:27:13 +0000]
arm: tegra: la: set t148 bbc ptsa values are PROD values

Change-Id: Ib078a733dfd75d8af137e680a818075991a3ca5e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/266184
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agotegra: video: fix timing reg set for 1080i
Xue Dong [Wed, 28 Aug 2013 23:03:42 +0000]
tegra: video: fix timing reg set for 1080i

bug 1343195

Change-Id: Ied1cf35f894f094974e71ac48efbfb5bd9da5cad
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/267590
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: Fix build error if tegra 2x is enabled
Mark Zhang [Wed, 14 Aug 2013 10:14:17 +0000]
video: tegra: Fix build error if tegra 2x is enabled

Callback ops "postpoweron" has been changed but the in tegra 2x,
the codes which call it doesn't change which makes a build error.

Change-Id: Ia861304d172b2516bcb5f7a82e45d62ddc3cff18
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/262265
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: Remove SWITCH ifdef
Mark Zhang [Thu, 15 Aug 2013 03:00:03 +0000]
video: tegra: Remove SWITCH ifdef

Remove a "ifdef" for CONFIG_SWITCH. The variable declared
in this "ifdef" is not only used by switch related codes.
So if we disable CONFIG_SWITCH, a build error occurs.

Change-Id: I1fac37e5045502a2fc375efefe7a2fce83b4a248
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/262323
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: nvmap: fix warning in ioctl_pinop
Krishna Reddy [Wed, 28 Aug 2013 21:32:20 +0000]
video: tegra: nvmap: fix warning in ioctl_pinop

Change-Id: Ida67dd93f145d9f75816816660f968549152c1a6
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/267549
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: Dump DC interlace regs when config enabled
Mark Zhang [Thu, 15 Aug 2013 06:37:31 +0000]
video: tegra: Dump DC interlace regs when config enabled

Only dump DC interlace regs when "CONFIG_TEGRA_DC_INTERLACE"
is enabled, otherwise the build fails.

Change-Id: I370055b91e83c7ca9badf0cf1304c88e8ec0bdf2
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/262331
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: Mask SOR tusize field before set
Mark Zhang [Wed, 28 Aug 2013 08:49:46 +0000]
video: tegra: Mask SOR tusize field before set

To set a field in the register, we need to mask it first then do
the setting. Otherwise the old value should be muxed with the
new value.

Change-Id: I2b1ed2f32c609101bcac0572382bf1ec3e4a9cc7
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/267668
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: Synchronize CRC read
Michael Frydrych [Tue, 13 Aug 2013 12:25:54 +0000]
video: tegra: dc: Synchronize CRC read

Wait for frame_end interrupt when reading CRC
register. Then, if read function is initiated
after window register activation, the CRC will
correspond to just activated config.

bug 1346194
bug 1356757

Change-Id: I94662fc9594bc70d5a5eaf42223309d6617b22bc
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-on: http://git-master/r/267296
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra12: clock: 3-bit client mux
Kaz Fukuoka [Thu, 23 May 2013 01:53:09 +0000]
ARM: tegra12: clock: 3-bit client mux

On Tegra12, all the client mux is changed to 3-bit.
This change removes old treatment of 3-bit mux (MUX8 flag),
and treat all the client mux as 3-bit.

bug 1281129

Change-Id: Iaccef6032606a34d6f08c063523bbd3b004c7710
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/265786
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoSUNRPC: Fix memory corruption issue on 32-bit highmem systems
Trond Myklebust [Wed, 28 Aug 2013 17:35:13 +0000]
SUNRPC: Fix memory corruption issue on 32-bit highmem systems

Some architectures, such as ARM-32 do not return the same base address
when you call kmap_atomic() twice on the same page.
This causes problems for the memmove() call in the XDR helper routine
"_shift_data_right_pages()", since it defeats the detection of
overlapping memory ranges, and has been seen to corrupt memory.

The fix is to distinguish between the case where we're doing an
inter-page copy or not. In the former case of we know that the memory
ranges cannot possibly overlap, so we can additionally micro-optimise
by replacing memmove() with memcpy().

Bug 1357971

Change-Id: If8e21f06f0cd65a4eb76d38939cd1851b8eaa7e9
Reported-by: Mark Young <MYoung@nvidia.com>
Reported-by: Matt Craighead <mcraighead@nvidia.com>
Cc: Bruce Fields <bfields@fieldses.org>
Cc: stable@vger.kernel.org
Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/267939
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agovideo: tegra: dc: add sysfs interface for hdmi settings
siddardha naraharisetti [Tue, 27 Aug 2013 20:51:18 +0000]
video: tegra: dc: add sysfs interface for hdmi settings

Added sysfs interface to update hdmi related settings like
drive strength etc for the purpose of tuning

Bug 1313494

Change-Id: I5ada1fb68fef34208dfdbce817c788bd266d8054
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/267539
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agopinctrl: palmas: add dt support for palmas pincontrol driver
Laxman Dewangan [Thu, 29 Aug 2013 16:02:34 +0000]
pinctrl: palmas: add dt support for palmas pincontrol driver

Add DT support for the palmas pincontrol driver. The driver can
be instantiated from DT as well as from board files.

Modify the boardfiles to align with changes.

Change-Id: I20a6ece4016b7028b3640ba7df4b798805d9e598
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267845

5 years agopinctrl: utils : add support to pass config type in generic util APIs
Laxman Dewangan [Thu, 29 Aug 2013 07:36:11 +0000]
pinctrl: utils : add support to pass config type in generic util APIs

Add support to pass the config type like GROUP or PIN when using
the utils or generic pin configuration APIs. This will make the
APIs more generic.

Added additional inline APIs such that it can be use directly as
callback for the pinctrl_ops.

Changes from V1:
- Remove separate implementation for pins and group for
  pinctrl_utils_dt_free_map and improve this function
  to support both i.e. PINS and GROUPs.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 3287c24088abded9f111ca797fdd36f86912d199)

Conflicts:

drivers/pinctrl/pinctrl-palmas.c

Change-Id: Ib37c1692040c606f07267e617cea915876b4fb1e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267844

5 years agopinctrl: add includes and ifdefs for non-DT builds
Linus Walleij [Thu, 15 Aug 2013 19:38:49 +0000]
pinctrl: add includes and ifdefs for non-DT builds

Commit e81c8f18afc4fdd6e34d8c83814b8b5134dbb30f
"pinctrl: pinconf-generic: add generic APIs for mapping pinctrl node"
Added function prototypes with implicit dependencies
on other header files causing build warnings like this:

In file included from
arch/arm/mach-ux500/board-mop500-pins.c:12:0:
include/linux/pinctrl/pinconf-generic.h:142:3:
warning: 'struct device_node' declared inside parameter list [enabled
by default]
   unsigned *reserved_maps, unsigned *num_maps);
   ^
include/linux/pinctrl/pinconf-generic.h:142:3:
warning: its scope is only this definition or declaration, which is
probably not what you want [enabled by default]
include/linux/pinctrl/pinconf-generic.h:142:3:
warning: 'struct pinctrl_dev' declared inside parameter list [enabled
by default]
include/linux/pinctrl/pinconf-generic.h:145:3:
warning: 'struct device_node' declared inside parameter list [enabled
by default]
   unsigned *num_maps);
   ^
Let's just add ifdefs for non-DT systems (the actual code is
already ifdefed) and #include <linux/device.h> to get the
most important structs and forward-declare the pinctrl
core structs.

Reported-by: Olof Johansson <olof@lixom.net>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 0d74d4a161c9f9870039af414b712552c0ed6dfb)
Change-Id: I8f0b93068af033d4255c3f34b497a7d6974d4793
Reviewed-on: http://git-master/r/267843
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: palmas: make sure disable boost during suspend for SMPS10
Laxman Dewangan [Thu, 29 Aug 2013 02:35:30 +0000]
regulator: palmas: make sure disable boost during suspend for SMPS10

If flag for SMPS10 has the disable_boost_on_suspend is true then
make sure that boost of SMPS10 is disabled.

If any regulator is using this then defer the boost disable and
disable when client actually disable the smps10.

bug 1291841

Change-Id: Ia03d29f68132f87b970d4df8402b3cdd4dba95df
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/239722
(cherry picked from commit 368abfad3a0b27fa893df2d1b201339701df367d)
Reviewed-on: http://git-master/r/267662
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: use macro in place of magic number for external control
Laxman Dewangan [Thu, 29 Aug 2013 11:38:11 +0000]
ARM: tegra: use macro in place of magic number for external control

Use macro for setting external control in place of the direct
number when populating AMS AS3722 regulator platform data.

Change-Id: Id8e00b3d6ec14b8ba3d12d1280d7a46f4e4586a9
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267919
GVS: Gerrit_Virtual_Submit

5 years agommc: tegra: Always enable calibration
Pavan Kunapuli [Wed, 28 Aug 2013 15:14:14 +0000]
mmc: tegra: Always enable calibration

Do not disable calibration unless NVQUIRK_SET_DRIVE_STRENGTH is set
which means the drive strength codes would be updated in the pad ctrl
registers and the same would be sent to the pads.

Bug 1357541

Change-Id: I2574e412859b3c2e0214ebf996f0459dcda4b139
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/267403
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: use the correct initail value for pwm_gpio
Kerwin Wan [Fri, 9 Aug 2013 08:42:04 +0000]
arm: tegra: use the correct initail value for pwm_gpio

pwm-backlight driver will check whether pwm_gpio is a valid gpio
by gpio_is_valid. If it's a valid gpio pin, it will use
it as a pwm output pin. If not, it will ignore and the pwm
output pin should be configured in board files. But pwm_gpio
is 0 by default and 0(TEGRA_GPIO_PA0) is a valid gpio.
So the pwm-backlight drvier will do gpio_request(TEGRA_GPIO_PA0)
and gpio_free(TEGRA_GPIO_PA0). This is definetly wrong.
So set pwm_gpio to TEGRA_GPIO_INVALID for those panels which
pwm output pin is set in board files to fix the wrong behavior.

Change-Id: I96e451b1f82c494731e29c09695a399d46c243b9
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/267752
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: Remove VE from pg skiplist
Terje Bergstrom [Tue, 27 Aug 2013 12:10:03 +0000]
ARM: tegra: Remove VE from pg skiplist

nvhost has a separate flag for enabling power gating for VE. Remove
VE from power gating skiplist. Fix clock list of VE domain.

Change-Id: I295f6ef3fec9f15d6644295b47545d4d3b73fc14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267117
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Enable ISP 2nd level cg
Terje Bergstrom [Tue, 27 Aug 2013 12:08:23 +0000]
video: tegra: host: Enable ISP 2nd level cg

Enable ISP's 2nd level clock gating when ISP is powered up.

Bug 1346075

Change-Id: I9c1f1f67b3ecd33b57c073ba1ae426db4985d317
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267116
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Merge runtime PM code
Terje Bergstrom [Tue, 27 Aug 2013 11:41:43 +0000]
video: tegra: host: Merge runtime PM code

Merge enabling of runtime to common code in
nvhost_module_init().

Change-Id: Iabd21b6b9c1b89d9d2fea593e693acbb29445d0b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267115
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Merge power domain code
Terje Bergstrom [Tue, 27 Aug 2013 10:20:55 +0000]
video: tegra: host: Merge power domain code

Merge different instances of power domain code into one.

Change-Id: I8ba329601c624aa66e7a4793d4bf16ae5cbf116f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267114
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Implement generic module resume
Terje Bergstrom [Tue, 27 Aug 2013 08:53:28 +0000]
video: tegra: host: Implement generic module resume

Implement generic module resume which gets called when a power domain
is turned on. Convert VIC to use the generic module resume.

Change-Id: I2a40a1a050fd38d3e793b35ac16019ee1cb5e525
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/267113
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: tn8: set LDO1 to EXT_CONTROL_NSLEEP
Hunk Lin [Wed, 28 Aug 2013 09:43:23 +0000]
ARM: tegra: tn8: set LDO1 to EXT_CONTROL_NSLEEP

LDO1 is used for PLLs. So it should be on in active use cases and off in
LP0.

Bug 1357501

Change-Id: Id77d5d3af8aec9cb2c2cb24047c198f739fa4d4d
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/267224
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: cpuidle: Attach MC clock PM on CPU0
Prashant Gaikwad [Tue, 27 Aug 2013 04:27:14 +0000]
ARM: tegra: cpuidle: Attach MC clock PM on CPU0

Attach MC clock PM with CPUIDLE driver of CPU0.When attaching the
PM with cpuidle through the API pm_genpd_attach_cpuidle,it attaches to
the curent cpu's cpuidle driver on which the code is executing.Hence
there is possiblity that it can attach to other CPUs than 0.On Tegra,
CPU0 can't  enter an idle state until all the other CPUs are idle.
Therefore, the code can be scheduled to run on CPU 0.

Bug 1331433
Bug 1355109

Change-Id: I8850fb88f328723e4a286693cfc978ca8c44ca51
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/266370
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agopinctrl: utils: include export.h to avoid warnings
Laxman Dewangan [Wed, 28 Aug 2013 12:02:15 +0000]
pinctrl: utils: include export.h to avoid warnings

Include "linux/export.h" to avoid following warnings during compilation:

/***
pinctrl/pinctrl-utils.c:53:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:53:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:53:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:70:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:70:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:70:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:98:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:98:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:98:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:122:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:122:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:122:1: warning: parameter names (without types) in function declaration [enabled by default]
pinctrl/pinctrl-utils.c:135:1: warning: data definition has no type or storage class [enabled by default]
pinctrl/pinctrl-utils.c:135:1: warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL_GPL' [-Wimplicit-int]
pinctrl/pinctrl-utils.c:135:1: warning: parameter names (without types) in function declaration [enabled by default]
**/

Change-Id: I6062ced44284ca3f692a89d6f3e74952f333ea86
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267335
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: add utility functions for add map/configs
Laxman Dewangan [Tue, 6 Aug 2013 13:12:33 +0000]
pinctrl: add utility functions for add map/configs

Some of pincontrol driver needs the utility function to create map
list. The utility function needed for adding mux, configs etc.

In place of duplicating this in each driver, add the common utility
function in common file and use from device specific driver. This will
reduce the duplicating of code across drivers.

Changes from V1:
- Add this files in this patch and add common utility APIs to here.

Changes from V2:
- Nothing in code.
- Added Reviewed by Stephen.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 1eb207a9ecaafb980704d8bc055a9a0269f62f8e)

Change-Id: I96612c3f46d3466d62fe90f518b75c132e40d771
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267318
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: pinconf-generic: add generic APIs for mapping pinctrl node
Laxman Dewangan [Tue, 6 Aug 2013 13:12:34 +0000]
pinctrl: pinconf-generic: add generic APIs for mapping pinctrl node

Add generic APIs to map the DT node and its sub node in pinconf generic
driver. These APIs can be used from driver to parse the DT node who
uses the pinconf generic APIs for defining their nodes.

Changes from V1:
- Add generic property for pins and functions in pinconf-generic.
- Add APIs to map the DT and subnode.
- Move common utils APIs to the pinctrl-utils from this file.
- Update the binding document accordingly.
Changes from V2:
- Rebased the pinctrl binding doc on top of Stephen's cleanup.
- Rename properties "pinctrl-pins" and "pinctrl-function" to
  "pins" and "function".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit e81c8f18afc4fdd6e34d8c83814b8b5134dbb30f)

Change-Id: I8bce66c1e082d8599ecac6c3440a668dfaab4c06
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267334
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: remove bindings for pinconf options needing more thought
Heiko Stübner [Tue, 25 Jun 2013 12:57:10 +0000]
pinctrl: remove bindings for pinconf options needing more thought

Some options currently take arguments in unspecified driver-specific units.
As pointed out by Stephen Warren, driver specific values should not be part
of generic devicetree bindings describing the hardware.

Therefore remove the critical bindings again, before they become part of
an official release.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 5b81d55c4ccf23b9de398f819571dfc8941c7b04)

Change-Id: I4df5788c3c14fe41e4dbf8bcecdabd32c807cc2c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267333
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: set unit for debounce time pinconfig to usec
Heiko Stübner [Tue, 25 Jun 2013 12:56:11 +0000]
pinctrl: set unit for debounce time pinconfig to usec

Currently the debounce time pinconfig option uses an unspecified
"time units" unit. As pinconfig options should use SI units and a
real unit is also necessary for generic dt bindings, change it
to usec. Currently no driver is using the generic pinconfig option
for this, so the unit change is safe to do.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 256aeb648741bf095e884793862d3dfa6b1c1fb5)

Change-Id: I9e5be7753f00881013e7d0dd84246b7bc9e86e4b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267332
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: dynamically alloc temp array when parsing dt pinconf options
Heiko Stübner [Fri, 14 Jun 2013 15:43:55 +0000]
pinctrl: dynamically alloc temp array when parsing dt pinconf options

Allocating the temorary array in pinconf_generic_parse_dt_config on stack
might cause problems later on, when the number of options grows over time.
Therefore also allocate this array dynamically to be on the safe side.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 6abab2d4bec982bcefbe99201ddee5f25227daf4)

Change-Id: I5739f8d37a6ce6c11eefc45dc38d886735e20af0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267331
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: handle zero found dt pinconfig properties better
Heiko Stübner [Fri, 14 Jun 2013 15:43:21 +0000]
pinctrl: handle zero found dt pinconfig properties better

This adds a shortcut when no valid pinconf properties are found
in the parsed dt node, to set the values immediately and return.

Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit e4a8844c04c00a1a64c6779692e1baff3851c1f7)

Change-Id: Ib7cdc320de37097b642074412c5ff3a717ac7f1c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267330
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: clarify some dt pinconfig options
Heiko Stübner [Fri, 14 Jun 2013 15:42:49 +0000]
pinctrl: clarify some dt pinconfig options

The bias-pull-* options use values > 0 to indicate that the pull should
be activated and optionally also indicate the strength of the pull.
Therefore use an default value of 1 for these options.

Split the low-power-mode option into low-power-enable and -disable.

Update the documentation to describe the param arguments better.

Reported-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 9ee1f7d266aa1e2bfeb20cb5d4ac299c8e8ef8c7)

Change-Id: I4ad03658500b7d54b8b067d79abecf3fc8b0bf70
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267329
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: add function to parse generic pinconfig properties from a dt node
Heiko Stübner [Mon, 10 Jun 2013 19:40:29 +0000]
pinctrl: add function to parse generic pinconfig properties from a dt node

pinconf_generic_parse_dt_config() takes a node as input and generates an
array of generic pinconfig values from the properties of this node.

As I couldn't find a mechanism to count the number of properties of a node
the function uses internally an array to accept one of parameter and copies
the real present options to a smaller variable at its end.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 7db9af4b6e41be599e0fcd50d687138a5add428c)

Change-Id: Ife82b86c851f354ee123cb520ea6c02ef9b025f8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267328
GVS: Gerrit_Virtual_Submit

5 years agopinctrl: add pinconf-generic define for a pin-default pull
Heiko Stübner [Thu, 6 Jun 2013 14:44:25 +0000]
pinctrl: add pinconf-generic define for a pin-default pull

There exist controllers that don't support to set the pull to up or down
separately but instead automatically set the pull direction based on
embedded knowledge inside the controller, for example depending on the
selected mux function of the pin.

Therefore this patch adds another config option to use this default
pull-state for a pin where it is not possible to know or decide if the
pin will be pulled up or down.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 7970cb770dffa23cb20a36f46602e688e075f5d9)

Change-Id: Ibdf32c6fc52f55c31f940ed472a268e3cdc34425
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267327
GVS: Gerrit_Virtual_Submit

5 years agopinconf-generic: add BIAS_BUS_HOLD pinconf
James Hogan [Fri, 24 May 2013 16:21:12 +0000]
pinconf-generic: add BIAS_BUS_HOLD pinconf

Add a new PIN_CONFIG_BIAS_BUS_HOLD pin configuration for a bus holder
pin mode (also known as bus keeper, or repeater). This is a weak latch
which drives the last value on a tristate bus. Another device on the bus
can drive the bus high or low before going tristate to change the value
driven by the pin.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit a2df4269cad79635201587c5c5404f0b1cb0b05c)

Change-Id: I4b5e1b54008b09cbcd9d911cb3e671d06a25badd
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267326
GVS: Gerrit_Virtual_Submit

5 years agopinconf-generic: add drive strength to debugfs output
James Hogan [Fri, 24 May 2013 16:21:11 +0000]
pinconf-generic: add drive strength to debugfs output

Add the drive strength pinconf to debugfs output (with the unit "mA").

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 73ae368cd309dae277b66444d471ac62825ee407)

Change-Id: Ia90dad63f1fad74b7f76a8dba22d26cae1cd66ba
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267325
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: Move from video/tegra to platform/tegra
Ajay Nandakumar [Tue, 16 Jul 2013 08:02:18 +0000]
video: tegra: Move from video/tegra to platform/tegra

Moving the drivers/media/video/tegra to drivers/media/platform/tegra.
This is done with respect with the upstream version of kernel 3.8.

Bug 1319074

Change-Id: Id30bc8616ed77aa7777394e153330969647112ed
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/267209
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agosecurity: tlk_driver: Use CPU0 for smc calls
James Zhao [Tue, 20 Aug 2013 01:41:47 +0000]
security: tlk_driver: Use CPU0 for smc calls

- All smc calls need to be done through CPU0.
- Add the sched_setaffinity logic to tlk_generic_smc(), will solve
  the occasional prefetch abort.
- Also adding sched_setaffinity logic to tlk_extended_smc().

bug 1322280

Change-Id: I67716bec49aec1f1c9a2e33ec3de90aec2048870
Signed-off-by: James Zhao <jamesz@nvidia.com>
Signed-off-by: Aaron Gamble <jgamble@nvidia.com>
Reviewed-on: http://git-master/r/264177
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Johnson <cwj@nvidia.com>
Tested-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

5 years agovideo: tegra: nvmap: Set nvmap DMA parameters
Alex Waterman [Wed, 28 Aug 2013 21:37:27 +0000]
video: tegra: nvmap: Set nvmap DMA parameters

This makes sure the DMA mapping API does not split passed buffers
into multiple IO maps.

Change-Id: Icacaedd410faf83e264694ce4293f5f7ef236341
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/267560
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: dc: Set dma parameters
Alex Waterman [Wed, 28 Aug 2013 21:29:09 +0000]
video: tegra: dc: Set dma parameters

For usage with the DMA API the DC driver must specify DMA max
segment size parameter.

Change-Id: I59661c81239fee4b51d61b29ae782515a73a13e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/267559
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agotegra: of: enable HDMI output for t114 boards
Alexandre Courbot [Wed, 28 Aug 2013 07:23:04 +0000]
tegra: of: enable HDMI output for t114 boards

HDMI node is disabled by default. Enable it for boards that have a HDMI
output.

Bug 1332618.

Change-Id: I16fdb062845b2e2248d39413295736414749ca6d
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/267130
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: clock: Combine bus cap/floor callbacks
Alex Frid [Wed, 28 Aug 2013 06:11:23 +0000]
ARM: tegra: clock: Combine bus cap/floor callbacks

Used common callbacks for shared bus cap and floor sysfs show/store
operations, and PM QoS notifier. Only final bus user update operation
is different, since applying floor implies that shared bus should be
enabled, while cap does not require it.

As a result of this refactoring PM QoS optional support implemented
for bus caps become available for bus floors as well.

Change-Id: I6cfa79b8f203f40dd69772199dabb7da73c4ba2a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/267533
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Expand clock stats
Alex Frid [Wed, 28 Aug 2013 20:18:54 +0000]
ARM: tegra12: clock: Expand clock stats

Added to clock statistic new shared buses: c4bus (VI/ISP) and
gbus (gk20a).

Bug 1349649
Bug 1357006

Change-Id: I1063137df22838ee52dc4797a194ad862146be6d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/267516
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Don't select dynamic cbus
Alex Frid [Wed, 28 Aug 2013 19:53:27 +0000]
ARM: tegra12: clock: Don't select dynamic cbus

Removed dynamic cbus option from Tegra12 configuration - not needed,
static cbus works fine per characterization.

Change-Id: Iea936b85df88338ac2a4d4c4da4a738372f2961d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/267515
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: fb: Add LPAE support for FB driver
Chao Xu [Fri, 23 Aug 2013 17:30:05 +0000]
video: tegra: fb: Add LPAE support for FB driver

Bug 1341658

Change-Id: I14b54505382cf2aa671c588bda4e48c200f46b8f
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/265623
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: nvmap: remove unused nvmap_pin_array
Krishna Reddy [Wed, 28 Aug 2013 21:18:20 +0000]
video: tegra: nvmap: remove unused nvmap_pin_array

remove unused nvmap_pin_array API.

Change-Id: I33d96c327decfc79a36efd51503ed9bb6956b9b9
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/267545
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: Use correct device pointer
Alex Waterman [Tue, 27 Aug 2013 19:43:28 +0000]
video: tegra: dc: Use correct device pointer

Pass the correct device to dmabuf API which is the dc platform
device. This causes the correct IOMMU DMA operations to be used
thereby generating mappings in the tegra SMMU.

Change-Id: I64904f31b836773ae2bc61e0bf0103b8a91bc40f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/266893
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: config: removed incorrectly applied errata
Matt Craighead [Wed, 28 Aug 2013 18:30:47 +0000]
arm: config: removed incorrectly applied errata

Bug 1349683

Change-Id: I86f97e07157f6aa42cfc22fe0c7cbf53375e6f4c
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/267460
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: tegra: allow disabling HDMI through DT
Alexandre Courbot [Tue, 12 Mar 2013 06:42:40 +0000]
ARM: tegra: allow disabling HDMI through DT

HDMI output can be disabled by setting the "host1x/hdmi" node's status
to disabled. Also factorizes the common HDMI initialization code to one
place.

Bug 1239870
Bug 1332618

Change-Id: I34f8d3cfdcc205b640b4294e8cfc38449484d6ba
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/208311
Reviewed-on: http://git-master/r/263200
(cherry picked from commit c0b71f030335bf33c0aaa227c139f4ce056950bb)
(cherry picked from commit fcaff7edf54611d085b2f21f9674fd1e58bc4f46)
Reviewed-on: http://git-master/r/263764
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Tested-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: make VBUS-ENx gpio to open drain type
Laxman Dewangan [Wed, 28 Aug 2013 10:25:01 +0000]
ARM: tegra: make VBUS-ENx gpio to open drain type

The VBUS-ENx are bidirectional gpio and it should not be
driver high in output mode, it should be set high by
enabling Pull up and setting this as gpio-input mode.

Making these pins as open drain type.

Change-Id: Ib6218958211c928c97ea07a344435aee257fb2c3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267241
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: remove pinmux-tegra11x header for T124 platform
Laxman Dewangan [Wed, 28 Aug 2013 10:23:42 +0000]
ARM: tegra: remove pinmux-tegra11x header for T124 platform

T114 support is removed from the T124 platforms and hence removing
their pinmux files also.

Change-Id: I5fdc9c874392be8c9ae0e269b45b8eab020e78d8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/267240
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clk: Always enable common XUSB gate
Krishna Yarlagadda [Tue, 27 Aug 2013 12:36:55 +0000]
ARM: tegra12: clk: Always enable common XUSB gate

Added separate common XUSB gate clock. It has to be always enabled,
so that h/w sequencers that automatically control XUSB operations can
properly work.

Bug 1320271

Change-Id: I6a9d51bf8821b6010ed03a5974f1065b22e1988f
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/266755
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: defconfig: enable USB_VIDEO_CLASS
Naveen Kumar Rai [Tue, 20 Aug 2013 11:39:41 +0000]
ARM: defconfig: enable USB_VIDEO_CLASS

This is on dalmore. Ardbeg already has this enabled.

Bug 1333188

Change-Id: I3885a6e0459f1212b1e3e439ef1df2adab80776d
Signed-off-by: Naveen Kumar Rai <nkumarrai@nvidia.com>
Reviewed-on: http://git-master/r/263868
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM mm: memcg: do not trap chargers with full callstack on OOM
Johannes Weiner [Thu, 8 Aug 2013 02:56:33 +0000]
UPSTREAM mm: memcg: do not trap chargers with full callstack on OOM

The memcg OOM handling is incredibly fragile and can deadlock.  When a
task fails to charge memory, it invokes the OOM killer and loops right
there in the charge code until it succeeds.  Comparably, any other task
that enters the charge path at this point will go to a waitqueue right
then and there and sleep until the OOM situation is resolved.  The problem
is that these tasks may hold filesystem locks and the mmap_sem; locks that
the selected OOM victim may need to exit.

For example, in one reported case, the task invoking the OOM killer was
about to charge a page cache page during a write(), which holds the
i_mutex.  The OOM killer selected a task that was just entering truncate()
and trying to acquire the i_mutex:

OOM invoking task:
[<ffffffff8110a9c1>] mem_cgroup_handle_oom+0x241/0x3b0
[<ffffffff8110b5ab>] T.1146+0x5ab/0x5c0
[<ffffffff8110c22e>] mem_cgroup_cache_charge+0xbe/0xe0
[<ffffffff810ca28c>] add_to_page_cache_locked+0x4c/0x140
[<ffffffff810ca3a2>] add_to_page_cache_lru+0x22/0x50
[<ffffffff810ca45b>] grab_cache_page_write_begin+0x8b/0xe0
[<ffffffff81193a18>] ext3_write_begin+0x88/0x270
[<ffffffff810c8fc6>] generic_file_buffered_write+0x116/0x290
[<ffffffff810cb3cc>] __generic_file_aio_write+0x27c/0x480
[<ffffffff810cb646>] generic_file_aio_write+0x76/0xf0           # takes ->i_mutex
[<ffffffff8111156a>] do_sync_write+0xea/0x130
[<ffffffff81112183>] vfs_write+0xf3/0x1f0
[<ffffffff81112381>] sys_write+0x51/0x90
[<ffffffff815b5926>] system_call_fastpath+0x18/0x1d
[<ffffffffffffffff>] 0xffffffffffffffff

OOM kill victim:
[<ffffffff811109b8>] do_truncate+0x58/0xa0              # takes i_mutex
[<ffffffff81121c90>] do_last+0x250/0xa30
[<ffffffff81122547>] path_openat+0xd7/0x440
[<ffffffff811229c9>] do_filp_open+0x49/0xa0
[<ffffffff8110f7d6>] do_sys_open+0x106/0x240
[<ffffffff8110f950>] sys_open+0x20/0x30
[<ffffffff815b5926>] system_call_fastpath+0x18/0x1d
[<ffffffffffffffff>] 0xffffffffffffffff

The OOM handling task will retry the charge indefinitely while the OOM
killed task is not releasing any resources.

A similar scenario can happen when the kernel OOM killer for a memcg is
disabled and a userspace task is in charge of resolving OOM situations.
In this case, ALL tasks that enter the OOM path will be made to sleep on
the OOM waitqueue and wait for userspace to free resources or increase the
group's limit.  But a userspace OOM handler is prone to deadlock itself on
the locks held by the waiting tasks.  For example one of the sleeping
tasks may be stuck in a brk() call with the mmap_sem held for writing but
the userspace handler, in order to pick an optimal victim, may need to
read files from /proc/<pid>, which tries to acquire the same mmap_sem for
reading and deadlocks.

This patch changes the way tasks behave after detecting a memcg OOM and
makes sure nobody loops or sleeps with locks held:

1. When OOMing in a user fault, invoke the OOM killer and restart the
   fault instead of looping on the charge attempt.  This way, the OOM
   victim can not get stuck on locks the looping task may hold.

2. When OOMing in a user fault but somebody else is handling it
   (either the kernel OOM killer or a userspace handler), don't go to
   sleep in the charge context.  Instead, remember the OOMing memcg in
   the task struct and then fully unwind the page fault stack with
   -ENOMEM.  pagefault_out_of_memory() will then call back into the
   memcg code to check if the -ENOMEM came from the memcg, and then
   either put the task to sleep on the memcg's OOM waitqueue or just
   restart the fault.  The OOM victim can no longer get stuck on any
   lock a sleeping task may hold.

Debugged by Michal Hocko.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Reported-by: azurIt <azurit@pobox.sk>
Acked-by: Michal Hocko <mhocko@suse.cz>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
(cherry picked from commit fdb134a97c437a513d8587a78ca8f0c2291a3c8a)
Change-Id: Ifb7c4c5688d1c4bb5c0ff71e1672b4ff3fb424f1
Reviewed-on: http://git-master/r/266407
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM mm: memcg: rework and document OOM waiting and wakeup
Johannes Weiner [Thu, 8 Aug 2013 02:56:33 +0000]
UPSTREAM mm: memcg: rework and document OOM waiting and wakeup

The memcg OOM handler open-codes a sleeping lock for OOM serialization
(trylock, wait, repeat) because the required locking is so specific to
memcg hierarchies.  However, it would be nice if this construct would be
clearly recognizable and not be as obfuscated as it is right now.  Clean
up as follows:

1. Remove the return value of mem_cgroup_oom_unlock()

2. Rename mem_cgroup_oom_lock() to mem_cgroup_oom_trylock().

3. Pull the prepare_to_wait() out of the memcg_oom_lock scope.  This
   makes it more obvious that the task has to be on the waitqueue
   before attempting to OOM-trylock the hierarchy, to not miss any
   wakeups before going to sleep.  It just didn't matter until now
   because it was all lumped together into the global memcg_oom_lock
   spinlock section.

4. Pull the mem_cgroup_oom_notify() out of the memcg_oom_lock scope.
   It is proctected by the hierarchical OOM-lock.

5. The memcg_oom_lock spinlock is only required to propagate the OOM
   lock in any given hierarchy atomically.  Restrict its scope to
   mem_cgroup_oom_(trylock|unlock).

6. Do not wake up the waitqueue unconditionally at the end of the
   function.  Only the lockholder has to wake up the next in line
   after releasing the lock.

   Note that the lockholder kicks off the OOM-killer, which in turn
   leads to wakeups from the uncharges of the exiting task.  But a
   contender is not guaranteed to see them if it enters the OOM path
   after the OOM kills but before the lockholder releases the lock.
   Thus there has to be an explicit wakeup after releasing the lock.

7. Put the OOM task on the waitqueue before marking the hierarchy as
   under OOM as that is the point where we start to receive wakeups.
   No point in listening before being on the waitqueue.

8. Likewise, unmark the hierarchy before finishing the sleep, for
   symmetry.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Acked-by: Michal Hocko <mhocko@suse.cz>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: azurIt <azurit@pobox.sk>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
(cherry picked from commit f75dd54204e9078dabad2b53ab4fa638c9cfd4cc)
Change-Id: Ic1d2bb06cb31cbe8c9062a93f33220115e3a1d0e
Reviewed-on: http://git-master/r/266406
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM mm: memcg: enable memcg OOM killer only for user faults
Johannes Weiner [Thu, 8 Aug 2013 02:56:32 +0000]
UPSTREAM mm: memcg: enable memcg OOM killer only for user faults

System calls and kernel faults (uaccess, gup) can handle an out of memory
situation gracefully and just return -ENOMEM.

Enable the memcg OOM killer only for user faults, where it's really the
only option available.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Acked-by: Michal Hocko <mhocko@suse.cz>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: azurIt <azurit@pobox.sk>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
(cherry picked from commit 31d1d8b2aa8733b4fe221b4bcbaa15aec3582b99)
Change-Id: If84752f6c46e464bc0d1d868ac543497425ba7cc
Reviewed-on: http://git-master/r/266405
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM arch: mm: pass userspace fault flag to generic fault handler
Prashant Gaikwad [Mon, 12 Aug 2013 10:39:13 +0000]
UPSTREAM arch: mm: pass userspace fault flag to generic fault handler

Unlike global OOM handling, memory cgroup code will invoke the OOM killer
in any OOM situation because it has no way of telling faults occuring in
kernel context - which could be handled more gracefully - from
user-triggered faults.

Pass a flag that identifies faults originating in user space from the
architecture-specific fault handlers to generic code so that memcg OOM
handling can be improved.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Reviewed-by: Michal Hocko <mhocko@suse.cz>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: azurIt <azurit@pobox.sk>
Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
(cherry picked from commit 407c454cb0ac6e68ca66974da787a71118cfef84)

Conflicts:

arch/arc/mm/fault.c
arch/arm64/mm/fault.c
arch/metag/mm/fault.c
arch/parisc/mm/fault.c

Change-Id: Iee53942737627be8dd8e2e325b5ba87fe85d6814
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/266410
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM arch: mm: remove obsolete init OOM protection
Prashant Gaikwad [Mon, 12 Aug 2013 10:33:22 +0000]
UPSTREAM arch: mm: remove obsolete init OOM protection

The memcg code can trap tasks in the context of the failing allocation
until an OOM situation is resolved.  They can hold all kinds of locks (fs,
mm) at this point, which makes it prone to deadlocking.

This series converts memcg OOM handling into a two step process that is
started in the charge context, but any waiting is done after the fault
stack is fully unwound.

Patches 1-4 prepare architecture handlers to support the new memcg
requirements, but in doing so they also remove old cruft and unify
out-of-memory behavior across architectures.

Patch 5 disables the memcg OOM handling for syscalls, readahead, kernel
faults, because they can gracefully unwind the stack with -ENOMEM.  OOM
handling is restricted to user triggered faults that have no other option.

Patch 6 reworks memcg's hierarchical OOM locking to make it a little more
obvious wth is going on in there: reduce locked regions, rename locking
functions, reorder and document.

Patch 7 implements the two-part OOM handling such that tasks are never
trapped with the full charge stack in an OOM situation.

This patch:

Back before smart OOM killing, when faulting tasks were killed directly on
allocation failures, the arch-specific fault handlers needed special
protection for the init process.

Now that all fault handlers call into the generic OOM killer (609838c "mm:
invoke oom-killer from remaining unconverted page fault handlers"), which
already provides init protection, the arch-specific leftovers can be
removed.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Reviewed-by: Michal Hocko <mhocko@suse.cz>
Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: azurIt <azurit@pobox.sk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
(cherry picked from commit c5659bca566f8b4798a34c0bf19b7afd0bfa706e)

Conflicts:

arch/arc/mm/fault.c

Change-Id: I8807370a955f5a730832db8a86eb8dade81be251
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/266409
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM mm: invoke oom-killer from remaining unconverted page fault handlers
Prashant Gaikwad [Mon, 12 Aug 2013 10:32:28 +0000]
UPSTREAM mm: invoke oom-killer from remaining unconverted page fault handlers

A few remaining architectures directly kill the page faulting task in an
out of memory situation.  This is usually not a good idea since that
task might not even use a significant amount of memory and so may not be
the optimal victim to resolve the situation.

Since 2.6.29's 1c0fe6e ("mm: invoke oom-killer from page fault") there
is a hook that architecture page fault handlers are supposed to call to
invoke the OOM killer and let it pick the right task to kill.  Convert
the remaining architectures over to this hook.

To have the previous behavior of simply taking out the faulting task the
vm.oom_kill_allocating_task sysctl can be set to 1.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Reviewed-by: Michal Hocko <mhocko@suse.cz>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Acked-by: David Rientjes <rientjes@google.com>
Acked-by: Vineet Gupta <vgupta@synopsys.com> [arch/arc bits]
Cc: James Hogan <james.hogan@imgtec.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Cc: Lennox Wu <lennox.wu@gmail.com>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
(cherry picked from commit 609838cfed972d49a65aac7923a9ff5cbe482e30)

Conflicts:

arch/arc/mm/fault.c
arch/metag/mm/fault.c

Change-Id: I3a9435be0bd4b8ea43cefd87ca8d408201ae3bf1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/266408
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoUPSTREAM arch: mm: do not invoke OOM killer on kernel fault OOM
Johannes Weiner [Thu, 8 Aug 2013 02:56:30 +0000]
UPSTREAM arch: mm: do not invoke OOM killer on kernel fault OOM

Kernel faults are expected to handle OOM conditions gracefully (gup,
uaccess etc.), so they should never invoke the OOM killer.  Reserve this
for faults triggered in user context when it is the only option.

Most architectures already do this, fix up the remaining few.

Signed-off-by: Johannes Weiner <hannes@cmpxchg.org>
Reviewed-by: Michal Hocko <mhocko@suse.cz>
Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: David Rientjes <rientjes@google.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: azurIt <azurit@pobox.sk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Change-Id: Id58a8ebe3ee619ef9ae3590b5788823fa6bd2dce
Reviewed-on: http://git-master/r/266404
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agommc: tegra: Set pu,pd offsets for T148 SDMMC
Naveen Kumar Arepalli [Wed, 28 Aug 2013 05:57:28 +0000]
mmc: tegra: Set pu,pd offsets for T148 SDMMC

-Set pu,pd offsets for T148 SDMMC.
-Program pu,pd offset values to 2.

Bug 1333552

Change-Id: I61f17949e8c4da5e7b6044027769a9a437339e52
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/267086
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agodma: tegra: Use runtime_pm for enabling/disabling clock
Chaitanya Bandi [Tue, 27 Aug 2013 14:48:12 +0000]
dma: tegra: Use runtime_pm for enabling/disabling clock

Used runtime pm APIs for clock enabling/disabling and
also made changes such that clock is not enabled during
idle.

Bug 1326667

Change-Id: I7cf478006e11b3a63271c8c7b0a8f0e9406cbbca
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/265931
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoi2c: tegra: Add debug prints for i2c timed out case
Chaitanya Bandi [Mon, 26 Aug 2013 11:22:28 +0000]
i2c: tegra: Add debug prints for i2c timed out case

Added debug prints for i2c timed out case to
help debug.

Change-Id: I9b8b66acdc80b9bbddbf9d824d7fbd71fa602460
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/266034
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: pm: Add tegra-apbdma to MC clock power domain
Chaitanya Bandi [Tue, 27 Aug 2013 06:18:36 +0000]
ARM: tegra: pm: Add tegra-apbdma to MC clock power domain

Added tegra-apbdma device to MC clock power domain.

Bug 1326667

Change-Id: Iae1433280f79c3b50cb9e7e08fd324fdbf9a302e
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/266459
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>