5 years agoarm: thermal: Removed nonTEGRA_THERMAL_SYSFS logic
Joshua Primero [Thu, 17 May 2012 19:17:15 +0000]
arm: thermal: Removed nonTEGRA_THERMAL_SYSFS logic

All throttling must go through the Linux thermal sysfs
framework now.

Change-Id: Ia871e0b06e548d5d82211a65979bea52a6c28fb0
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/103183
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rbd09e37b3a08e19d75a82bf06ae2632436529efc

5 years agoarm: tegra: thermal: removed TEGRA_THERMAL_SYSFS
Joshua Primero [Thu, 17 May 2012 19:19:01 +0000]
arm: tegra: thermal: removed TEGRA_THERMAL_SYSFS

Removed the CONFIG_TEGRA_THERMAL_SYSFS option. Any
throttling activities must go through the Linux
thermal sysfs framework now via CONFIG_THERMAL.

Change-Id: Ibe680d82d3225994e6bebcfe75a0f058e567e35c
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/103182
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

arch/arm/mach-tegra/Kconfig

Rebase-Id: R5b4a4423d562fb9bef6fb6900b76d3935ecb224e

5 years agoARM: tegra: pcie: Fix for second pcie port detection.
Manoj Chourasia [Fri, 11 May 2012 13:14:42 +0000]
ARM: tegra: pcie: Fix for second pcie port detection.

PCIE card on second port doesn't get detected if the first
port is empty. If the link for first port is reset and the
second port is queried for card, it doesn't get detected.

Fix for the issue is do not reset the link if the port is
not detected in third attempt.

bug 970206

Change-Id: I4e4d32c22697b817381834ac746417437016d7f3
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/101986
(cherry picked from commit c085f6b1b3a77b7aae3b04e22c7a9bfed8517c1e)
Reviewed-on: http://git-master/r/103077
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R1d3b28c962276d16d82bad0670699927001d154d

5 years agoarm:tegra:pcie: Resolve section mismatch warning
Jay Agarwal [Thu, 17 May 2012 12:25:29 +0000]
arm:tegra:pcie: Resolve section mismatch warning

Bug 984434

Change-Id: I7184fc77132485ab24357e5f2c965ddf4eca6a07
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/103112
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R1a7a7f82327723234a0f25469a1eecfdd60d53e0

5 years agoARM: tegra: emc: add eack_disable functionality
Ray Poudrier [Fri, 2 Mar 2012 00:35:11 +0000]
ARM: tegra: emc: add eack_disable functionality

Bug 946110

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>

Change-Id: I0d4c716c4ab7a60011018d6c13be4265cc9f7290
Reviewed-on: http://git-master/r/87061
(cherry picked from commit a7dad880dcea36fcb8223cf0b34cc1091d725a9f)
Reviewed-on: http://git-master/r/102360
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R2a3875bc982b2e6218188f3bf9259c37d2913b54

5 years agoARM: tegra: power: Don't enable auto-hotplug as PM QoS side-effect
Alex Frid [Tue, 27 Mar 2012 19:19:52 +0000]
ARM: tegra: power: Don't enable auto-hotplug as PM QoS side-effect

On Tegra3, if PM QoS hotplug request is received when auto-hotplug
is disabled, do not enable auto-hotplug as side effect of the
request.

Change-Id: I8928d9ecd22e2d2df5fe60274fed30da0c565b47
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/102118
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Ra1d07bbb1c2a66394b0a66347ece3c41dde1db80

5 years agoArm: p1852: dvfs: Added ASIC SKUs as per updated POR
Mohit Kataria [Fri, 11 May 2012 05:30:18 +0000]
Arm: p1852: dvfs: Added ASIC SKUs as per updated POR

Automotive platforms are broken down further into 5 Asic skus from
3 ASIC SKUs, updated kernel to reflect these changes.

Bug 983555

Change-Id: I75925c5853d4ec2a5c72e430f4c2380e58aae774
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/101903
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rbf24c8f127a24bbef6232d1c8d034c816a9f17a9

5 years agoarm: tegra: pm: remove duplicate cpu pm calls
Mayuresh Kulkarni [Tue, 15 May 2012 08:52:18 +0000]
arm: tegra: pm: remove duplicate cpu pm calls

- cpu_pm_enter() & cpu_cluster_pm_enter() are called by
cpu_pm_suspend() in kernel/kernel/cpu_pm.c using syscore
notifier
- similarly, cpu_cluster_pm_exit() & cpu_pm_exit() are
are called by cpu_pm_resume()
- so no need for platform implementation to call them
explicitly

Change-Id: I188293403f4e714aee668f37584da8fb2deaf117
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/102530
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rd082b2903001011b7d66bddef107a1ed8aad9bfe

5 years agoARM: tegra: pm: suspend trace event
Sivaram Nair [Wed, 9 May 2012 16:51:38 +0000]
ARM: tegra: pm: suspend trace event

A new trace event is added for tracing cpu suspend start and end

Change-Id: I2506e3aed0692c44fb4325e9d381cea53228b0c3
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/101748
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R086f9958d0908673b654d8de521bc57422116283

5 years agoARM: tegra: clock: Export clock minimum
Antti P Miettinen [Wed, 9 May 2012 16:57:01 +0000]
ARM: tegra: clock: Export clock minimum

Add clock minimum to debugfs.

Bug 917644

Change-Id: Ie088809829af2bdc81a969a034bf00847459f0ce
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/101555
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R61b1f90e8fff742ce14175a87dea4f81cd58e614

5 years agoARM: tegra: Correction of safe option
Ashwini Ghuge [Tue, 15 May 2012 11:03:32 +0000]
ARM: tegra: Correction of safe option

Corrected safe option for LPW0 and LPW2

Bug 920686

Reviewed-on: http://git-master/r/101973
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Change-Id: If2077d60f1a79bd7c526a8d9a811a4634f26d482

Rebase-Id: R4d034d787509b8836e7dbd6092276f537ff0ac95

5 years agoARM: tegra: power: Apply down delay to balancing CPUs
Alex Frid [Sun, 29 Apr 2012 06:25:39 +0000]
ARM: tegra: power: Apply down delay to balancing CPUs

On Tegra3 secondary G-CPU may be turned off by auto-hotplug governor
in two cases: when overall CPU load is low enough to justify transition
to LP CPU, or when CPU cores usage by the scheduler is unbalanced
(skewed). In the former case down delay (currently 2sec) was inserted
before the core is turned Off. In the latter case the up delay (100ms)
was used, i.e., the same delay applied to balancing cores regardless
of the On/Off direction.

This commit would apply down delay when turning core Off in both cases
above, and keep using up delay only for turning core On.

Change-Id: Id545f8d48cbf380e24824a5adfe045ff68c1f39c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99708
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R543994e4e2637afd49638c04db1deeeb741c3a26

5 years agoARM: tegra: clock: Add locked version of round rate
Alex Frid [Sun, 18 Mar 2012 06:38:07 +0000]
ARM: tegra: clock: Add locked version of round rate

Add locked version of round rate API to be used by tegra arch
specific layer.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 457627966b91f2141439812869adc4acf9242471)

Change-Id: Id68d0bb952d1e7d9e650341872d1b06b0b2d3cea
Reviewed-on: http://git-master/r/100474
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rcc373d9c638b77d8fe54e650e558ea6c4c7ba92c

5 years agoarm: tegra: pl310: Enable dynamic clock gating and standy.
Krishna Reddy [Mon, 14 May 2012 10:20:55 +0000]
arm: tegra: pl310: Enable dynamic clock gating and standy.

Bug 947861

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/100462
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Change-Id: I9770a96622e37176322c2941e665e5e677a5c8ed

Rebase-Id: R170f84262031614cf298e87ebf01a66e3c311307

5 years agoarm: tegra: scu: Enable IC and SCU standby
Krishna Reddy [Fri, 4 May 2012 02:02:04 +0000]
arm: tegra: scu: Enable IC and SCU standby

Bug 947861

Change-Id: I1ac97b5de5e7e79a418b3c38c70df4976616cdf3
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/100457
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R7d702046b68e7e2e5ee36f1ceca5779ac5cd982d

5 years agoARM: tegra: Export tegra_powergate_is_powered()
Antti P Miettinen [Thu, 19 Apr 2012 21:14:01 +0000]
ARM: tegra: Export tegra_powergate_is_powered()

Export tegra_powergate_is_powered() for use by modules.

Change-Id: I8cfbb8aeb95dca00cbf6ef0c8c2bd189afeb62b6
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/97724
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc58f8bea2d4211cb45806a8380823efc9267ac9b

5 years agoARM: tegra: Enable ARM errata 716044 for Tegra2.
Krishna Reddy [Wed, 11 Apr 2012 18:23:25 +0000]
ARM: tegra: Enable ARM errata 716044 for Tegra2.

Change-Id: Id71da6f6371f337f913d981f6d121c3fb2561a41
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/95915
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R47f53be16717f1eda20ac0a5fee7c2e173d5612d

5 years agoarm: tegra: Implement safe option for T30 pinmux
Ashwini Ghuge [Mon, 14 May 2012 09:34:37 +0000]
arm: tegra: Implement safe option for T30 pinmux

Bug 950086

Change-Id: I2eb129566bfea83b9a73d29f0c6443bdab087b65
Reviewed-on: http://git-master/r/95518
Reviewed-by: Andy Park <andyp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>

Rebase-Id: R725a7c028188224599658d66296f6e3e4c5b89b8

5 years agoARM: tegra: pinmux: fix dbg_pinmux_show routine
Varun Wadekar [Mon, 7 May 2012 12:05:14 +0000]
ARM: tegra: pinmux: fix dbg_pinmux_show routine

e4b9a093889311aac9a54b6bd55f255fd482ffda added support to consider reg_base
of zero as valid.

Add the same support in debugfs' _show routine so that all the pinmux
registers are displayed when we do "cat /d/tegra_pinmux"

Change-Id: Ia4eeaf808c5f853db96a2d118d308e072dbc38f4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/100926
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Rd43e93a31c618cdd0aec4119d1158a2a4bd040f6

5 years agoARM: tegra: power: Enforce CPU rate range in min cpu notifier
Alex Frid [Fri, 20 Apr 2012 06:04:28 +0000]
ARM: tegra: power: Enforce CPU rate range in min cpu notifier

On Tegra3 make sure cpu rate is within G-mode range before LP to G
mode switch triggered by minimum CPUs notifier.

Bug 964208

Change-Id: Ic4ee6bc7eca5ad0902da4907e4702f296a155280
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99834
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R0304730b68194b33428a822a4c9d8aa0c448d529

5 years agogpio: tegra: implement gpio_request and gpio_free.
Laxman Dewangan [Tue, 24 Apr 2012 13:33:26 +0000]
gpio: tegra: implement gpio_request and gpio_free.

Recent pinctrl discussions concluded that gpiolib APIs
should in fact do whatever is required to mux a GPIO onto
pins.
This change is based on the work done by Stephen Warren in mainline
kernel.
-----
commit 3e215d0a19c2a0c389bd9117573b6dd8e46f96a8

    gpio: tegra: Hide tegra_gpio_enable/disable()

    Recent pinctrl discussions concluded that gpiolib APIs should in fact do
    whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
    required. This change implements this for the Tegra GPIO driver, and removes
    calls to the Tegra-specific APIs from drivers and board files.
----

Change-Id: I482ea5c177cf2ee6fa06ddac48b556f1508efacb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98466
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: R10296d028dc9fe13da347dc93a215cfeb49170e3

5 years agoARM: tegra: add powergating trace event
Peter De Schrijver [Fri, 27 Apr 2012 13:52:16 +0000]
ARM: tegra: add powergating trace event

Add a trace event for powergating. The existing power_domain_target is used.
state 0 is used for off and state 1 is used for on. This patch only traces
non CPU domains. The powerstate of CPU domains is already traced using
power_start events.

bug 976845

Change-Id: Ic9503f7b42b35c0bf70c7b64a7f15c4960637200
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/99416
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R97c6eeec3d158631fa968b194cc0fdcab724deab

5 years agousb: cdc_ether: Add new product id for the 5AE profile
Jonathan Roux [Tue, 24 Jan 2012 15:33:16 +0000]
usb: cdc_ether: Add new product id for the 5AE profile

Bug 924863

Change-Id: I10d3036ce19f8c1f37e57998c204f3a72bd42f85
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/89718
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Rbaaeeadc87c82cde7eba4fb8a212b8c49c6f759a

5 years agotracing: Add tracepoints for cluster switch
Antti P Miettinen [Mon, 2 Apr 2012 11:27:21 +0000]
tracing: Add tracepoints for cluster switch

Simple trace points for measuring cluster switch latencies.

Bug 958262

Change-Id: Ia1e5e13131d5e55aaa0a44e9e8b5196539df54e7
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/93841
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R377085ebb9f8be01f3b80c66075d613ed3907030

5 years agoarm: tegra: pm: use writel instead pmc_32kwritel
Shridhar Rasal [Wed, 18 Apr 2012 04:49:57 +0000]
arm: tegra: pm: use writel instead pmc_32kwritel

For update of PMC_CTRL register delay is not required.
Replacing pmc_32kwritel by writel to improve cluster switch time.

bug 954247

Change-Id: Ic39c6fafd606321d549cf26e4cfe662f462b9bdc
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/97229
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R8d7585acfcc872520e7e16ba001713bbcd826be1

5 years agoarm: tegra: pinmux: treat reg base = 0 valid
Mayuresh Kulkarni [Thu, 3 May 2012 13:49:19 +0000]
arm: tegra: pinmux: treat reg base = 0 valid

- master SoC pinmux table subtracts the reg base (for mux, tri-state &
pull-up/down). this is because, its platform data/device tree binding
adds APB base with the reg base
- however, pinmux driver has checks which results in treating reg base of
0 as invalid. thus, during boot-up pinmux/tristate/pull-up/down
registers are not set correctly as per the setting in board file
- as a result, settings are good for base regs != 0 & hence some things work
while others not
- this is revert of commit 8791f084fb6ebbd8ba2ca1c8c09cfaba1fde88c6
as the master SoC pin-mux table format is changed

bug 974063

Change-Id: Ib254022e3693ffbbafcd475eaeaddc663f6c27df
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/100344
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R740cffb526eed9611099d1dd26ca77ee68283fc5

5 years agoARM: tegra: pcie: fix pcie resume issue
Shridhar Rasal [Wed, 11 Apr 2012 10:54:47 +0000]
ARM: tegra: pcie: fix pcie resume issue

Its observed that PCIE all clocks enabled on resume.
Follow up resume and suspend only if any port added

bug 943712

Change-Id: I0644aad8a4994726451cda094f2607eb8398aadf
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/95836
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rae545ed33e04403d3202244883906f71650dc573

5 years agoARM: tegra: provide fixed mapping for PCIe host
Peter De Schrijver [Wed, 25 Apr 2012 12:43:57 +0000]
ARM: tegra: provide fixed mapping for PCIe host

Provide a fixed mapping for the PCIe host registers. This reduces the pressure
on the VMALLOC area significantly.

bug 969392

Change-Id: I80ea0dd5e81a005f86a26eb47aea00d78e9e0ad2
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/96748
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:

arch/arm/mach-tegra/include/mach/io.h

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R0326b56c017e36e26d7e2d0e95a684eaf519a915

5 years agoARM: tegra: devices: add IORESOURCE_IRQs for tegra-aes
Varun Wadekar [Thu, 12 Apr 2012 12:23:24 +0000]
ARM: tegra: devices: add IORESOURCE_IRQs for tegra-aes

Change-Id: I03f1800fb6b249e3f85fcbccf1fc95b376c25e9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Re006f82e8ab2a230cc0edc965d6177d2860e9e2c

5 years agoARM: tegra2: dvfs: Update DVFS rails statistic for Tegra2
Joshua Cha [Mon, 23 Apr 2012 01:13:47 +0000]
ARM: tegra2: dvfs: Update DVFS rails statistic for Tegra2

LP2 state of Tegra2 is considered into rail statistic.

Change-Id: Iab2e0fe25ecb8feca1f4aa1040ce5020e6dcf584
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/98118
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R12360db9523d6070f88ef4e3839766a9972f26a5

5 years agoARM: tegra: power: Cancel hotplug work upon disable
Antti P Miettinen [Fri, 6 Apr 2012 11:21:26 +0000]
ARM: tegra: power: Cancel hotplug work upon disable

Cancel hotplug work when auto hotplug gets disabled to prevent
e.g. cpu_up() getting called in LP cluster.

Bug 965777

Change-Id: I058fe6a5e0c2fd3203ce9bc951d0973b60e033e0
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/95076
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R1231b26dc3e75cb093969d16fed8f93bc9ddcd99

5 years agoARM: tegra: add several other sysfs/debugfs params
Liang Cheng [Thu, 12 Apr 2012 18:56:05 +0000]
ARM: tegra: add several other sysfs/debugfs params

Bug 939292

Change-Id: Ib0c849418c6c426518948785082fcceb180f3d64
Reviewed-on: http://git-master/r/96250
Tested-by: Liang Cheng (SW) <licheng@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Mark Peters <mpeters@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R9df8e6a2268408f425e235031f76e4528a12e5e1

5 years agoARM: tegra20: pm: flush L1 data before exit coherency
Prashant Gaikwad [Tue, 27 Mar 2012 12:10:35 +0000]
ARM: tegra20: pm: flush L1 data before exit coherency

Bug 934368

Change-Id: I960d8ae5c6390e719b8ee6c9cbc067cf8d28122d
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: R427f723d0d107291c15c4f2e371ff7a06af82643

5 years agoARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU
Varun Wadekar [Tue, 27 Mar 2012 10:47:20 +0000]
ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU

Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92542
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rc6500c96b497bc20caa75dd5cae36afed165973f

5 years agoARM: tegra: rethink the cpu suspend-resume code path
Varun Wadekar [Fri, 30 Mar 2012 04:13:40 +0000]
ARM: tegra: rethink the cpu suspend-resume code path

The current kernel methodology expects that tegra_cpu_suspend
is actually the last function in the entire suspend sequence.

In order to achieve this, the code needs to be remodelled a
bit so that we actually execute native cpu_suspend at the end
of the suspend sequence. This allows us to leverage all the
cpu_suspend code developed by ARM in the upstream kernels.

Bug 934368

Change-Id: I94172d7adaa54c10043c479a57b270925d85a16b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/84481
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R15682d1d82f341338a2dd20c3083b66b9325bf7d

5 years agoARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND
Varun Wadekar [Tue, 27 Mar 2012 11:58:00 +0000]
ARM: tegra: remove usage of USE_TEGRA_CPU_SUSPEND

Bug 934368

Change-Id: Ic9d75cbb0c324b1858b2e476e33dd4f96349bce3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/86351
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb4fb04a26bc05a9649d17a3be8956d18998acc25

5 years agoarm: tegra: turn off pll-a/p in LP1
Mayuresh Kulkarni [Fri, 24 Feb 2012 14:05:36 +0000]
arm: tegra: turn off pll-a/p in LP1

- current code does not turn off pll-a/p in LP1
irrespective of voice call status
- add a new flag to indicate voice call on-going
- use PMC_SCRATCH37 to hold this flag
- if it is set, do not turn-off pll-a/p during LP1
- save-restore PMC_SCRATCH37 if it was used to hold the
voice call on-going flag
- fix few misc formatting issues in tegra3_cpu_clk32k

Bug 924817

Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/85768
(cherry picked from commit 7853981c987ae329620bb54d869016cb74a6c054)

Change-Id: Id5348d2eb44a4bacaf00f6d17edceedaef819e29
Reviewed-on: http://git-master/r/94395
Tested-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R08711befca33c0506083c3991fe2d88373a5a99e

5 years agoARM: tegra: clock: Set EMC and SCLK rates suspend floors
Alex Frid [Fri, 9 Mar 2012 23:07:00 +0000]
ARM: tegra: clock: Set EMC and SCLK rates suspend floors

- On suspend entry set EMC rate floor high enough to select PLLM as
  EMC clock source, since PLLM is always turned off in suspend.
- On suspend entry set SCLK (AVP) rate floor to speed-up system bus
  during save/restore procedures.

Bug 939942
Bug 938649

Reviewed-on: http://git-master/r/89234
(cherry picked from commit ccfdaef143f9017d682af017e11a25c3e5bcf3a7)

Change-Id: I4e1d66521f1f3453502c471999a52637c3d489aa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/94124
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Re3a8f00277608599ea41fbf101d6d2578b3af199

5 years agoarm: tegra: pm: Update CPU complex resume
Prashant Gaikwad [Tue, 27 Mar 2012 10:42:57 +0000]
arm: tegra: pm: Update CPU complex resume

Completely removed PLLP restoration from CPU complex resume on
Tegra2 platforms (too late: PLLP is restored from AVP warm boot
code)

Bug 952200
Bug 931285

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/92523
(cherry picked from commit 066dc172010f1a5ea5a375e1cbdcf162ab206d63)

Change-Id: I1a31793db8ee1fda5a947d69890e3118f0d3cdab
Reviewed-on: http://git-master/r/93562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R64f35a7cd9baf5d73ab2e5a4e80274aed2529912

5 years agopower: bpcm: Re-try setting BPC limit
Alex Frid [Sun, 11 Mar 2012 08:02:33 +0000]
power: bpcm: Re-try setting BPC limit

Check returned value from BPC set limit api, and re-try again
on error. Keep CPU throttled while re-trying.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 8d5e5a36a03587e3e9374ad8cec6958bd3617f0c)

Change-Id: I29b24a92b87cbd41d68473d0c9ef4c8d6add992f
Reviewed-on: http://git-master/r/93732
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1a1d8e5221407e7d85e2b222472fd27bf33335c5

5 years agoARM: tegra3: Make MC early ack feature configurable.
Manoj Chourasia [Wed, 21 Mar 2012 08:58:58 +0000]
ARM: tegra3: Make MC early ack feature configurable.

Add a config option to configure early acknowlegement
from memory controller.

Early acknowledgement is feature of memory controller
where MC acknowledged immediately to any write requests
from CPU. To maintain mermory coherency all the read
requests are blocked till all the early-acked writes
have reached to a point of coherency.

bug 943638

Change-Id: I97f30261c4711fc338b007502b6eef7217ddb6cb
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/91477
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R30f90744622a4bf6624d1e64143ca0be5653efaf

5 years agoARM:tegra:pcie:Avoid commenting PM noirq calls
Jay Agarwal [Mon, 26 Mar 2012 14:23:23 +0000]
ARM:tegra:pcie:Avoid commenting PM noirq calls

1. disable read write operation while suspend/resume
   noirq operation is performed to avoid hang
2. implement dev pm_ops for pcie tegra driver
3. use a backup buffer to save config space of
   all pcie devices to avoid legacy PM calls.

Change-Id: I2d39f69a865b48e1e51ce2cd466e24007718a8b6
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/90617
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Penny Chiu <pchiu@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Emily Jiang <ejiang@nvidia.com>

Rebase-Id: Re9b6cd5c88ddc8464239b4a04c3b09980b9d40e5

5 years agoARM:tegra:pcie: fix pcie power management
Jay Agarwal [Fri, 2 Mar 2012 18:38:07 +0000]
ARM:tegra:pcie: fix pcie power management

1. disable pci devices asynchronous suspend/resume.
2. correct resume function of tegra pcie driver.
3. enable clock clamping
4. require noirq suspend/resume calls to be commented

Bug 790141
Bug 947673

Change-Id: I49ebba43f296c3c38bc960d7db5fe847232e29a8
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/87316
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Penny Chiu <pchiu@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>

Rebase-Id: Re6718ef71103b0e12071f9e438df08e5405f8fe1

5 years agoarm: tegra: Enable speculative line fill in SCU.
Krishna Reddy [Thu, 22 Mar 2012 17:31:35 +0000]
arm: tegra: Enable speculative line fill in SCU.

Enable speculative line fill in SCU.
Bug 947861

Change-Id: I2db7515c47715160a4e559931e178b41c01a1744
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/91834
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra417206fd2895f95226617212dc7dfb088af8c88

5 years agoARM: tegra3: ARM_SAVE_DEBUG_CONTEXT should be selected based on PM_SLEEP
Manoj Chourasia [Wed, 21 Mar 2012 09:14:14 +0000]
ARM: tegra3: ARM_SAVE_DEBUG_CONTEXT should be selected based on PM_SLEEP

ARM_SAVE_DEBUG_CONTEXT was getting selected by tegra3 independent
of PM_SLEEP config. ARM_SAVE_DEBUG_CONTEXT itself is dependent on
PM_SLEEP. That was generating following warning while doing
savedefconfig with PM_SLEEP disabled.

scripts/kconfig/conf --savedefconfig=defconfig Kconfig
warning: (ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects \
ARM_SAVE_DEBUG_CONTEXT which has unmet direct dependencies\
(PM_SLEEP && CPU_V7)

This patch fixes the issue.

bug 931053

Change-Id: I57016476b7ca39f9ac36a9c59d0102c89c85c6c9
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/91461
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rd4e8f7c16261aff4fd848bd6b255c5b681a9e1e6

5 years agoARM: tegra: Fix PPCS IO address for Tegra 2x
Krishna Yarlagadda [Thu, 22 Mar 2012 10:52:16 +0000]
ARM: tegra: Fix PPCS IO address for Tegra 2x

PPCS physical address is different for Tegra 3x and 2x

Change-Id: If26f08f6f234786194f6642523b644e8bf4be770
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/91768
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: R1ba4eb9a41cc90532ff1e960a726054c41f1051e

5 years agoARM: tegra: dvfs: Add chip sku override
Ray Poudrier [Fri, 9 Dec 2011 01:38:25 +0000]
ARM: tegra: dvfs: Add chip sku override

Based on command line parameter, override the sku

Bug 925878

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/83241
(cherry picked from commit 24df2878418fc0c5f2b2dd20130df91a23dd042e)

Change-Id: Ic8d2408c6e408fcf28f9b64f12866971b753b41e
Reviewed-on: http://git-master/r/88864
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R429a8f39d29ee14b3f422f7fd38057ea25b30983

5 years agoARM: tegra: timer: add /dev/timerinfo
Jon Mayo [Wed, 29 Feb 2012 04:55:19 +0000]
ARM: tegra: timer: add /dev/timerinfo

Add a device that allows read-only mmap() of timer registers.

Reviewed-on: http://git-master/r/87511
(cherry picked from commit 95a6a6dafd97cbc72ea305f17b600be67a03093b)

Change-Id: I8782107dc3a32ff1c5a3a3c68d2ff0e8fb123dc3
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/91984
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb52591deea1abd67f12030137797f5f73bfd75a5

5 years agotegra:pcie: Correct pcie check link sequence
Jay Agarwal [Fri, 9 Mar 2012 12:21:02 +0000]
tegra:pcie: Correct pcie check link sequence

1. Removed mdelay in reset code since pci devices
   are not detected with this.
2. Moved the reset logic down in retry label.

Bug 637871

Change-Id: Idd6344860e513407d5f8c8ba05e1beef0f39bf57
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/89128
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

Rebase-Id: R2348e87464846782dc2c386d41a764acbca271d3

5 years agoARM: tegra: Add AHB EMEM to MC Flush Register IO
Rakesh Bodla [Mon, 6 Feb 2012 10:51:03 +0000]
ARM: tegra: Add AHB EMEM to MC Flush Register IO

Add the AHB EMEM to MC Flush Register
area to the statically mapped io regions

Bug 729267

Change-Id: I86542cd3ffec587e7213cbc34129e8b5124aab9c
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/88283
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

Rebase-Id: Rc06feec527b077aad17930e9d68f18c065317705

5 years agoARM: tegra: clock: Fix activity monitor resume
Alex Frid [Mon, 12 Mar 2012 19:01:17 +0000]
ARM: tegra: clock: Fix activity monitor resume

Properly restore Tegra3 actmon sampling period after suspend.

Bug 952739

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eb6e96a39dbc5d310e8e59046d6e1b787b780e60)

Change-Id: I6a61c2aa1d384a8d17d7ef579000cf59ac218435
Reviewed-on: http://git-master/r/90804
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R81027c97fbdaaeb18f3e8bd8e9fa327db6c09895

5 years agoarm: tegra: fuse: let ODM production mode be world readable
Chris Johnson [Sat, 10 Mar 2012 01:52:50 +0000]
arm: tegra: fuse: let ODM production mode be world readable

Also, fixup some of the bit offsets that were leading to incorrect
values being returned from get_fuse() on T20/T30.

Bug 912862

Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/89283
(cherry picked from commit f6323c7f32017b51202d478671cbf366beb0b0f5)

Change-Id: Ieb9f92e36760cbc470d63257d26c09388cec7e1e
Reviewed-on: http://git-master/r/90762
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Johnson <cwj@nvidia.com>
Tested-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rb601b07c80b00030a1fbd05f1edd6ad68a0911a7

5 years agoARM: tegra: tegra20_mc_init: fix warning
Dan Willemsen [Fri, 23 Mar 2012 07:40:09 +0000]
ARM: tegra: tegra20_mc_init: fix warning

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R91c84edeb7d48aa408e1d52e933b054ac98000a9

5 years agoshare irqs
Dan Willemsen [Fri, 23 Mar 2012 06:59:26 +0000]
share irqs

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rc9ec3044c122673073343c53a052f995d35eacf3

5 years agoarm: tegra: p1852: Add proc interface for board specific info
Bob Johnston [Thu, 15 Mar 2012 17:45:52 +0000]
arm: tegra: p1852: Add proc interface for board specific info

1) /proc/board_serial will have the board serial number.
2) /proc/skuinfo will have 18 character sku information.
3) /proc/skuver will have 2 character sku version number.
4) /proc/prodinfo will have product information
5) /proc/prodver will have product version number.

bug 931053

Change-Id: I7daccf932d3ee55b13c89eb4aaa519f51d8dba3e
Signed-off-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-on: http://git-master/r/90378
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R4b5d67c94f0180aa2b78fe6a71d50a8c9e2a838d

5 years agoARM: tegra: clock: Add tegra_cpu_user_cap_set function
Jinyoung Park [Fri, 2 Mar 2012 05:17:09 +0000]
ARM: tegra: clock: Add tegra_cpu_user_cap_set function

To set cpu_user_cap in tegra drivers, added tegra_cpu_user_cap_set
function.

Bug 945552

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/87109
(cherry picked from commit db954aafdfdbe1fa122466b8e8ec4ea4273efb90)

Change-Id: I765c44de4ed4ae908ef56914db53533605bd6d88
Reviewed-on: http://git-master/r/89740
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Re6ba9de6aada4d3c389ee61177e7e0fdcb19b064

5 years agoarm: tegra: ventana: use fixed regulator instead of direct gpio
Pritesh Raithatha [Tue, 13 Mar 2012 11:47:46 +0000]
arm: tegra: ventana: use fixed regulator instead of direct gpio

Bug 925547

Change-Id: I81f87cef3a9767d9bd60b72e33a23620392ab5fc
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/89736
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc862b26aef9167e3c5a0f9f673495491e4a0ca0c

5 years agoARM: tegra: power: Boost CPU rate before device resume
Alex Frid [Tue, 28 Feb 2012 21:52:58 +0000]
ARM: tegra: power: Boost CPU rate before device resume

Boost CPU frequency in tegra platform resume finish phase, just
before driver resume. Boost level is specified by platform suspend
data (ignored if 0).

Bug 946301

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59)

Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e
Reviewed-on: http://git-master/r/89353
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6fb2c94bac7079a35224ed5b2d81b98babb60dca

5 years agoARM: tegra: power: Use CPU G mode in suspend prepare
Alex Frid [Tue, 28 Feb 2012 19:33:07 +0000]
ARM: tegra: power: Use CPU G mode in suspend prepare

Switch to CPU G mode in Tegra3 suspend prepare if CPU suspend
rate is high enough. By symmetry, it guarantees that device
resume will be happening in G mode as well.

Bug 946301

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 082be3604056c39442e1b42f5cfceeb089ffdaae)

Change-Id: I42e37ce8847e4916dd0fca9e4bd44096b65f7032
Reviewed-on: http://git-master/r/89352
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R927e8f6c3ea5394b94533dbafc6a4e4d63399671

5 years agoARM: tegra: pm: only identity map lowmem area
Ray Poudrier [Fri, 2 Mar 2012 03:56:35 +0000]
ARM: tegra: pm: only identity map lowmem area

Bug 941380
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>

Reviewed-on: http://git-master/r/87095
(cherry picked from commit 72b72afb18f852ee0b352b0644bf30b4afeaa055)

Change-Id: I7e10b6180044a6fb58b2fee835991812c193d9b1
Reviewed-on: http://git-master/r/89564
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R07c5deb21033d418283e41e278bc4f99a0b71a1d

5 years agoARM: tegra: clock: Add SoC-to-DDR bit swap support
Alex Frid [Sat, 18 Feb 2012 07:25:06 +0000]
ARM: tegra: clock: Add SoC-to-DDR bit swap support

Since Tegra3 allows bit swapping when routing SoC-to-DDR data bus,
added the respective decoding mechanism for reading LPDDR2 mode
registers. Populated mapping table for PM269 board.

Bug 939626

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5f5329596167681b528c87fd088d60030eee6fdc)

Change-Id: I6670110a828df4264b8f7a8c8e6e67611a830033
Reviewed-on: http://git-master/r/89350
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Ra7f7bcb762eb542812e42a2b7d748a78429bf4b5

5 years agoARM: tegra: clock: Add LPDDR2 temperature controls
Alex Frid [Wed, 15 Feb 2012 07:00:41 +0000]
ARM: tegra: clock: Add LPDDR2 temperature controls

Added interfaces for
- reading scaled  LPDDR2 temperature from MR4 register
- controlling refresh rate according LPDDR2 specification

For now, these interfaces are only used by debufs nodes:

/sys/kernel/debug/tegra_emc/dram_temperature (read only)

/sys/kernel/debug/tegra_emc/over_temp_state (read/write,
0 - set regular low temperature refresh rate,
1 - speed up refresh for high temperature)

Bug 939626

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 373ff7e49235f6e222b42e324b6a2dc9eac633e6)

Change-Id: I9cfaaeeab16d5b49acb91824fecc6b0ee8f3cdbb
Reviewed-on: http://git-master/r/89349
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rf59ca31cf6bf91172c3f536273ded55bac28db31

5 years agoARM: tegra: clock: Update Tegra3 EMC timing tracking
Alex Frid [Wed, 15 Feb 2012 06:44:58 +0000]
ARM: tegra: clock: Update Tegra3 EMC timing tracking

Separated tracking of Tegra3 EMC timing settings from EMC rate
statistic, as the same rate may be configured with different
timing (e.g., BCT timing and DVFS timing are not the same even
for the same rate).

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit cbf5634f67d3fb53ad01bb632905cf311052e2f1)

Change-Id: I4015d31297e9be29ec2d3f298ad33bc59bf45836
Reviewed-on: http://git-master/r/89348
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R7712857be859f327ceda4abaf6b8dcf5613da576

5 years agoARM: tegra: clock: Disable early-ack during EMC clock change
Alex Frid [Wed, 15 Feb 2012 03:14:36 +0000]
ARM: tegra: clock: Disable early-ack during EMC clock change

Bug 935079

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit edf6b3ed22c4f803bf13d1bf6316ffb01c8946dc)

Change-Id: Ifd155a66469e9463da89639b6577c1f90972f4ac
Reviewed-on: http://git-master/r/89347
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rcf99ed43cf52be47c64648f1b94358572e5243d7

5 years agoARM: tegra: Put all Tegra Kconfig entries under if ARCH_TEGRA
Scott Williams [Fri, 9 Mar 2012 01:01:00 +0000]
ARM: tegra: Put all Tegra Kconfig entries under if ARCH_TEGRA

Change-Id: I49041ada720045908a433b44f301036fc4913462
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/88955
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: R24ea158659ec0502a9a13afcddaec1184189f0ad

5 years agoARM: tegra: Enable CPA.
Krishna Reddy [Wed, 7 Mar 2012 03:12:45 +0000]
ARM: tegra: Enable CPA.

Change-Id: I24725e7d98226e56af7ca06c91c05277a7eb1fdd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/88443
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Red219d6c9c584c50afb000b12b36b08090009015

5 years agoARM: tegra: power: Trim Tegra3 hotplug timings
Diwakar Tundlam [Thu, 1 Mar 2012 00:18:11 +0000]
ARM: tegra: power: Trim Tegra3 hotplug timings

Bug 945921
Reduce delays in going LP->G and G->Gn

(cherry picked from commit 51b7022f328d955cc4dbbf47b35403ea9c5e3a7b)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: I10f68196cb64ea20461000e9b0d64999fd714395
Reviewed-on: http://git-master/r/88169
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R034700ebd8691349c87b442a1ab721c1a941c1ac

5 years agoARM: tegra: Fix warnings for missing type forward reference
Scott Williams [Tue, 6 Mar 2012 22:17:42 +0000]
ARM: tegra: Fix warnings for missing type forward reference

Change-Id: Ic327c7323f1d98639b20a44527d9e4a0c01d11d2
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/88113
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R15131723cb0bab9954ccd3c4d4a705e7491fc7e5

5 years agoARM: tegra: power: Fix build error on non-SMP systems
Scott Williams [Fri, 26 Aug 2011 01:39:56 +0000]
ARM: tegra: power: Fix build error on non-SMP systems

Can't use NR_CPUS on non-SMP systems. Just use the maximum.

Change-Id: I00b455adf950869146dfcd176efe4abdbe7aa24e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/87416
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rd38f56587bd586144b67680d3e6c595d5f6b3def

5 years agoARM: tegra: Clean kernel and I/O mappings upon LP2
Antti P Miettinen [Thu, 23 Feb 2012 11:18:31 +0000]
ARM: tegra: Clean kernel and I/O mappings upon LP2

There is no need to flush the complete L2 upon LP2
entry but it is necessary to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.

Bug 931316

Change-Id: Ice353f16d35ee24d4387e7b9b135f205c4d0ba32
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/86293
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R21a9d573a7e4550da6d7b6a6947a66a50b7b956b

5 years agotegra: pcie: Fix individual port detection on T20
Jay Agarwal [Mon, 27 Feb 2012 14:49:20 +0000]
tegra: pcie: Fix individual port detection on T20

This commit fix two issues.
1. MMIO space should be reserved for T30 as well
2. There is a bug in link reset sequence causing
   problem in detecting the other slot as well
   on T20

bug 826956
bug 637871

Reviewed-on: http://git-master/r/66814
(cherry picked from commit 11ce98902d0687646eb30a4bd1f9a1d5e8da34ce)

Change-Id: I1843e3a1d897a36768b05b33ab7624889191d011
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/86134
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Re83bb96eb57b75a959bc2338f37de79cc10c52d3

5 years agoARM: tegra: power: Don't enter LP2 if not in NOHZ mode
Alex Frid [Sat, 3 Mar 2012 01:49:18 +0000]
ARM: tegra: power: Don't enter LP2 if not in NOHZ mode

Prevent Tegra3 secondary CPU entry to LP2 state when scheduler tick
is not switched to NOHZ mode, yet.

Bug 945658

Change-Id: I654f7aac0e545ecb557005cc4efad4317689e091
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/87937
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R399de42b81f5ccb63f99801fdfc14bcf1e359f59

5 years agovideo: tegra: host: register nvhost master device in board-xxx-panel.c
Mayuresh Kulkarni [Mon, 5 Mar 2012 13:06:47 +0000]
video: tegra: host: register nvhost master device in board-xxx-panel.c

- the suspend order of devices is governed by the order
in which devices are registered
- this commit ensures that nvhost master is registered before
any of the graphics devices
- previously this was done in rootfs_init call which is
later than arch_init calls of board-xxx-panel.c
- this caused tegra-dc device to be registered *before* nvhost
master device. as a result it was suspended *later* than nvhost
master device. this is a clear violation of dependency rule
for nvhost. this caused suspend-resume to fail for L4T
- this worked on android as it has CONFIG early suspend enabled
while it failed for L4T which doesn't have CONFIG early suspend
enabled

Bug 947617

Change-Id: I6cd405f3ba23d004e7659140019f5130e6c25159
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/87756
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

Rebase-Id: Rc1bd18592bac4e07563394250a550862dd2ffd46

5 years agoARM: tegra: Add forced-recovery support for bootloader.
Gaurav Sarode [Fri, 2 Mar 2012 13:00:19 +0000]
ARM: tegra: Add forced-recovery support for bootloader.

Set SCRATCH0 bit 1 when forced-recovery is set.
Bootrom will check this and put device into nvflash mode.

Bug 948326

Signed-off-by: Gaurav Sarode <gsarode@nvidia.com>
Change-Id: I78108021dffda681d63ddc6760e07cb563ba2eac
Reviewed-on: http://git-master/r/87238
Reviewed-by: Vivek Kumar <vivekk@nvidia.com>
Reviewed-by: Hon Fei Chong <hchong@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: Rd2ffc27d7496c6ffdf75dc0c33fe1b79239b6e43

5 years agotegra: pcie: Remove unnecessary clock operations
Manoj Chourasia [Tue, 22 Nov 2011 18:11:37 +0000]
tegra: pcie: Remove unnecessary clock operations

All these clock operations should be handled by
powergate operations.

bug 840051

Reviewed-on: http://git-master/r/66177
(cherry picked from commit 1ad8fe3e184db04063275c837e240827bda009e9)

Change-Id: I0159c6c1f64932b22b25d31d4bb1ff9d41385879
Reviewed-on: http://git-master/r/86126
Tested-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R51086a12e0d30b6aa707d18072676762fa6fd127

5 years agoarm: tegra: update thermal sensor configurations
Hao Tang [Thu, 16 Feb 2012 19:45:03 +0000]
arm: tegra: update thermal sensor configurations

Bug 941960

Removed CONFIG_TEGRA_INTERNAL_TSENSOR_EDP_SUPPORT.
Add internal tsensor on kai.

Change-Id: Iaefa43112fbbaa42d43a428ecb86ad821e683f85
Signed-off-by: Hao Tang <htang@nvidia.com>
Reviewed-on: http://git-master/r/84350
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: Rd7d08385b89ea4b19aef5b0b8b9d9283db01adc1

5 years agoARM: tegra: power: Fix LP2 timers suspend/resume
Alex Frid [Thu, 23 Feb 2012 04:40:58 +0000]
ARM: tegra: power: Fix LP2 timers suspend/resume

On entry/exit to suspend state remove/restore Tegra3 LP2 wake timers
interrupts affinity to the respective secondary CPUs.

Change-Id: I9b46c5fa446a8c6e813343f4564abda5313853da
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/87541
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rbe5a012771239ff09ea256b4b78f8bd63ee5d61f

5 years agoARM: tegra: clock: Increase Tegra3 EACK countdown
Alex Frid [Sun, 26 Feb 2012 23:19:37 +0000]
ARM: tegra: clock: Increase Tegra3 EACK countdown

Bug 935079

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5e70d23ef33dbdf0ce628fd2f287eec1b145dd8e)

Change-Id: Ib8bd72b2cac82b50789f86d034d6ad03b76a657f
Reviewed-on: http://git-master/r/87539
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rfd04345b3e0e65e695de0606c3892a7ac0e071a5

5 years agoarm: tegra: Enable gizmo settings after system resume
Seshendra Gadagottu [Fri, 10 Feb 2012 06:23:22 +0000]
arm: tegra: Enable gizmo settings after system resume

Enable save/restore gizmo settings for all tegra chip sets.

Bug 935834

Change-Id: I0400d555c05c5558aca2bf3d2cee707c7db77927
Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/83037
(cherry picked from commit 5a51bbfc4715dc50571ccfc44c31d8318ba306c1)
Reviewed-on: http://git-master/r/87507
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R341ab54b61b1e588a7a6e771f0bca0b7dd6a3cac

5 years agoarm: tegra: power: disable SUSPEND_LP2 mode selection
Ashwini Ghuge [Wed, 29 Feb 2012 11:25:01 +0000]
arm: tegra: power: disable SUSPEND_LP2 mode selection

Disable selection of LP2 suspend mode from sysfs and
if LP2 mode set from board file change mode to LP0

Bug 928456

Change-Id: I1603153e23688ff1048289c4e04f7c7337f480af
Reviewed-on: http://git-master/r/86580
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R6a918cb4e79ea6b4768ea76e21d7812a79b7bc20

5 years agoARM: tegra: Add support for passing arguments to bootloader.
Gaurav Sarode [Mon, 27 Feb 2012 16:24:30 +0000]
ARM: tegra: Add support for passing arguments to bootloader.

PMC SCRATCH register 0 holds value across warmboot.
Storing values in bit31:30 for recovery and fastboot.
This requires change in bootloader as well to parse these arguments.

Bug 863014

Change-Id: I1d4b752dbc6dd7b065e9d0cc87df189e7caeb201
Signed-off-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-on: http://git-master/r/86140
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R55bb6af9c4fa0970320f4397bbe3aca4678e8c7d

5 years agoarm: tegra: io: Increase host1x io size
Animesh Kishore [Tue, 14 Feb 2012 09:49:50 +0000]
arm: tegra: io: Increase host1x io size

This accomodates dsi second instance address space.

Bug 928423

Change-Id: I4aa3314b3227f49b3fe49552503fbdb2fd1c9ddb
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/83773
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R551bd8cc20006b37e35361bc3360efe90f3dd764

5 years agoARM: tegra: power: Fix Tegra2 power timer rate
Alex Frid [Sun, 19 Feb 2012 08:24:18 +0000]
ARM: tegra: power: Fix Tegra2 power timer rate

Commit cb0428145196ed7a75861c78d28f46b6bc8d2320 implemented LP0
state entry with fast CPU and system bus clocks only for Tegra3,
but changed power timers rate calculation in the common Tegra2
and Tegra3 path. Fixing it now.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 9e66d6adf6ab1fe06eee63baf0f1f684715d1ae2)

Change-Id: Iac276f048fed4edbee318cadddb862e45ba851c6
Reviewed-on: http://git-master/r/86550
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R58e05290ae8c359a5be22271961bae2152ab3966

5 years agoARM: tegra: dvfs: Relax Tegra3 lower speedo limits
Alex Frid [Sun, 19 Feb 2012 01:02:03 +0000]
ARM: tegra: dvfs: Relax Tegra3 lower speedo limits

Bug 817679
Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 44e7c117b3188bdd45a6e7dae31e8d3ea78c5d98)

Change-Id: I3d6d43a9a6690a8df51b0c84f4e4b6ad244c4fea
Reviewed-on: http://git-master/r/86549
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Re765273646c35342a748d31da842a3660a67c20d

5 years agoARM: tegra: dvfs: Update Tegra3 speedo thresholds
Diwakar Tundlam [Thu, 2 Feb 2012 02:02:23 +0000]
ARM: tegra: dvfs: Update Tegra3 speedo thresholds

Bug 817679
Bug 841336

Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit a4f6d43aa692586654ebb441246f0509fce7fa58)

Change-Id: Ie649f71177ed71b8e8c4062a8966f2478bfef7aa
Reviewed-on: http://git-master/r/86548
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R68e51503350d377b4775b8772386ca723188f216

5 years agoARM: tegra: Enable ARM_SAVE_DEBUG_CONTEXT
Scott Williams [Mon, 27 Feb 2012 18:54:56 +0000]
ARM: tegra: Enable ARM_SAVE_DEBUG_CONTEXT

Change-Id: Icbeed86d3fdc04d4ae7e3c129a707ceba6f61fba
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/86159
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R8c6d2e71a86dcbf9159156cd8ab9e0f858687d2c

5 years agoARM: tegra: invalidate volatile CPU state after resume from suspend or hotplug
Haley Teng [Fri, 24 Feb 2012 05:19:25 +0000]
ARM: tegra: invalidate volatile CPU state after resume from suspend or hotplug

In the CPU hotplug startup routine, besides invalidate d-cache, we also
need,

- invalidate BTAC, i-cache, branch predict array, TLB
- invalidate SCU tags
- enable i-cache, branch prediction

Bug 926063
Bug 925488

Change-Id: I3751192f6aee65d93f6654e768d93ef7a5092023
Signed-off-by: Haley Teng <hteng@nvidia.com>
Change-Id: I35af9d4bbe5d60df2d648d9e7dcc18762194fb11
Reviewed-on: http://git-master/r/84759
Reviewed-by: Foster Cho <ycho@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R602268297bd2926fae8d5b0006c3fc1f1b931560

5 years agoARM: tegra: power: Support minimum on-line cpus limit
Alex Frid [Sun, 19 Feb 2012 04:46:15 +0000]
ARM: tegra: power: Support minimum on-line cpus limit

Updated Tegra3 auto-hotplug mechanism to keep minimum number of
on-line cpus above the limit specified by the PM QoS parameter
PM_QOS_MIN_ONLINE_CPUS.

Added respective debugfs node /kernel/debug/tegra_hotplug/min_cpus.

Bug 940061

Change-Id: Ic7d2e0fdb334661d46c9cd3ce0c73ae662ca3722
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/84707
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R8791a0f1bd598c9919af1f80ae2ec5c8d82465c9

5 years agovideo: tegra: host: Merge tegra_grhost and host1x devices
Mayuresh Kulkarni [Fri, 24 Feb 2012 10:16:51 +0000]
video: tegra: host: Merge tegra_grhost and host1x devices

- tegra_grhost is a platform device that represents host1x
- nvhost has device host1x which represents the same hardware
- merge these two device structs
- as the new struct is a nvhost_device, platform_driver
is also converted into a nvhost_driver
- register nvhost device before other graphics devices.
this ensures that nvhost_probe() is called as soon as
nvhost_driver is registered with the core.
- this also ensures that nvmap is probed first, followed
by nvhost, followed by tegra-dc and nvavp (if they
are enabled).

Change-Id: Ic420a6516a9cb20d6f481692a4db10fa6053dd90
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/82631
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R065d81b1662002350c233fa2167e05db6033aa15

5 years agoARM: tegra: power: Don't lower clocks on LP0 entry
Alex Frid [Sun, 12 Feb 2012 04:19:42 +0000]
ARM: tegra: power: Don't lower clocks on LP0 entry

Do not change (lower) CPU and system clocks, and do not disable PLLs
on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1)

Change-Id: I2f175882d4d3dcfe5aee9c460f873a5e907e4ece
Reviewed-on: http://git-master/r/84714
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R5213db4e83e16fe448a0a494af25ab9f340cce0b

5 years agoARM: tegra: clock: Update secondary pll dividers resume
Alex Frid [Sun, 5 Feb 2012 08:12:59 +0000]
ARM: tegra: clock: Update secondary pll dividers resume

During resume from LP0 on Tegra3 always enable pll secondary dividers
before clocks restoration (to make sure clock sources are enabled).
Restore actual secondary dividers settings after clocks are restored.

Remove pllp secondary dividers restoration from cpu complex restore,
and add them to common clock restoration procedure. These dividers
are not affected by CPU complex suspend, only by LP0 core suspend.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 1f631436717c0602ef30770f7976615150114afe)

Change-Id: I45777ca0535f51a39c35e9d360ac6e97a13ea92c
Reviewed-on: http://git-master/r/84712
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rfa8bbf01564827e488c7ffc6153c0050c21b0a8d

5 years agoarm: tegra: pci: fix lost interrupts condition
Rakesh Iyer [Thu, 16 Feb 2012 20:09:48 +0000]
arm: tegra: pci: fix lost interrupts condition

Clear the interrupt status before posting events to driver code, to avoid
losing interrupts for devices with high interrupt rate.

Change-Id: I776dff33e273b7d1c0dd10615ce4405acdc867e8
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/84356
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1f86ae2432bbe29ba6dfc594ab16eb3e5325ae53

5 years agoARM: tegra: power: Notify clock event in CPU mode switch
Alex Frid [Sun, 5 Feb 2012 06:32:44 +0000]
ARM: tegra: power: Notify clock event in CPU mode switch

Add clock event notification to switch timekeeping to broadcast
timer during Tegra3 CPU mode switch. Skip notifications if mode
switch happens on entry/exit to/from suspend state when timekeeping
is already suspended.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 236fd35c40a748d8373d7f34b53c320045fa4d3a)

Change-Id: I38386dfe3d4ffb89f35828cd911d254b976f0063
Reviewed-on: http://git-master/r/84713
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Raabcec0c9dddd3a2f3d80ed61de3acb9c2ce2e5f

5 years agoARM: tegra: clock src initialisation for debug port in common place
Laxman Dewangan [Wed, 22 Feb 2012 12:05:38 +0000]
ARM: tegra: clock src initialisation for debug port in common place

Moving clock source rate initialisation of  debug ports in
common place from board files.
In this way, it does not need to call the same function from
all board files and so avoid duplicating.

Change-Id: I4e0292c7760488125c0dd8ee5fa23f50faca3436
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/85174
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R39246b3dd3462f37f94b21110686ec16ebd1a2b9

5 years agoarm: tegra: power: Add AP33 Battery EDP table
Peter Boonstoppel [Fri, 20 Jan 2012 18:33:32 +0000]
arm: tegra: power: Add AP33 Battery EDP table

Exact copy of AP30 table

Bug 926056

Change-Id: I48730c41605b177d267a569804bbc75a6b94cfba
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/85233
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rf882b5566c8619ddbbe4c98ca6b7ef9717807639

5 years agoARM: tegra: Do not unlock CoreSight register access
Scott Williams [Wed, 22 Feb 2012 01:20:10 +0000]
ARM: tegra: Do not unlock CoreSight register access

There is no reason to unlock APB CoreSight register access in the
kernel. The debugger can perform it's own unlock operation as
needed. Keep the registers write-protected to prevent inadvertent
access.

Change-Id: I22f28f76b5dd498b3782ab3380a04f865b59d6fd
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/85039
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

Rebase-Id: Rb7544ceebc5b79fbe8abe9909e4b5019584ba484

5 years agoARM: tegra: cardhu: set dap1 drive strength
Nikesh Oswal [Fri, 17 Feb 2012 10:11:36 +0000]
ARM: tegra: cardhu: set dap1 drive strength

Change-Id: I1b3797b021adadd1ad944ede45b5916500a881e6
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/84542
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R20d1982a1f84f0c61d978cacbbce4a8ca1a8f1dd

5 years agoARM: tegra: power: Power off multiple CPUs on-line
Alex Frid [Fri, 3 Feb 2012 00:21:02 +0000]
ARM: tegra: power: Power off multiple CPUs on-line

Currently on Tegra3 cpu complex is powered off in idle (enters CPU0
LP2 state) only if all secondary CPUs are off-line. This commit adds
an option for CPU0 to enter LP2 while secondary CPUs are still on-line
but have been power gated and entered LP2 state by themselves.

The critical race: secondary CPU is waking up from LP2, while CPU0 is
turning common CPU rail off, is addressed as follows.

1. When entering LP2 state on CPU0:
a) disable GIC distributor
b) check that CPU1-3 are all power-gated (i.e., either off-lined or
have entered LP2)
c) if (b) passes - set all interrupts affinity to CPU0, then
re-enable distributor and continue with CPU complex powering off
d) if (b) fails - re-enable distributor and enter clock-gated (LP3)
state on CPU0
This procedure prevents waking secondary CPUs by GIC SPIs.

2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ
or private timers would happen. This is achieved by disabling timers
and legacy interrupts if CPU1-3 enters LP2 state with external timers
selected as wake sources. Respectively, establish dependency between
turning rail off and LP2 wake timers configuration options.

3. Finally, no IPIs is sent by CPU0 entering LP2.

There are no special changes in wake up procedures - whenever CPU0
is awaken by external interrupt or wake timer, cpu complex is powered
on by h/w, and secondary CPUs that were in LP2 state are ungated by
the same interrupt (off-line CPUs are kept power gated). Hence, there
is no need for CPU1-3 external wake timers to run while the rail is
off, and these timers are stopped. To make sure that none of secondary
CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep
interval of all CPUs.

By default configuration option for powering off multiple on-line CPUs
is disabled on Tegra3.

Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83547
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rc518e98ddce9152f0eeb086a49c31e1c252fe9eb

5 years agoTegra: Pinmux: Fixed up errors about DTV interface
Adam Jiang [Thu, 17 Nov 2011 04:09:04 +0000]
Tegra: Pinmux: Fixed up errors about DTV interface

Pin configuration on DTV interface could be enabled by this patch.

Fixed Bug 904626
Fixed Bug 881303

Change-Id: I6b5dc12629740bb8275156df9d9a5b4ca9dae352
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/66626
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
(cherry picked from commit c34733e5ea933b322cd5edbceb93f921ffe413de)
Reviewed-on: http://git-master/r/73955
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rc5ff48d2d28c657fb12fa22280f74139766ab532

5 years agoarm: tegra: pinmux: correct pinmux setting for DDC and PTA group
Sanjay Singh Rawat [Tue, 15 Nov 2011 06:22:47 +0000]
arm: tegra: pinmux: correct pinmux setting for DDC and PTA group

The safe function setting is not correct for the pingroup

Bug 901383

Change-Id: I5a7340b0d4951d844e3b1824edbfc6de4fec0006
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/64371
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb9e9261e3725f21bcb97edaf71d16f7c0aed2eaa