4 years agomisc: mods: update reference to emc clock
Chris Dragan [Wed, 25 Mar 2015 09:41:55 +0000]
misc: mods: update reference to emc clock

Use tegra_emc clock domain when referencing the emc clock.

Bug 200083696

Change-Id: Ice4cc91d6fc3d5a4f1dc979f06d34815dae3b194
Signed-off-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-on: http://git-master/r/722574
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rohan Sreeram <rsreeram@nvidia.com>
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agomisc: tegra-cec: Short-circuit init on suspend
Xia Yang [Fri, 20 Feb 2015 23:45:52 +0000]
misc: tegra-cec: Short-circuit init on suspend

Bug 1591149

Initialization of cec engine is slow.
Short-circuit the init in event of suspend.

Change-Id: Ibfbd6f36883a7bf45fdb5137120b041a52f42086
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-on: http://git-master/r/714423
(cherry picked from commit d5f4a6602678c87e8caa5032e43f2415c314d800)
Reviewed-on: http://git-master/r/716496
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agoarm64: add MIDR_EL1 field accessors
Mark Rutland [Wed, 16 Jul 2014 15:32:43 +0000]
arm64: add MIDR_EL1 field accessors

The MIDR_EL1 register is composed of a number of bitfields, and uses of
the fields has so far involved open-coding of the shifts and masks
required.

This patch adds shifts and masks for each of the MIDR_EL1 subfields, and
also provides accessors built atop of these. Existing uses within
cputype.h are updated to use these accessors.

The read_cpuid_part_number macro is modified to return the extracted
bitfield rather than returning the value in-place with all other fields
(including revision) masked out, to better match the other accessors.
As the value is only used in comparison with the *_CPU_PART_* macros
which are similarly updated, and these values are never exposed to
userspace, this change should not affect any functionality.

Change-Id: I9b287b3bd1621f8ca7ffaee4c235f2c2cd98c2c8
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-on: http://git-master/r/721974
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

4 years agofirmware: tegra: export tegra_bpmp_send
Antti P Miettinen [Wed, 25 Mar 2015 07:25:05 +0000]
firmware: tegra: export tegra_bpmp_send

Bug 200084664

Change-Id: I5d4a64b34ebcb0736a37c367cc7830d09bbe9bce
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/722435
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>

4 years agoadd generic fixmap.h
Mark Salter [Thu, 23 Jan 2014 23:53:48 +0000]
add generic fixmap.h

Many architectures provide an asm/fixmap.h which defines support for
compile-time 'special' virtual mappings which need to be made before
paging_init() has run.  This support is also used for early ioremap on
x86.  Much of this support is identical across the architectures.  This
patch consolidates all of the common bits into asm-generic/fixmap.h
which is intended to be included from arch/*/include/asm/fixmap.h.

Change-Id: Ie893201a7edc1651b28f780f4c9ae401aa749b71
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jonas Bonn <jonas.bonn@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Reviewed-on: http://git-master/r/722005
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

4 years agovideo: tegra: hdmi: consolidate dbgfs nodes
Sam Payne [Thu, 19 Mar 2015 18:28:56 +0000]
video: tegra: hdmi: consolidate dbgfs nodes

moves ability to read edid from /d/edidx to
read/write node /d/tegradc.x/edid

bug 1625630

Change-Id: Ibe138676c1756ee006202a473f6334853117d6eb
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/719676
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

4 years agoarm: dts: add wifi/bt regulator node
Ian Chang [Fri, 20 Mar 2015 11:12:05 +0000]
arm: dts: add wifi/bt regulator node

Change-Id: I3874d622009b032c85d84e86c97d3ddf923212fd
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/720309
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agoarm: dts: add regulator node of Green Arrow
Ian Chang [Fri, 20 Mar 2015 09:27:01 +0000]
arm: dts: add regulator node of Green Arrow

Add regulator nodes of sensors and audio

Change-Id: I5578bfb148af1748cdbfc59d3b115b938c0e9b0a
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/720266
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Shih <rshih@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agoarm: dts: backlight: set boost freq to 1MHZ
Ian Chang [Wed, 18 Mar 2015 04:50:20 +0000]
arm: dts: backlight: set boost freq to 1MHZ

Set boost frequency to  1MHZ for ripple issue.

bug 1622290

Change-Id: Ia9f43dce978bb237c2c3a5f22bcbd6495b4ab7d1
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/718760
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

4 years agoarm: dts: Add thermal/ldo3 node.
Ian Chang [Thu, 19 Mar 2015 06:54:43 +0000]
arm: dts: Add thermal/ldo3 node.

Add thermal/ldo3 node for Green arrow

Change-Id: Ic1fc21b4053098b009ce3c9a51e35c6be9711f93
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/719363
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agoarm: mach-tegra: add compatible of green-arrow
Ian Chang [Thu, 19 Mar 2015 07:09:10 +0000]
arm: mach-tegra: add compatible of green-arrow

Change-Id: I5c354432c004afae9f35d328579e8fc7805c3620
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/719367
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agousb: gadget: xudc: fix zlp issue for ctrl ep
Henry Lin [Thu, 12 Mar 2015 10:51:18 +0000]
usb: gadget: xudc: fix zlp issue for ctrl ep

In control endpoint's zlp handling, a racing between SW ring doorbell
and HW process data stage TD will cause zlp's TD will not be scheduled.

Solution is: set data stage TD's IOC, wait data stage TD's completion
event, and then schedule zlp TD.

Bug 200078991

Change-Id: I9d996fdae71a41c3b3b05c0fdbebfeb064222578
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/717800
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>

4 years agospi: tegra: Set dma burst size
Krishna Yarlagadda [Tue, 24 Mar 2015 15:36:54 +0000]
spi: tegra: Set dma burst size

Set dma burst size same as spi trigger size calculated
from length of transfer

Bug 200089395

Change-Id: Ia1f30276699ffe03b8447faa92b727bbd11447b9
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/721867
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agospi: tegra: add T186 to compatible list
Krishna Yarlagadda [Fri, 6 Mar 2015 07:37:38 +0000]
spi: tegra: add T186 to compatible list

Add T186 chip to compatible devices list

Change-Id: Id4770e114b50989854b6c54a6716cd2a1c899c3f
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/714705
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM64: dts: Hawkeye: set dcp charger current limit
Venkat Reddy Talla [Tue, 24 Mar 2015 10:44:14 +0000]
ARM64: dts: Hawkeye: set dcp charger current limit

set input current limit for DCP charger cable as 3A,
the charger's input current is limited to 2.0A in hardware.

Change-Id: Ib790b761e73eadfb87adac3a7b7d2731545a632c
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/721589
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM: tegra: hawkeye-ffpb: correct dts file name match with board name
Laxman Dewangan [Wed, 25 Mar 2015 15:40:06 +0000]
ARM: tegra: hawkeye-ffpb: correct dts file name match with board name

Hawkey-ffpb board name is e2295 and so changing the dts file for
this board to match with the board name.

Change-Id: I5493e4d1f10ce63d0a8cec1e4df25d650372d94e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/722813
Reviewed-by: Q-Ha Park <qpark@nvidia.com>

4 years agoarm: dts: vcm30t124: HDMI: Golder register update
Varun TV [Mon, 9 Mar 2015 07:13:43 +0000]
arm: dts: vcm30t124: HDMI: Golder register update

Update golden register fields as per latest QUAL for HDMI on vcm30t124.

bug 1592120

Change-Id: I758140655fc5c577f90bca5a362c186b4b168377
Signed-off-by: Varun TV <vtv@nvidia.com>
Reviewed-on: http://git-master/r/715130
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agodvfs: tegra21: Increase CPU max rate to 2.014 GHz
Alex Frid [Fri, 6 Mar 2015 20:54:41 +0000]
dvfs: tegra21: Increase CPU max rate to 2.014 GHz

Increased CPU max rate to 2.014 GHz for shield sku.

Bug 1558421

Change-Id: Ic803f91d109a7c4be6476a5417f24719361c3ed0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/714879
Reviewed-by: Bo Yan <byan@nvidia.com>

4 years agomisc: tegra-fuse: Simplify HW access for chip id
Bo Yan [Mon, 23 Mar 2015 23:50:21 +0000]
misc: tegra-fuse: Simplify HW access for chip id

ASIM address ranges now come from device tree, there is no need
to statically map resources in i/o table init. This also removes
the need to map APB misc. register address space in fuse driver
, because that address space is still mapped in i/o table init,
so the simple macro IO_ADDRESS can be used instead.

The obsolete t18x specific chip id access code is removed.

Change-Id: I538e80a85b03c562d6a5d930918e4ac45d001d03
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/721969
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>

4 years agoiommu/arm-smmu: override bool option
Hiroshi Doyu [Wed, 25 Mar 2015 15:36:30 +0000]
iommu/arm-smmu: override bool option

Allow to override bool option if the same bool starts with '-'.

Bug 1610014
Bug 1610542
Bug 1618080

Change-Id: Ibc496f9d204edf6528a3f23f41890e0a73e11b97
Tested-by: Antti P Miettinen <amiettinen@nvidia.com>
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/722818
Reviewed-by: Vandana Salve <vsalve@nvidia.com>

4 years agoRevert "misc: bluedroid_pm: Add uevent for resume"
Terje Bergstrom [Wed, 25 Mar 2015 21:16:15 +0000]
Revert "misc: bluedroid_pm: Add uevent for resume"

This reverts commit e539832ca181ed3f2e8ae3b6cb0bc4972b0cd461. It
causes panic when suspending.

Bug 1628120

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I5404de5f2b2866807e726edf534e078aca520b7a
Reviewed-on: http://git-master/r/722911
Reviewed-by: Automatic_Commit_Validation_User

4 years agoplatform: tegra: emc: allow table modification
Alex Waterman [Tue, 6 Jan 2015 23:54:36 +0000]
platform: tegra: emc: allow table modification

Provide a debugfs mechanism to modify EMC tables post boot. This allows
some trimmers, configuration parameters, etc, to be modified. It is
dangerous and should only be used if you *really* know what you are
doing.

Bug 1583167
Bug 1625892

Change-Id: I1967797be161bc7b18eb0fd8d7052884e7885de5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/714833
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

4 years agousb: gadget: xudc: power up pad in system resume
Henry Lin [Mon, 23 Mar 2015 07:27:19 +0000]
usb: gadget: xudc: power up pad in system resume

Xudc driver always initializes utmi pad during system resume. Because
initializing utmi pad will power down utmi pad by default, xudc driver
should power up utmi pad again if vbus is detected in system resume.

Bug 200086605

Change-Id: I0522378e078663fcba1472a67fdf85ecff6e3399
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/720822
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>

4 years agousb: gadget: xudc: apply sw war per chip
Henry Lin [Mon, 29 Dec 2014 04:49:42 +0000]
usb: gadget: xudc: apply sw war per chip

Using fpci device id to identify chip version. Below t210 specific
wars are changed to be only applied to t210:
- usb: gadget: xudc: war for ctrl request
- usb: gadget: xudc: war for disconnect in U2/U3

Bug 200058268

Change-Id: Ic347591ba615ebbcdd11fa91bdd6bbba3ff686ca
Signed-off-by: Henry Lin <henryl@nvidia.com>
Reviewed-on: http://git-master/r/718737
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ray Sung <rsung@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hui Fu <hfu@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

4 years agoconfigs: tegra: unset CONFIG_LOCALVERSION_AUTO
Konsta Holtta [Tue, 3 Mar 2015 13:33:49 +0000]
configs: tegra: unset CONFIG_LOCALVERSION_AUTO

Unset CONFIG_LOCALVERSION_AUTO in defconfigs, since it causes the build
to set the current git sha1 to the kernel version string. This appended
version confuses our magic scripts and affects build paths and kernel
module versions when the kernel is changed even slightly. The developer
usually knows which version he is using anyway, so the shortened sha1 is
unnecessary information.

Bug 200082598

Change-Id: I12cf67bc5042c848bdd295ade61ac960dfda3ead
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/713184
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 years agoptm: tegra210: adds reg contents to trace output
Sam Payne [Fri, 20 Feb 2015 23:30:55 +0000]
ptm: tegra210: adds reg contents to trace output

adds 16 4-byte cpu config values to the beginning
of trace data pulled from /dev/trc
this data is used by the trace parser to read
the configuration of each core.

Change-Id: Ic1b7706f86f2787e751e4000493490c8a870b903
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/710017
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

4 years agogpu: nvgpu: Fix comptag index in trace
Terje Bergstrom [Tue, 17 Mar 2015 19:39:42 +0000]
gpu: nvgpu: Fix comptag index in trace

Instead of comptag index we were dumping an offset in buffer.

Change-Id: Iaa07919c8d87009227556eacbcb6dcbd83954c7d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/718597
Reviewed-by: Automatic_Commit_Validation_User

4 years agotegra: gpu: disable touch boost for gpu
Seshendra Gadagottu [Tue, 24 Mar 2015 20:24:11 +0000]
tegra: gpu: disable touch boost for gpu

Gpu boosting with input events is causing more gpu power consumption
than required. To avoid this, touch boot for gpu is disabled by not
registering gpu device for cfboost frame work. Current rail gate
entry/exit latencies are fast enough to give smooth user experience.

Bug 200087243

Change-Id: I18673d9c95a44ce9bee87e860b4edb29212dc766
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/721989
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 years agodrivers: thermal: number modem thermal zones
Neil Patel [Tue, 24 Mar 2015 20:04:36 +0000]
drivers: thermal: number modem thermal zones

Add a suffix to the modem thermal zone name "modem" to allow easier
differentiation.

Bug 1619534

Change-Id: I1a6395b7cc93e2e8a278100b328fd8cf0700752a
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/721964
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rider Ni <rni@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

4 years agoarm64: configs: t210: Enable isc manager module
Anurag Dosapati [Tue, 17 Mar 2015 18:17:04 +0000]
arm64: configs: t210: Enable isc manager module

Enable to compile isc-mgr and isc-dev

Bug 1624846

Change-Id: Ib8afc3c08bf6457b3cd56b57cda7dd0614494486
Signed-off-by: Anurag Dosapati <adosapati@nvidia.com>
Reviewed-on: http://git-master/r/718575
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Reviewed-by: Songhee Baek <sbaek@nvidia.com>

4 years agotegra: hv_net: update driver for ivc reset
Dennis Kou [Tue, 17 Mar 2015 18:30:36 +0000]
tegra: hv_net: update driver for ivc reset

Update the virtual network driver to implement support for
ivc channel resets. Use of ivc under the previous (non-reset)
model has been deprecated.

Bug 1597820

Change-Id: I2049baabffec6bfe75a85ab3bc1de136ae1d7156
Signed-off-by: Dennis Kou <dkou@nvidia.com>
Reviewed-on: http://git-master/r/718578
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

4 years agodt-bindings: memory: t18x header
Hiroshi Doyu [Tue, 24 Mar 2015 07:39:16 +0000]
dt-bindings: memory: t18x header

Change-Id: I48871e95141bc8d97d16e6162320989433612375
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/721795
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

4 years agoRevert "dt-binding: memory: add TEGRA_SWGROUP_SCE"
Hiroshi Doyu [Tue, 24 Mar 2015 07:37:56 +0000]
Revert "dt-binding: memory: add TEGRA_SWGROUP_SCE"

This reverts commit 854e7ebd5cd12675904e34389b98956c1e9f336f.

Change-Id: I533390d9b3f83a7e987a670cea7d62521871d4b9
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/721794
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

4 years agoRevert "dt-binding: memory: add NVCSI"
Hiroshi Doyu [Tue, 24 Mar 2015 07:37:49 +0000]
Revert "dt-binding: memory: add NVCSI"

This reverts commit 5d16ef4b161bd8fa65d7961a4660df15f75beeb7.

Change-Id: I5445606fd0cee8302835fdfb0ac4067cb47a18ed
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/721793
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

4 years agogpu: nvgpu: Use common allocator for compbit store
Terje Bergstrom [Fri, 20 Mar 2015 16:43:26 +0000]
gpu: nvgpu: Use common allocator for compbit store

Reduce amount of duplicate code around memory allocation by using
common helpers, and common data structure for storing results of
allocations.

Bug 1605769

Change-Id: I7c1662b669ed8c86465254f6001e536141051ee5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/720435

4 years agoARM: tegra: hawkeye: Fix irq number
Hyungwoo Yang [Mon, 23 Mar 2015 22:36:42 +0000]
ARM: tegra: hawkeye: Fix irq number

Fix irq number for MAX77621 for GPU

bug 1626740
bug 1619534

Change-Id: I0ae592b47533b247996037b5920fd3e6912747f5
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/721141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM: tegra: set SMPS10 to 3.75V
Laxman Dewangan [Tue, 24 Mar 2015 12:53:32 +0000]
ARM: tegra: set SMPS10 to 3.75V

Set SMPS10 to 3.75V as per platform specific configuration.

bug 1626724

Change-Id: I15c3477e052256d73034c3e01165f798bd51d5f6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/721775

4 years agoarm64: configs: tegra21: enable tegra profiler
Igor Nabirushkin [Wed, 11 Mar 2015 08:59:13 +0000]
arm64: configs: tegra21: enable tegra profiler

Enable Tegra System Profiler for T210 L4T platforms.

Bug 1540280

Change-Id: I51ba1861a6b54ddc20c50e33ab30f72623245b9c
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/716234
(cherry picked from commit 67594ae40282ebd7219446bfaaa61ae1dc1a1dd0)
Reviewed-on: http://git-master/r/719383
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agoarm64: dts: vcm31: e2580: Update emc-table, sata, pcie and OC
Amlan Kundu [Thu, 12 Mar 2015 10:02:02 +0000]
arm64: dts: vcm31: e2580: Update emc-table, sata, pcie and OC

- Add emc table
- Enable SATA/Pcie
- Disable soctherm OC in e2580 as it
  dose not support external over-current detection chip

bug 200063105

Change-Id: I3346bc929400a95016c57f92ea96b472e97c2d3f
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/718167
(cherry picked from commit 739aff39692a22244579650d6ea435ccdb634265)
Reviewed-on: http://git-master/r/721609
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

4 years agoarm64: dts: t210: Dt file support for e2379
Amlan Kundu [Fri, 6 Mar 2015 08:54:26 +0000]
arm64: dts: t210: Dt file support for e2379

- Dt support for e2379
- Enable camera GPIO for E2379
- Add sound node for E2379
- Add vcm3.1 emc table
- Disable soctherm OC
- redefine changed LDOs, set LDO2 always on.
- disable sdmmc1, 2, 3.
- Enabled SATA/PCie

bug 200086460
bug 200086451
Bug 200085452
Bug 1587869
bug 200085472
bug 200086257

Change-Id: I649a1ef191b19c39adb47464ba7638b6c059563e
Signed-off-by: Amlan Kundu <akundu@nvidia.com>
Reviewed-on: http://git-master/r/718157
(cherry picked from commit aae512d29f2c7776016acf6f62ee91f82fc9c206)
Reviewed-on: http://git-master/r/721601
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ambika Prasad <ambikap@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

4 years agoRevert "video: tegra: host: Add VI/ISP clock ctrl ioctl"
Arto Merilainen [Wed, 25 Mar 2015 08:36:42 +0000]
Revert "video: tegra: host: Add VI/ISP clock ctrl ioctl"

This reverts commit a0fd071b3f0cd72ed9e551123705a876ca7c5369 as
it causes build failure

Bug 1628484

Change-Id: Idfa5275292a5e20620d96837a17b605d2e5b016b
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/722531

4 years agovideo: tegra: host: Add VI/ISP clock ctrl ioctl
Sudhir Vyas [Thu, 12 Mar 2015 13:07:22 +0000]
video: tegra: host: Add VI/ISP clock ctrl ioctl

Add ctrl-node ioctl support for VI and ISP clocks.

Bug 1610946

Change-Id: Icbd7d00d26912a1b0ffd0611c5c5644a86681d4d
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/716814
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

4 years agoarm: configs: p1889: disable SMSC95XX
Shawn Joo [Tue, 3 Mar 2015 05:26:39 +0000]
arm: configs: p1889: disable SMSC95XX

P1889 does not have SMSC95XX.
Disable it.

Change-Id: I47fc96564563b8cf01da066704998e6ef0b4e736
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/712989
GVS: Gerrit_Virtual_Submit
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agoarm: dts: set HDMI power rail
Ian Chang [Mon, 23 Mar 2015 05:44:32 +0000]
arm: dts: set HDMI power rail

a. set VDD_SYS_BOOST as VDD_HDMI supply
b. set GPIO3_PN5 to push-pull mode

Change-Id: If5e9273f27ef57632b13bbe5fed490404c9a25f4
Signed-off-by: Ian Chang <ianc@nvidia.com>
Reviewed-on: http://git-master/r/720754
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agoarm: dts: green arrow: add rollback-protection node
Mahesh Lagadapati [Thu, 12 Mar 2015 19:19:52 +0000]
arm: dts: green arrow: add rollback-protection node

Add rollback-protection node to enable RPMB for Green Arrow devices.

Bug 1608437

Change-Id: I242706dff276f6677fc62a5697e3004ff1e30424
Signed-off-by: Mahesh Lagadapati <mlagadapati@nvidia.com>
Reviewed-on: http://git-master/r/717027
Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM: tegra: set sensor rail (smps9) to 2.8V
Laxman Dewangan [Tue, 24 Mar 2015 12:45:56 +0000]
ARM: tegra: set sensor rail (smps9) to 2.8V

Set sensor rail (SMPS9 from PMIC) to 2.8V during regulator init.

bug 1626717

Change-Id: Ib867bb14320b17db222003ff020e8ad748466f57
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/721767
Reviewed-by: Automatic_Commit_Validation_User

4 years agodrivers: media: platform: tegra: isc driver update
Charlie Huang [Fri, 20 Mar 2015 01:14:18 +0000]
drivers: media: platform: tegra: isc driver update

support of isc-dev driver pre-install.
support of debug fs of isc-mgr.
update dev_pm_ops to remove warning message due to legacy pm support.

bug 200086212
bug 1604566

Change-Id: Ic1b3a4ffa658a17e6972f6198030d2ae2f4320f5
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/719963
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

4 years agot124: dts: update isc-mgr entry
Songhee Baek [Tue, 10 Mar 2015 16:29:53 +0000]
t124: dts: update isc-mgr entry

+ enable isc-mgr entry in p1889.
+ add aggregator/serializer/sensor entries in each mgr entry in p1889
  for kernel driver early installation.
+ update csi port number in isc-mgr entry in p2360.
+ update pwdn-gpios order to be GMSL power first and
  then TV power because TV power can be various number.

Bug 1601092
Bug 200086212

Change-Id: I165fa59f8ffe3adaca8bb1545fa35a43a75774c1
Signed-off-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-on: http://git-master/r/715841
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Tested-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

4 years agoalarmtimer: add support to set the maximum alarm interval time
Laxman Dewangan [Mon, 23 Mar 2015 12:01:56 +0000]
alarmtimer: add support to set the maximum alarm interval time

When system enters into suspend, alarmtimer set the RTC HW for alarm.
Add API to set the maximum time for alarm such that if any client/user
space has set the wakeup for more than this time then alarmtimer will
set the alarm to this time.

This help to ensure that system will wakeup once on this time.

bug 200082198

Change-Id: Ib22ad0a01782e946750a6641579bcad9f119fd70
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/720942

4 years agoinclude: ktime.h: add API to get seconds from ktime
Laxman Dewangan [Tue, 24 Mar 2015 10:06:50 +0000]
include: ktime.h: add API to get seconds from ktime

Add API to get second from ktime. This will be applicable for
all type of architecture.

Change-Id: I6aca51b933766443d705284c3ba4569c9c2c997c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/721563

4 years agoarch: tegra: enable full regulator constraint for green arrow
Laxman Dewangan [Mon, 23 Mar 2015 09:57:08 +0000]
arch: tegra: enable full regulator constraint for green arrow

Enable full regulator constraints for green arrow. This will allow
to turn off the rails which are not used.

Change-Id: I2996d406e54ebd4ed1b22ec62cedcfc05c5fe958
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/720877

4 years agoclock: tegra21: Assign clock IDs for CEC, DISP1
Hoang Pham [Fri, 20 Mar 2015 01:03:36 +0000]
clock: tegra21: Assign clock IDs for CEC, DISP1

Assign Tegra21 clock IDs for CEC, DISP1, DISP2,
DSIA, DSIB, HOST1X

Bug 1608456

Change-Id: I6b7d4b4dadadbd611a82701ca05f49644e577036
Signed-off-by: Hoang Pham <hopham@nvidia.com>
Reviewed-on: http://git-master/r/719954
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

4 years agoclock: tegra21: Add VI/ISP emc clocks
Wenjia Zhou [Fri, 20 Mar 2015 22:10:54 +0000]
clock: tegra21: Add VI/ISP emc clocks

Based on http://git-master/r/299389, added VI/ISP clock for T210 platform

Bug 1624387

Change-Id: I8a6f620c646b6e62c428748f72dc11738b4ad3a3
Signed-off-by: Wenjia Zhou <wenjiaz@nvidia.com>
Reviewed-on: http://git-master/r/720495
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

4 years agotegra: hv_net: fix transmit on unresponsive peer
Dennis Kou [Mon, 16 Mar 2015 22:59:17 +0000]
tegra: hv_net: fix transmit on unresponsive peer

Make transmit operations timed such that an unresponsive peer will
not cause a soft kernel crash as reported by the netdev watchdog.
The default timeout value is 10 ms, but this value is configurable
via a new device tree binding (max-tx-delay-msecs).

Bug 200079332

Change-Id: I534680d7e588e62988f27b7ef42a70269528edb8
Signed-off-by: Dennis Kou <dkou@nvidia.com>
Reviewed-on: http://git-master/r/717953
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Tested-by: Vladislav Buzov <vbuzov@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

4 years agovideo: tegra: dp: enable fake dp by default
Sam Payne [Thu, 19 Mar 2015 01:21:37 +0000]
video: tegra: dp: enable fake dp by default

enable fake dp in Kconfig be default in
preparation for testing dp in kernel_submit
as part of sanity

Change-Id: Ia3576e3bb555ffa5d4063b9170e0d7009245cc12
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/719225
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

4 years agoarm64: dts: Enable capture for e2580 platform
Anurag Dosapati [Tue, 17 Mar 2015 17:51:58 +0000]
arm64: dts: Enable capture for e2580 platform

Bug 1625859

Change-Id: If69f8750e7f5e69bcd1e1655fb7af2174923a1f2
Signed-off-by: Anurag Dosapati <adosapati@nvidia.com>
Reviewed-on: http://git-master/r/718580
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Songhee Baek <sbaek@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

4 years agotegra: mc: Fix kernel hang caused by clk_get
Wenjia Zhou [Sat, 21 Mar 2015 02:41:55 +0000]
tegra: mc: Fix kernel hang caused by clk_get

clk_get return NULL, and t21x_set_la caused segfault

Bug 1624387

Change-Id: I97f79ac6e3c16432b2acf9fbe2e0925e76401540
Signed-off-by: Wenjia Zhou <wenjiaz@nvidia.com>
Reviewed-on: http://git-master/r/720571
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

4 years agotegra:host:t210: Add emc clock in isp device
Wenjia Zhou [Sat, 21 Mar 2015 01:24:08 +0000]
tegra:host:t210: Add emc clock in isp device

Bug 1624387

Change-Id: I1251bae5d77d2bc280e3321373c2c37fc8a397ad
Signed-off-by: Wenjia Zhou <wenjiaz@nvidia.com>
Reviewed-on: http://git-master/r/720570
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Jihoon Bang <jbang@nvidia.com>

4 years agovideo: tegra: dc: set up secure vrr call.
Marvin Zhang [Wed, 11 Mar 2015 17:26:46 +0000]
video: tegra: dc: set up secure vrr call.

Bug 1576607

Change-Id: Ic415a4d39a84d663254d360fa08838411b5209b0
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/716435
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

4 years agosecurity: tlk_driver: export te_vrr_sec fastcall
Chris Johnson [Thu, 19 Feb 2015 03:01:24 +0000]
security: tlk_driver: export te_vrr_sec fastcall

Add support for a callable interface to issue a monitor fastcall
to do VRR (currently only supported for ARMv8 archs).

Bug 200081504

Change-Id: I2a29cd6d1c627ab80d9b504ec8bdf978125d43ec
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/714943
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

4 years agodrivers: net: usb: Update to r8152.53-2.03.3
Aly Hirani [Sat, 27 Dec 2014 07:03:15 +0000]
drivers: net: usb: Update to r8152.53-2.03.3

This commit adds the latest Realtek's recommended RTL8153
vendor driver. This fixes the packet loss issue on top of the v2.03.0
(which was breaking GameStream).

Bug 1604791

Change-Id: I46926b984a6252a27492f824200b7f3b5e9acb58
Signed-off-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-on: http://git-master/r/681275
(cherry picked from commit 904cb4c43d17bf4a6fd94c800e814194c661f138)
Reviewed-on: http://git-master/r/716075
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agovideo: tegra: nvmap: protect handle's VMAs with mutex in missing path
Maneet Singh [Fri, 13 Mar 2015 21:36:40 +0000]
video: tegra: nvmap: protect handle's VMAs with mutex in missing path

Fix race conditions while displaying NvMap procrank data where
handle's VMAs were accessed without holding handle's mutex lock.

Bug 200087086

Change-Id: I37f507ad57da779811a6f9744e2c7874c16e08a1
Signed-off-by: Maneet Singh <mmaneetsingh@nvidia.com>
Reviewed-on: http://git-master/r/720179
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

4 years agovideo: tegra: Don't allocate double buffered fb
Peter Pipkorn [Thu, 12 Mar 2015 12:07:05 +0000]
video: tegra: Don't allocate double buffered fb

Don't support 2x virtual yres. This means
that double buffering is not supported.

Bug 1618575

Change-Id: I0f23cedd4a47082d13a43190fdab6c68bf018215
Signed-off-by: Peter Pipkorn <ppipkorn@nvidia.com>
Reviewed-on: http://git-master/r/716792
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Arun Shamanna Lakshmi <aruns@nvidia.com>

4 years agoarm: dts: add DT matrix labels
Erik Lilliebjerg [Tue, 24 Mar 2015 04:30:12 +0000]
arm: dts: add DT matrix labels

The NVS (NVidia Sensor) framework's device tree module uses Android
sensor names for device tree labels so the DT orientation matrix lables
needed to change.
Note the DT label "orientation" has been changed to "matrix" to avoid
confusion with the actual sensor named "orientation".

Bug 1625384

Change-Id: I5a46de60a6d895f68c44470342d2eb91d43472b6
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/721363
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Robert Collins <rcollins@nvidia.com>

4 years agogpu: nvgpu: Helper for no kernel mapping alloc
Terje Bergstrom [Sat, 21 Mar 2015 15:47:41 +0000]
gpu: nvgpu: Helper for no kernel mapping alloc

Reduce amount of duplicate code around memory allocation by
introducing a variant of allocation helper that does not map the
allocated buffer to kernel address space.

NO_KERNEL_MAPPING allocations return a struct page **, so store the
results of allocation in a new field of mem_desc.

Bug 1605769

Change-Id: Ib760b9e6d34b229b04d1fb4f3abf10648670fc69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/721029

4 years agogpu: nvgpu: Use common allocator for GPFIFO
Terje Bergstrom [Thu, 19 Mar 2015 21:17:08 +0000]
gpu: nvgpu: Use common allocator for GPFIFO

Reduce amount of duplicate code around memory allocation by using
common helpers, and common data structure for storing results of
allocations.

Bug 1605769

Change-Id: I81701427ae29b298039a77f1634af9c14237812e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719872

4 years agogpu: nvgpu: Use common allocator for cmd queue
Terje Bergstrom [Thu, 19 Mar 2015 21:17:15 +0000]
gpu: nvgpu: Use common allocator for cmd queue

Reduce amount of duplicate code around memory allocation by using
common helpers, and common data structure for storing results of
allocations.

Bug 1605769

Change-Id: If93063acbbfaa92aef530208241988427b5df8eb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719871

4 years agogpu: nvgpu: Skip debug dump on stuck syncpoint
Terje Bergstrom [Thu, 19 Mar 2015 21:56:31 +0000]
gpu: nvgpu: Skip debug dump on stuck syncpoint

Skip dumping full debug spew on stuck syncpoint.

Change-Id: I22c019bac23c4530229e20c0f8ce00806e23d9a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/719876

4 years agogpu: nvgpu: Catch DS exception
Terje Bergstrom [Thu, 29 Jan 2015 20:46:59 +0000]
gpu: nvgpu: Catch DS exception

Catch DS exception and write an error to UART.

Change-Id: Iaad9813c48191f0d3d734d4af264b976a3818672
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/679142

4 years agoarm64: dts: add DT matrix labels
Erik Lilliebjerg [Mon, 23 Mar 2015 23:29:10 +0000]
arm64: dts: add DT matrix labels

The NVS (NVidia Sensor) framework's device tree module uses Android
sensor names for device tree labels so the DT orientation matrix lables
needed to change.
Note the DT label "orientation" has been changed to "matrix" to avoid
confusion with the actual sensor named "orientation".

Bug 1625384

Change-Id: I8a665f3fba0b9c47d0619da5f53de61ba9554c91
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/721173
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

4 years agovideo: tegra: hdcp: disable hdcp when unsupported
Sam Payne [Wed, 18 Mar 2015 22:43:27 +0000]
video: tegra: hdcp: disable hdcp when unsupported

prevents hdcp from being enabled and attempting
to read over i2c when using a dvi monitor

bug 1622732

Change-Id: I7837fecf479090c1ebf090497a2c45a9acb16ee0
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/719152
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

4 years agoiio: imu: Fix register cache defaults
Erik Lilliebjerg [Mon, 23 Mar 2015 19:39:33 +0000]
iio: imu: Fix register cache defaults

- When ICM regulators are not defined when the auto-detection
  of the device is not used, the execution path missed the
  device's master reset causing the device's POR register
  state to not be loaded to the register cache.
  Fixed by testing the regulator status at a common execution
  path for initialization and asserting the master reset if
  needed.
- Fix orientation matrix for device tree.  Previously, the
  orientation matrix was only retrieved from the obsolete
  board file.  Now it's also retrieved from the device tree.

Bug 1618724

Change-Id: I35cdbb234d969cadecb88949d9d1893561446241
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/721095
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>

4 years agosensors: Add DT suport for dynamic light table
Robert Collins [Wed, 11 Mar 2015 18:16:44 +0000]
sensors: Add DT suport for dynamic light table

Add DT support instead of overriding light table

Bug 1617955

Change-Id: I5c7df1bc10e86ead6df054997f0551c09b1e54ec
Signed-off-by: Robert Collins <rcollins@nvidia.com>
Reviewed-on: http://git-master/r/716453
GVS: Gerrit_Virtual_Submit
Reviewed-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
(cherry picked from commit 2dde0b2d03eb318f643a92556e499b325e0f4499)
Reviewed-on: http://git-master/r/718601
Tested-by: Akhilesh Khumbum <akhumbum@nvidia.com>

4 years agosensors: Add hybrid HW/SW integration time.
Erik Lilliebjerg [Sun, 8 Mar 2015 14:34:56 +0000]
sensors: Add hybrid HW/SW integration time.

Fix ALS reporting wrong values. The new patch introduces hybrid mode capability and also applies a scaling factor.

Bug 1617955

Change-Id: I18f5bbe401d0b10463d578340354451e81544a7c
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/715454
GVS: Gerrit_Virtual_Submit
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Tested-by: Robert Collins <rcollins@nvidia.com>
(cherry picked from commit 441b9b2257396c8f32316ece4ddaa1a5dea7e671)
Reviewed-on: http://git-master/r/715028
Tested-by: Akhilesh Khumbum <akhumbum@nvidia.com>

4 years agostaging: ozwpan: check for empty list before deleting node
Pritesh Raithatha [Wed, 4 Feb 2015 05:05:50 +0000]
staging: ozwpan: check for empty list before deleting node

Bug 200046702

Change-Id: Ia55feb43d6864619d5c1b8f436941cbeb7868541
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/680980
(cherry picked from commit aa2375f94463c793051b758d32c2f06005e0aaa5)
Reviewed-on: http://git-master/r/718076
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agoASoC: Tegra: rt5639: Fix jack detection using DT
Sharad Gupta [Fri, 20 Mar 2015 13:30:08 +0000]
ASoC: Tegra: rt5639: Fix jack detection using DT

Added support for enabling jack detection logic using codec IRQ
for DT.

Change-Id: Ic3b24be6e9bdab5b405f9398124660541fbfeaef
Signed-off-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-on: http://git-master/r/720364
Reviewed-by: Ian Chang <ianc@nvidia.com>
Tested-by: Ian Chang <ianc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM: tegra: fix rt5639 entry
Sharad Gupta [Fri, 20 Mar 2015 13:28:50 +0000]
ARM: tegra: fix rt5639 entry

Fixing entry for RT5639 for GreenArrow.

Change-Id: I328e8b8596375c795a0490b16b48d88b6708f90e
Signed-off-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-on: http://git-master/r/720330
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ian Chang <ianc@nvidia.com>
Tested-by: Ian Chang <ianc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoarch: arm64: configs: Disable wifi Multi-channel concurrency
Srinivas Ramachandran [Tue, 25 Nov 2014 00:10:32 +0000]
arch: arm64: configs: Disable wifi Multi-channel concurrency

Multichannel concurrency adds channel switching latency
in the data path. To reduce end-to-end audio/HID input
latency constraints, it is desirable to disable MCC so
that STA and P2P connections are on the same channel.

Bug 200058606

Change-Id: I5f81e8109e23541c155703afcd8d6f10f2a92242
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
(cherry picked from commit e53fa1b1d5df44b3af0f26b33857bf20de327508)
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: http://git-master/r/659264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Tested-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoarm64: t210: serial: poll rx periodically
Shardar Shariff Md [Wed, 18 Mar 2015 12:05:45 +0000]
arm64: t210: serial: poll rx periodically

Enable the feature of polling RX periodically
to avoid missing any RX interrupt

Bug 200087049

Change-Id: Ib5fd75f7ee5349b0e0f845a46600b346f6279645
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/718994
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoscripts: suspend-resume: Write "all" complete cycle information.
Alankrita G [Tue, 17 Mar 2015 10:57:43 +0000]
scripts: suspend-resume: Write "all" complete cycle information.

- Also only integer part of result is stored

Change-Id: I84fd89b1426d17d4fee46fde94bce14fe792d789
Signed-off-by: Alankrita G <alankritag@nvidia.com>
Reviewed-on: http://git-master/r/718435
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 years agoplatform: tegra: mc: include proper header file
Amit Sharma (SW-TEGRA) [Mon, 23 Mar 2015 05:13:57 +0000]
platform: tegra: mc: include proper header file

Fixed the following sparse warnings by including the proper header file:
- tegra_emc_timers.c: warning: symbol 'tegra_emc_timer_mr4_start' was not
       declared. Should it be static?
- tegra_emc_timers.c: warning: symbol 'tegra_emc_timer_mr4_stop' was not
       declared. Should it be static?
- tegra_emc_timers.c: warning: symbol 'tegra_emc_timer_training_start' was
       not declared. Should it be static?
- tegra_emc_timers.c: warning: symbol 'tegra_emc_timer_training_stop' was
       not declared. Should it be static?

Bug 200067946

Change-Id: Iebf283ffb353c6d8647010f963b92b5dd5dfc216
Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/720728
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

4 years agotegra: hv_net: fix security hole in guest comm
Dennis Kou [Wed, 11 Mar 2015 23:02:46 +0000]
tegra: hv_net: fix security hole in guest comm

Fix a security vulnerability that allows the remote peer to crash
the kernel by exploiting its ability to make unfriendly changes to
shared IVC state.

Bug 1619182

Change-Id: I106dac547c4c098e912fa36fee0226cae9e361ff
Signed-off-by: Dennis Kou <dkou@nvidia.com>
Reviewed-on: http://git-master/r/716552
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pantelis Antoniou <pantoniou@nvidia.com>
Reviewed-by: Bahadir Balban <bbalban@nvidia.com>
Tested-by: Bahadir Balban <bbalban@nvidia.com>
Reviewed-by: Peter Newman <pnewman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

4 years agotegra: hv_net: fix potential crash on init
Dennis Kou [Mon, 5 Jan 2015 20:08:52 +0000]
tegra: hv_net: fix potential crash on init

Fix a potential null dereference when tegra_hv_ivc_reserve()
fails. The reserve attempt can fail for a variety of reasons.

Also, fix the read of the low watermark value to come from
"low-watermark-mult" instead of "high-watermark-mult".

Bug 1566154

Change-Id: I2ff4b76a66c258810eac59c5dbfe404f8016067a
Signed-off-by: Dennis Kou <dkou@nvidia.com>
Reviewed-on: http://git-master/r/669355
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

4 years agotegra: adsp: dfs: Fix DFS exit
Alex Frid [Thu, 19 Mar 2015 19:59:46 +0000]
tegra: adsp: dfs: Fix DFS exit

Unregistered DFS notifier with ADSP CPU parent clock. This is required
to balance registration target which was changed from ADSP CPU clock
to its parent by commit 7a4c3d644ff0b79a0483b5c552aeb729a77fe295.

Bug 1588362

Change-Id: I65409324bbbebab1ba5d7a83b1a29b11f2c67ae7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/719835
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Tested-by: Viraj Karandikar <vkarandikar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

4 years agovideo: tegra: nvsr: sparse mode changes
Daniel Solomon [Thu, 16 Oct 2014 22:41:47 +0000]
video: tegra: nvsr: sparse mode changes

A few changes relating to Sparse mode and
prep for future functionality:

- Track self-refresh mode with TEGRA_DC_OUT_NVSR_MODE
  instead of reusing ONE_SHOT_MODE
- Add ability to keep DP link on or disable it during
  sparse mode
- Add modeset notifier
- Refactor sparse enable/disable, SRC init, vendor
  id and device
- Fix resync_delay type and resync capability check

Bug 1315461

Change-Id: I74014f193e66a8dad5145a37985b54728348dfe5
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/497178
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

4 years agovideo: tegra: dc: expose _tegra_dc_set_mode
Daniel Solomon [Mon, 20 Jan 2014 22:58:01 +0000]
video: tegra: dc: expose _tegra_dc_set_mode

The NVSR driver needs to be able to change
pixel clock as part of toggling burst mode.
The NVSR driver takes care of DC mutex
locking when calling this function.

Bug 1315461

Change-Id: Ia7edabc21f17e85a325aaae621cbf94e2b243d8d
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/363524
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

4 years agoARM: tegra: add DTS file for hawkeye-ffpb p2295-a00
Laxman Dewangan [Mon, 23 Mar 2015 10:16:43 +0000]
ARM: tegra: add DTS file for hawkeye-ffpb p2295-a00

Add top level DTS file for the Hawkeye FFPB P2296-A00 platform.
This is hawkeye form factor- power break board for power
measurement.

The base design is same as the Hawkeye FFF.

bug 1625590

Change-Id: Ie83cc80e5190079550aa2f2e2745f42af598baee
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/720885
Reviewed-by: Steve Rogers <srogers@nvidia.com>

4 years agovideo: tegra: dc: bypass EDID checksum
Aly Hirani [Tue, 17 Mar 2015 02:38:27 +0000]
video: tegra: dc: bypass EDID checksum

We have seen some old TVs which actually have a bad checksum hardcoded
in their EDIDs. Given our current use of the checksum code, this causes
things to break. These bad TVs actually have the right modes listed in
their timing blocks. Just the checksum is bad.

The bootloader doesn't fully validate the EDID checksum. This means that
it is actually possible to boot with HDMI connected on these "bad" TVs
(since the kernel just copies over the mode set by BL). However, as soon
as we hot plug in the kernel, we break HDMI. This is because in the current
state of code, if the EDID checksum fails, we assume that to be an equal
to an i2c read failure.

Instead of assuming a failed checksum to be equal to a read failure,
this change adds a retry mechanism built into the EDID read.
Specifically, if we read the EDID multiple number of times and calculate
the checksum to be exactly the same, assume that the TV has a bad
checksum and just ignore it. This change also adds the checksum
calculated from the EDID block in a print since it really helps in
debugging.

This approach is also recommended in CEA-861-F Section F.3.5.

Bug 1608233

Change-Id: I0384c90345a599c328337f7d63362df900a4bf4b
Signed-off-by: Aly Hirani <ahirani@nvidia.com>
Reviewed-on: http://git-master/r/718345
(cherry picked from commit b1823f58e621c202f2414a0878858abe7e3f9f4e)
Reviewed-on: http://git-master/r/719282
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

4 years agogpu: nvgpu: GM20B extended buffer definition
Sandarbh Jain [Fri, 13 Mar 2015 19:41:51 +0000]
gpu: nvgpu: GM20B extended buffer definition

Update extended buffer definition for Maxwell. On GM20B only PERF_CONTROL0 and
PERF_CONTROL5 registers are restored in extended buffer. They are needed for
stopping the counters as late as possible during ctx save and start them as
early as possible during context restore. On Maxwell, these registers contain
the enable/disable bit.

Bug 200086767

Change-Id: I59125a2f04bd0975be8a1ccecf993c9370f20337
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: http://git-master/r/717421
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 years agoarm: tegra: p1859: Add PWR_INT_N wake config
Shawn Joo [Thu, 22 Jan 2015 08:33:57 +0000]
arm: tegra: p1859: Add PWR_INT_N wake config

Depends on HW design, PMC PWR_INT(wake18) is required.
e.g. wake key is not routed to GPIO and only to PWR_INT_N.
Add CONFIG_BOARD_HAS_PWR_INT_WAKE_SOURCE config and
disable it by default.

Bug 200070392

Change-Id: I40fcc5178712cc1e338697bb17787901a837294c
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/676446
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

4 years agodrivers: backlight: add notify callback to lp855x
Nitish [Thu, 19 Mar 2015 08:11:31 +0000]
drivers: backlight: add notify callback to lp855x

This also sets the stage for a generic tegra BL callback. Future
patch needs to remove the dependency on board-panel.h.

Bug 1612033

Change-Id: Id6c4f7c7ee9c13f67364e090f41fad7b0a7bd4cd
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Signed-off-by: Nitish <nrajguru@nvidia.com>
Reviewed-on: http://git-master/r/713450

4 years agomm: cma: remove the get_page to avoid blocked
Xianhui Wang [Mon, 16 Mar 2015 03:17:21 +0000]
mm: cma: remove the get_page to avoid blocked

In current process if it meet error in __unmap_and_move, no need to add page
count for below two part:
1. For the vma related page count which reduced by try_to_unmap, it will add
page count back by function remove_migration_ptes.
2. For the page count reduced by put_page above migrate_replace_cma_page in
function __get_user_pages, it is corresponding with the add process
get_page_foll inside function follow_page_mask.

Then when __unmap_and_move return failure we should do nothing for page count
or it will continuously repeat follow_page_mask -> migrate_replace_cma_page
and page count increase every iteration and process blocked.

Bug 200078152

Change-Id: Ia5a1c2eb5c7936a620fe54818d08a7be1b4e9b1d
Signed-off-by: Xianhui Wang <xianhuiw@nvidia.com>
Reviewed-on: http://git-master/r/717725
(cherry picked from commit 16cfd49cb1b3ec0e190b68fb26b6c3fa6df7b25e)
Reviewed-on: http://git-master/r/718854
Reviewed-by: Louis Li <louli@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

4 years agoconfig: l4t: disable CONFIG_ANDROID for l4t
Naveen Kumar S [Wed, 18 Mar 2015 04:48:50 +0000]
config: l4t: disable CONFIG_ANDROID for l4t

CONFIG_ANDROID was enabled to facilitate a new SYNC Framework
for Linux: http://git-master/r/#/c/714740/. Made the sync framework
independent of android with http://git-master/r/#/c/718757/. Now we
can safely disable android config on L4T.

bug 1601262

Change-Id: I3c9ee7f5d3ecc5ed5f2beb3c5d51c810b1215d12
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/718762
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

4 years agoARM: tgera: hawkeye: configure FPS and timing for different rail
Laxman Dewangan [Thu, 19 Mar 2015 12:57:56 +0000]
ARM: tgera: hawkeye: configure FPS and timing for different rail

Configure FPS setting of different rail as per platform specific
recommendation.

Also configure the enable/disable/ramp time and active discharge
for CPU/GPU rail.

bug 1624428

Change-Id: Ic4acfd864a07384cd635b3e9e5f2a0638876be2d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/719608

4 years agoregulator: max8973: add support for enable/disable active discharge
Laxman Dewangan [Thu, 19 Mar 2015 12:56:11 +0000]
regulator: max8973: add support for enable/disable active discharge

Add support to enable/disable active discharge from DT for this device.

bug 1624428

Change-Id: I04568737e9f1a4c9f8efbc754d5546650527cbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/719607

4 years agoregulator: max77620: add provision to disable rails on suspend
Laxman Dewangan [Tue, 17 Mar 2015 10:43:40 +0000]
regulator: max77620: add provision to disable rails on suspend

Add provision to disable rails on suspend. This property can be
selected from DT.

Change-Id: I3de09418153df5a9527693d0866d8399cda218ee
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/718429

4 years agoregmap: core: add support to init device register from DT node
Laxman Dewangan [Mon, 9 Mar 2015 14:16:59 +0000]
regmap: core: add support to init device register from DT node

Add support to initialise the device register based on system
requirements from register value provided from DT.

The DT node of device should have driver specific subnode node
on DT node of this device and this subnode have property "config"
which contains the register, mask and value.

dev_node {
system-config {
config = <index reg mask val
 index reg mask val>;
};
};

Here index is the regmap index, reg is register offset, mask is
register mask and val is value need to be updated.

Driver will call the API with specific node name to configure
during driver initialisation.

Change-Id: I031629b692640e7b0edf4c02c8949d87d3520b22
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/715262

4 years agonet: wireless: bcmdhd: handling rmmod of bcmdhd driver
Narayan Reddy [Tue, 17 Mar 2015 05:58:55 +0000]
net: wireless: bcmdhd: handling rmmod of bcmdhd driver

Before low level access ensure power is restored
if in power save mode and also reenable mmc powersave
as a last step incase of removing the bcmdhd module

Bug 1608740

Change-Id: I02e90cddff9af8d27bc3ec83e38ed77ac63982c4
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: http://git-master/r/718755
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

4 years agoARM64: DT: t210: sdhci: Enable periodic calibration
R Raj Kumar [Wed, 25 Feb 2015 05:13:32 +0000]
ARM64: DT: t210: sdhci: Enable periodic calibration

- Enabled periodic calibration for SDMMC1/SDMMC3
- Added en-periodic-calib dt node details in the sdhci tegra
  documentation.

Bug 1591658

Change-Id: I673859aba5078dd6bd08983d94001a8f95d71447
Reviewed-on: http://git-master/r/711021
(cherry picked from commit be9c50ed7469e8572899912f9473540bcbb93134)

Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Change-Id: I06eab249f436fd3a17954dff38fc720350bf624e
Reviewed-on: http://git-master/r/719423
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

4 years agommc: Run auto calibration for every 100ms
R Raj Kumar [Thu, 12 Feb 2015 10:26:03 +0000]
mmc: Run auto calibration for every 100ms

Added support to run auto calibration for
sdmmc for every 100ms time interval
when sdmmc1/sdmmc3 interface is active.

Bug 1591658

Change-Id: Iecb8e9d1ae9b9c8a64f0bd79d5df5ac9c211bc43
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/719314
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>