5 years agoARM: tegra: power: Flush cache just before cpu shutdown
Alex Frid [Wed, 21 Sep 2011 01:45:53 +0000]
ARM: tegra: power: Flush cache just before cpu shutdown

Re-arranged cpu die procedure to flush L1 cache just before shutdown.
This is necessary as code executed after L1 flush included spin-lock
protected sections, and the unlock operation was not properly detected
by SCU. As a result CPUs that stayed on-line hanged trying to acquire
the same spin-lock.

Bug 864256

Change-Id: I415160d60686094059e62d91cdcf4b264a4fb69f
Reviewed-on: http://git-master/r/53637
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0663eac9b5c3c84d8b7380873bde6af6b2a74a9f

5 years agoARM: tegra: timer: Fix mismatch in twd suspend/resume code
Alex Frid [Tue, 20 Sep 2011 02:27:19 +0000]
ARM: tegra: timer: Fix mismatch in twd suspend/resume code

Change-Id: Ied49d7517574b62ebc54ba8a5ef04d26408f0145
Reviewed-on: http://git-master/r/53347
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Rd540ebbeb48903eea556508be45580c5d260941e

5 years agoARM: tegra: reduce LP0 resume CPU power on time
Jin Qian [Wed, 14 Sep 2011 18:53:35 +0000]
ARM: tegra: reduce LP0 resume CPU power on time

cherry-picked from adf08ef4030598a6bf9036f45584be8acc008fea

Bug 862504

Change-Id: I79460aa4abdccc4f2ca17867197bb12668d59dea
Reviewed-on: http://git-master/r/52420
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rffc2d7314a61f04274e0db116c5a1cb7004dc77d

5 years agoarm:tegra: Add EXPORT_SYMBOL and ioctls for test framework
Rahul Mittal [Wed, 14 Sep 2011 09:34:32 +0000]
arm:tegra: Add EXPORT_SYMBOL and ioctls for test framework

Added EXPORT_SYMBOL to functions to be used by loadable kernel module
for audio test framework. Also added ioctl declarations for the same.

Change-Id: Id8a023c1d76fd031c042c7c663bb0e1df2d33b5c
Reviewed-on: http://git-master/r/52333
Tested-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R88ac0ceb719d9fae5d68d5f9a1894a3562e82b25

5 years agoARM: tegra: power: fix build error on tegra_pm_enter routines
Jin Qian [Mon, 12 Sep 2011 19:33:15 +0000]
ARM: tegra: power: fix build error on tegra_pm_enter routines

Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c
Reviewed-on: http://git-master/r/51852
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861

5 years agoARM: tegra: Add enterprise audio support
Sumit Bhattacharya [Wed, 7 Sep 2011 09:42:51 +0000]
ARM: tegra: Add enterprise audio support

Bug 862023

Change-Id: I0ba560f471088302d6197c564f02606a25f2a5db
Reviewed-on: http://git-master/r/51072
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Raafdfa1c8ada5731492222e59228da084c0905d9

5 years agoARM: tegra: power: do not check time after kernel time suspend
Jin Qian [Fri, 2 Sep 2011 23:24:01 +0000]
ARM: tegra: power: do not check time after kernel time suspend

cluster switch for LP0 is called after linux timekeeping suspend,
which turns off timer.

Bug 862504

Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe
Reviewed-on: http://git-master/r/50611
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a

5 years agoARM: tegra: power: save cluster switch status before entering LP0
Jin Qian [Fri, 2 Sep 2011 23:22:18 +0000]
ARM: tegra: power: save cluster switch status before entering LP0

warm boot reads SCRATCH4 to choose wake-up from LP or G

Bug 862504

Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94

5 years agoARM: tegra: power: move cluster switch to syscore for LP0
Jin Qian [Thu, 1 Sep 2011 02:47:26 +0000]
ARM: tegra: power: move cluster switch to syscore for LP0

move printk as well since they rely on uart resume in syscore

Bug 862504

Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e
Reviewed-on: http://git-master/r/50240
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b

5 years agoARM: tegra: power: fix lp0 suspend
Jin Qian [Thu, 1 Sep 2011 02:39:57 +0000]
ARM: tegra: power: fix lp0 suspend

enable pllm and skip io_dpd for lp0

Bug 862504

Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7
Reviewed-on: http://git-master/r/50239
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0

5 years agoARM: tegra: power: move cluster switch prolog/epilog from suspend
Jin Qian [Wed, 31 Aug 2011 00:23:55 +0000]
ARM: tegra: power: move cluster switch prolog/epilog from suspend

They're called only when doing cluster switch so move them to
cluster control function.

Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c
Reviewed-on: http://git-master/r/49952
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363

5 years agoARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache
Jin Qian [Wed, 24 Aug 2011 20:51:43 +0000]
ARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache

Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f

5 years agoARM: defconfig: tegra3: use REPORT_PRESENT_CPUS
Jon Mayo [Thu, 28 Jul 2011 00:01:57 +0000]
ARM: defconfig: tegra3: use REPORT_PRESENT_CPUS

enable reporting of present cpus in /proc/cpuinfo and /proc/stat

Bug 849167

Original-Change-Id: I8651079ff63c7399942d937cb0af126aa67a2fd7
Reviewed-on: http://git-master/r/43632
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R24122a5d7e8b2517e99518a698f89ac3946a76ec

5 years agoARM: tegra: power: restore reset handler after lp0
Jin Qian [Wed, 24 Aug 2011 01:15:32 +0000]
ARM: tegra: power: restore reset handler after lp0

Bug 862504

Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7
Reviewed-on: http://git-master/r/50241
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400

5 years agoARM: tegra: Update copyrights
Scott Williams [Wed, 7 Sep 2011 19:21:06 +0000]
ARM: tegra: Update copyrights

Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/51157

Rebase-Id: R5aa782b116daefeb126b3bf58af90a7fd78f648d

5 years agoARM: tegra: whistler: Add sound support
Sumit Bhattacharya [Tue, 30 Aug 2011 16:34:55 +0000]
ARM: tegra: whistler: Add sound support

Bug 862023

Change-Id: I32d8406a7c1d88b09156b94dda2a2b47e89e515f
Reviewed-on: http://git-master/r/49874
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R1114efe2768c40b0615a8e22639b01372688a5be

5 years agoARM: tegra: Clean up the chip revision decoder
Scott Williams [Wed, 7 Sep 2011 00:19:18 +0000]
ARM: tegra: Clean up the chip revision decoder

Replace the chip revision decoder with something that is more
extensible and maintainable.

Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50931
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136

5 years agoARM: Tegra: Pinmux: Fix drive strength configuration
Pavan Kunapuli [Fri, 2 Sep 2011 10:02:00 +0000]
ARM: Tegra: Pinmux: Fix drive strength configuration

In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.

Bug 870369

Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704
Reviewed-on: http://git-master/r/49872
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd

5 years agoARM: tegra: power: Tune Tegra3 hotplug algorithm
Alex Frid [Wed, 24 Aug 2011 05:52:42 +0000]
ARM: tegra: power: Tune Tegra3 hotplug algorithm

- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.

- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%

Added tunables:

/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level

Bug 865176
Bug 867186

Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128

5 years agoARM: tegra: pinmux: Prevent access to uninitialized pin groups
Scott Williams [Wed, 31 Aug 2011 15:37:27 +0000]
ARM: tegra: pinmux: Prevent access to uninitialized pin groups

There is no guarantee that every element in the pin group array
will be used (i.e., initialized) for a particular SOC. Prevent
access to pin group array elements that are not initialized.

Original-Change-Id: I90ea3616f8508b12ffe4a7daf9ff4b2bac057075
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50059
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd6c206b805d180fb3c52be52edfeebed701ca73d

5 years agoARM: tegra: speed up framebuffer copy
Jon Mayo [Tue, 30 Aug 2011 01:09:16 +0000]
ARM: tegra: speed up framebuffer copy

Use a memcpy with less overhead in tegra_move_framebuffer, this makes
this function about 30 times faster.

Bug 843089

Original-Change-Id: I4ae9127db6d5ff5d9680e3ff2c3d28463395e39b
Reviewed-on: http://git-master/r/49735
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: R0906917433643ac4ce9ac97284007527ef2d67df

5 years agoarm: tegra: iovmm: Fixed configurablability advertised in Makefile
Hiro Sugawara [Thu, 25 Aug 2011 21:14:02 +0000]
arm: tegra: iovmm: Fixed configurablability advertised in Makefile

CONFIG_TEGRA_IOVMM_SMMU now can be independently disabled and
the kernel still builds.

Original-Change-Id: I009319352f4b125941a58132d2be8d5f36411aab
Reviewed-on: http://git-master/r/49278
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb663949db3e3fcfa6418f71cdc74662dded08fc6

5 years agoARM: tegra: Use SATA and PCIE SOC architecture conditionals
Scott Williams [Thu, 1 Sep 2011 23:20:47 +0000]
ARM: tegra: Use SATA and PCIE SOC architecture conditionals

Use the SOC architecture conditionals for determining the
presense of PCIE and SATA.

Change-Id: I312d0d1b45fc08e4938260b978d083b113ed9d66
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50379
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra949d477a8e96ccc7760c4974ae93909ea054bbb

5 years agoARM: tegra: Only enable fuse programming on silicon platforms
Scott Williams [Tue, 30 Aug 2011 00:31:46 +0000]
ARM: tegra: Only enable fuse programming on silicon platforms

Fuse programming is possible only on silicon platforms.
Do not enable it for simulation or FPGA platforms.

Change-Id: If1bec072eeaae1ee95720a37e37fcb7c8e8ee464
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49724
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R71d2073c18353d32a2b5373819f2e27e1e8bb680

5 years agoARM: tegra: Clean up makefile conditionals
Scott Williams [Thu, 1 Sep 2011 22:07:44 +0000]
ARM: tegra: Clean up makefile conditionals

Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50358
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2

5 years agoARM: tegra: Clean up power gating code
Scott Williams [Thu, 1 Sep 2011 22:03:48 +0000]
ARM: tegra: Clean up power gating code

Clean up conditionals.
Use the generic name of CELP for the LP partition.

Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a

5 years agoARM: tegra: Remove unnecessary SOC conditionals
Scott Williams [Thu, 1 Sep 2011 21:59:01 +0000]
ARM: tegra: Remove unnecessary SOC conditionals

Change-Id: I4ad09ea97db373dbed0764214fc5d98be2e29f7a
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50356
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5c2b9b638a4e150eb1fa6e1d4f587bb71622efea

5 years agoARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets
Scott Williams [Thu, 1 Sep 2011 21:55:13 +0000]
ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets

Determine the number of GPU register sets based upon the setting
of ARCH_TEGRA_DUAL_3D.

Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50355
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96

5 years agoARM: tegra: Only Tegra3 has TSENSOR
Scott Williams [Thu, 1 Sep 2011 21:47:32 +0000]
ARM: tegra: Only Tegra3 has TSENSOR

Change-Id: I232d3ae5e037d491d1d8d185e75c1c9a7035cd4c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50354
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R899f3aaf97ca7f21785749a8675ba1bc461f81f9

5 years agoARM: tegra: Use forward looking architecture conditionals
Scott Williams [Thu, 1 Sep 2011 02:24:56 +0000]
ARM: tegra: Use forward looking architecture conditionals

Change-Id: I31f2717327a627ad83e4cc2f083b71fd68fb1465
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50221
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcaef7248cf06aa01c40b8e5eae13e3a20ed097d3

5 years agoARM: tegra: Add SOC architectural capabilities
Scott Williams [Thu, 1 Sep 2011 15:56:31 +0000]
ARM: tegra: Add SOC architectural capabilities

Add architectural capabilities the at are selected by the top-level
architecture type rather than deriving this knowledge directly from
the top-level type in the code.

Change-Id: I1c1e5d986a65301cf2e474d866f01e4f8c2a5505
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50298
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R118b523b4c6cac8f4f530f01a1d14ed961d5a085

5 years agoARM: tegra: Fix warnings
Scott Williams [Thu, 25 Aug 2011 21:28:10 +0000]
ARM: tegra: Fix warnings

Change-Id: Ic2cecccf0f4f6e6ca612af2ee07acdbca2ce07a5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49281
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R59e04e0a46099403284a036de7f35d21c6188d81

5 years agoARM: tegra: power: Call cluster_switch_prolog/epilog for LP1
Yudong Tan [Thu, 18 Aug 2011 22:29:08 +0000]
ARM: tegra: power: Call cluster_switch_prolog/epilog for LP1

cluster_switch_prolog is needed to set up car/flow controller registers
for LP1 entry. epilog is needed to clean up some flags in flow controller
after LP1 exit.

Bug 862502

Change-Id: Ib9eeac6fc541cfa644d782071dbd4187255404d8
Reviewed-on: http://git-master/r/47585
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2c72673ba1b7f04ffa1b760ff54aaf73cf23f09e

5 years agoARM: tegra: power: Correct settings for the BURST_POLICY register
Yudong Tan [Wed, 17 Aug 2011 18:30:00 +0000]
ARM: tegra: power: Correct settings for the BURST_POLICY register

This is needed to allow clusters come up on CLKM

Bug 862502

Change-Id: I667cccbf6cbc5af0d47ebc07a5c6c83f14a1cc4c
Reviewed-on: http://git-master/r/47584
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2c7ae1605c0d1561c7fa40f45d09ee073d920497

5 years agoARM: tegra: power: Enable LP1 power mode for cluster switch
Yudong Tan [Wed, 17 Aug 2011 18:29:12 +0000]
ARM: tegra: power:  Enable LP1 power mode for cluster switch

Bug 862502

Change-Id: Id119be010eadeaaebeea9a3c78313500f8dc481b
Reviewed-on: http://git-master/r/47583
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R80a63d66336349a3c05da17e4565902390763e74

5 years agoARM: tegra: power: implement LP1 suspend/resume for Tegra3
Yudong Tan [Thu, 18 Aug 2011 22:26:52 +0000]
ARM: tegra: power: implement LP1 suspend/resume for Tegra3

Bug 862502

Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722
Reviewed-on: http://git-master/r/47398
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef

5 years agoARM: tegra: power: fix cpu context save page mapping
Jin Qian [Tue, 23 Aug 2011 04:29:48 +0000]
ARM: tegra: power: fix cpu context save page mapping

Change-Id: Ie2bcc74d4a4fb76ee29c4a01e5dae72261da4885
Reviewed-on: http://git-master/r/48623
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5ee134042966de7a620f60095169e3aba823cd82

5 years agoARM: tegra: power: Fix non-SMP LP2 timer registration issues
Scott Williams [Fri, 26 Aug 2011 01:48:42 +0000]
ARM: tegra: power: Fix non-SMP LP2 timer registration issues

Don't call irq_set_affinity() on non-SMP systems.

Change-Id: I728d5163bff3fb2bd4a2ea7946d2e57cb0854589
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49346
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R470db120396c95bdcafc48ba357652a43d63da82

5 years agoARM: tegra: power: Fix build error on non-SMP systems
Scott Williams [Fri, 26 Aug 2011 01:39:56 +0000]
ARM: tegra: power: Fix build error on non-SMP systems

Can't use NR_CPUS on non-SMP systems. Just use the maximum.

Change-Id: Ie0d6289c3b8bdaada6335e4670c9f6b5ab2bcc93
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49344
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R58abf556bf542b8cf0ee6dd0f091806235f49623

5 years agoarm: tegra: Increase max irq of system by 64.
Laxman Dewangan [Wed, 24 Aug 2011 13:26:38 +0000]
arm: tegra: Increase max irq of system by 64.

Increasing the maximum irqs of system to +64 from
internel irqs of socs.

bug 822562

Original-Change-Id: Ib032232efd59ea7c1ccaa36b62d1fffcaa2c09b1
Reviewed-on: http://git-master/r/48984
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R7f7869796b99a52466d815412792f0357a902269

5 years agoARM: tegra: timer: Use common chip id functions
Scott Williams [Wed, 24 Aug 2011 20:43:42 +0000]
ARM: tegra: timer: Use common chip id functions

Original-Change-Id: Ibf7a37c0751924f0a8de4932d0d31b6fe6c3c4e8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49049
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rfcfb080975c0f844487b91167fc455882f0cb5f4

5 years agoarm: tegra: add edp limit to debugfs
Joseph Lehrer [Fri, 19 Aug 2011 22:36:13 +0000]
arm: tegra: add edp limit to debugfs

bug 865842

Original-Change-Id: I54dcf3e2e968692746f1d8b17bdf912305f547a2
(cherry picked from commit 5b9dce25485824036f86db093b28a45a3cd86c76)
Reviewed-on: http://git-master/r/48257
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1adb1ca832e0f63f1e5b7e405f4c87c4a8a7aabe

5 years agoarm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values
Mayuresh Kulkarni [Mon, 22 Aug 2011 13:37:25 +0000]
arm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values

The pin-func set by board-xxx-pinmux.c should be one of the 4 possible
values of the pin-func in master pinmux table. Also the safe pin-func
setting should follow the same rule.

If this is not followed then, warnings will be seen whenever a driver
tries to set a pin-func that is not in the master pinmux table. This is
specically seen for the mux values RSVD_X.

The hardware is always programmed with the bit value of setting
(00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table.

For bug 865503

Change-Id: I3933ca0002e099376798cc131690922fefa16868
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48197
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R6d5a11f9f3ab523a2557a512ab85c3ef5f90815a

5 years agoarm: tegra: pinmux: fix a few warnings for Tegra2
Mayuresh Kulkarni [Fri, 19 Aug 2011 13:52:17 +0000]
arm: tegra: pinmux: fix a few warnings for Tegra2

APIs lock_name(), od_name(), ioreset_name() are called from code for
Tegra3 and above. However, their implementation was not taking care
of this. This was causing 3 warnings during Tegra2 builds.

Change-Id: I4ac4d394c68fd1f8bab5938b2af76c8b92d04a64
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48195
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R4e7e7a4ec3cd7b31a2297bdeedccedc8cbcb5a01

5 years agoARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster control
Scott Williams [Tue, 23 Aug 2011 21:23:18 +0000]
ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster control

Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48798
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f

5 years agoARM: tegra: Add CONFIG_TEGRA_CLUSTER_CONTROL
Scott Williams [Tue, 23 Aug 2011 20:42:44 +0000]
ARM: tegra: Add CONFIG_TEGRA_CLUSTER_CONTROL

Change-Id: I562fb5abaf767572094f3c163a105dc4974a7139
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48797
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb67f65cb0866e66787eddb16533f0928ddcb3ea9

5 years agoARM: tegra: Fix build errors when PM_SLEEP is not selected
Scott Williams [Tue, 23 Aug 2011 22:52:45 +0000]
ARM: tegra: Fix build errors when PM_SLEEP is not selected

Change-Id: I2037be4b1309ac1fe9af0ec3e644e0a1a4924857
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48796
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R0840ee98b17984f73f9a5396ab6f86d4d92b744e

5 years agoARM: tegra: power: Fix premature clock event broadcast mode
Scott Williams [Tue, 23 Aug 2011 18:00:41 +0000]
ARM: tegra: power: Fix premature clock event broadcast mode

Do not switch to clock event broadcast mode until the final CPU
is going into LP2. Switching into broadcast mode on the secondary
CPUs can cause double ticking and/or kernel panics on the primary.

Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48743
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5

5 years agoARM: tegra: Enable CONFIG_TEGRA_EDP_EXACT_FREQ
Diwakar Tundlam [Fri, 19 Aug 2011 02:19:35 +0000]
ARM: tegra: Enable CONFIG_TEGRA_EDP_EXACT_FREQ

Toggle to using exact EDP table frequencies as default

Bug 863761

Original-Change-Id: Idbcbe870ae3266c2e5d5aefad6869632284b052b
Reviewed-on: http://git-master/r/47991
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7c305f4357d5cbb0700176fa37c6adf4fe39a9a1

5 years agoARM: tegra: Avoid timer calibration on slave cpu's.
Krishna Reddy [Fri, 19 Aug 2011 01:55:05 +0000]
ARM: tegra: Avoid timer calibration on slave cpu's.

Use the value calibrated by master cpu.
Bug 843553

Original-Change-Id: I88939f37050873e0633782f6a927ffaf9b8d776d
Reviewed-on: http://git-master/r/47988
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6520764a88346d5ab4a180810636b04ce474f4d7

5 years agoARM: tegra: pm: Do not use ioremap for sys mem
Prashant Gaikwad [Wed, 3 Aug 2011 09:19:20 +0000]
ARM: tegra: pm: Do not use ioremap for sys mem

ARMv6+ architecture does not allow ioremap on system memory.
lp0 is relocated using ioremap on DRAM. If lp0 vector start address
is in system memory then use memblock_reserve and do not relocate.
Else if it is overlapping with carveout/fb then first remove the
carveout/fb using memblock_remove and then use ioremap.

Bug 827199

Reviewed-on: http://git-master/r/43685
(cherry picked from commit 1753408edc65ebfc0d4d203f2be960d49ca747a8)

Original-Change-Id: Ic4abfbc98b43aafb2756cb3e69d0ee178204ec7d
Reviewed-on: http://git-master/r/44717
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re90d5554c301471fd177632887741109318c2c97

5 years agoarm: tegra: pm: Relocate lp0 vector
Prashant Gaikwad [Wed, 3 Aug 2011 09:11:14 +0000]
arm: tegra: pm: Relocate lp0 vector

LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.

Bug 827199

Reviewed-on: http://git-master/r/42113
(cherry picked from commit 9a3993d39599d1637d7c04218e6a634f914e9f91)

Original-Change-Id: If862f6ff61a316c478806b7dc3deff70a2861410
Reviewed-on: http://git-master/r/44716
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R085bc615567c70b7ff3b0ba1aee375fb29a72bfd

5 years agoARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x441/551
Diwakar Tundlam [Mon, 8 Aug 2011 18:55:15 +0000]
ARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x441/551

Bugid 860893

Original-Change-Id: Ia48b5b98917d75fd4fe9cafe595558e6dd17906b
Reviewed-on: http://git-master/r/45883
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd737556e04ed64c42e4fbb7f5477aa8441a00616

5 years agoARM: tegra: Fix warnings when CONFIG_PM_SLEEP is not selected
Scott Williams [Wed, 17 Aug 2011 22:53:11 +0000]
ARM: tegra: Fix warnings when CONFIG_PM_SLEEP is not selected

Change-Id: If06bd6a9030c8b1502c96459eb6657a6bff4b0fa
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47634

Rebase-Id: R2982ec1b130417178376a06bb37f24aaf65ec19f

5 years agomedia: tegra: avp: Clear interrupt registers when AVP starts
Kaz Fukuoka [Thu, 26 May 2011 01:21:32 +0000]
media: tegra: avp: Clear interrupt registers when AVP starts

There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.

This change also removes the workaroud for the bug.

bug 827353
bug 826234

Original-Change-Id: I51546400f0bace67dfcdb23f667c051c060d3983
Reviewed-on: http://git-master/r/33083
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Re8d35d9a62267d2a66f7eb4e754651edafdbb536

5 years agoarm: tegra: pinmux: Fix RSVD search condition.
Jin Park [Fri, 19 Aug 2011 08:11:42 +0000]
arm: tegra: pinmux: Fix RSVD search condition.

There is the potential problem in RSVD search routine, if mux function
index is masked by 0x3.

Original-Change-Id: Ieb823db5a304c0db6e898f29193d32bac3e34c38
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/48093
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Rdcf3a9747fab2f3aace0f7ee4b5b39f5ae497549

5 years agoARM: tegra: power: Don't clip EDP limits to cpufreq tables
Peter Boonstoppel [Tue, 16 Aug 2011 19:01:29 +0000]
ARM: tegra: power: Don't clip EDP limits to cpufreq tables

Always use maximum possible frequency when applying EDP
capping. Toggled through CONFIG_TEGRA_EDP_EXACT_FREQ.

Bug 863761

Original-Change-Id: I327440546991ad4f3abc78100a3a18017f3464b6
Reviewed-on: http://git-master/r/47169
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rdafcd7202975dd85631b4d281012343c5cda08be

5 years agoARM: tegra: power: Wait for power-gate toggle completion
Alex Frid [Tue, 9 Aug 2011 04:02:51 +0000]
ARM: tegra: power: Wait for power-gate toggle completion

Bug 857044

Original-Change-Id: I80c8c2183426fbaa8b7d5316c09709c9de7ea39d
Reviewed-on: http://git-master/r/45970
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd8c46b56d4ca22e05e40c664329d64f7bd6710f7

5 years agoARM: tegra: la: set LA to max for zero bandwidth requests
Michael Frydrych [Mon, 15 Aug 2011 12:23:06 +0000]
ARM: tegra: la: set LA to max for zero bandwidth requests

Requesting to set LA for zero bandwidth would otherwise
cause division by zero exception in LA computation. LA can
safely be set to max in this case.

Original-Change-Id: Id234e2432c7c21b7ab3d13614d0f9fbd82199cde
Reviewed-on: http://git-master/r/47132
Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com>
Tested-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R58676140d46d2b7b2b2c117a03f088944a8f4382

5 years agoARM: tegra: dvfs: Retry rail update
Alex Frid [Sat, 13 Aug 2011 07:38:41 +0000]
ARM: tegra: dvfs: Retry rail update

Since rail voltage change may be limited by from-relationship with
another rail, retry rail update to account for circular dependencies.

Bug 864112

Original-Change-Id: Ie45f656a74eac925ab2383fbe620fad47742d02f
Reviewed-on: http://git-master/r/47233
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R8f9435fb610c27605cdc043ebf2ef13a29377c3d

5 years agoARM: tegra: Added CONFIG_TEGRA_EDP_EXACT_FREQ
Peter Boonstoppel [Tue, 16 Aug 2011 18:58:30 +0000]
ARM: tegra: Added CONFIG_TEGRA_EDP_EXACT_FREQ

Used to toggle using exact EDP table frequencies

Bug 863761

Original-Change-Id: I5e6963504a7b472ff8431fe2e646bee52a26aaec
Reviewed-on: http://git-master/r/47362
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R294e6875dfeb503f5a9880dea15e17cebb7a36de

5 years agoarm: tegra: tsensor: fuse revision corrected
Bitan Biswas [Fri, 12 Aug 2011 09:32:31 +0000]
arm: tegra: tsensor: fuse revision corrected

tsensor functionality is enabled based on fuse revision.
The fuse revision is to be interpreted as an unsigned integer
while it is interpreted as a decimal number. Corrected this
in platform source file.

bug 863460

Original-Change-Id: Iaf9676d559bb7fb3555c7b731aa018f949441c8e
Reviewed-on: http://git-master/r/46901
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R8a85e2ce060dd3110c374b30d0018c7512b22113

5 years agoARM: tegra: power: Support for resetting module
Chris Johnson [Fri, 12 Aug 2011 05:58:17 +0000]
ARM: tegra: power: Support for resetting module

Add support for resetting a module.

Bug 625545

Original-Change-Id: Ibc5e57d73085e85f3d1184d0657d9bc650b28e4e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/46870
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcaa388b315159b1cc69dd29dd03176f4136bd285

5 years agoARM: tegra: power: Separate throttling code
Alex Frid [Wed, 10 Aug 2011 21:42:54 +0000]
ARM: tegra: power: Separate throttling code

Moved tegra CPU throttling algorithm implementation into a separate
file. For now, the same algorithm is used for both Tegra2 and Tegra3
architecture.

Original-Change-Id: I478c32b5adee4c946472129b89615580c10b41e1
Reviewed-on: http://git-master/r/46748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R2340f78e1d22942022e171044d6b20f260e2d312

5 years agoARM: Tegra: Cardhu: Setting sdmmc drive strengths
naveenk [Fri, 12 Aug 2011 14:16:35 +0000]
ARM: Tegra: Cardhu: Setting sdmmc drive strengths

configuring sdmmc drive strengths as suggested
by HW team based on Characterization results

Bug 799568

Original-Change-Id: Id30505659aefb9c63a24f8baa8296a62723710b4
Reviewed-on: http://git-master/r/46949
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R557938d130efb48eaa6f9e1b584f13505aa200a6

5 years agoARM: tegra: la: remove printf warning
Jon Mayo [Wed, 10 Aug 2011 23:20:48 +0000]
ARM: tegra: la: remove printf warning

arch/arm/mach-tegra/latency_allowance.c:499: warning: format '%4u'
expects type 'unsigned int', but argument 4 has type 'long unsigned int'

Original-Change-Id: Idfea3e60da375bfe903e1a517505c727ecc83d72
Reviewed-on: http://git-master/r/46495
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8eeb5ccc518d9591fa1a9a521913b17ec28c6b52

5 years agoARM: tegra: power: Update to EDP table
Peter Boonstoppel [Thu, 11 Aug 2011 00:38:44 +0000]
ARM: tegra: power: Update to EDP table

 - updated EDP table for AP30 A02 2.5A to match data from Bug 844268
 - updated EDP cap for single core on AP30 A02 to 1.3Ghz
 - changed EDP table for A01 to match AP30 A02

Original-Change-Id: I1722768f235d63a2f311d082d8126ba071226eb6
Reviewed-on: http://git-master/r/46482
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc98aaffd4568b9ad642696eef5f559d9c7fd7237

5 years agoARM: tegra: la: use lower LA for display clients
Jon Mayo [Wed, 10 Aug 2011 23:16:10 +0000]
ARM: tegra: la: use lower LA for display clients

In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.

Bug 840688

Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1

5 years agoARM: tegra: clock: Use rounded ActMon maximum rate
Alex Frid [Sat, 6 Aug 2011 01:56:04 +0000]
ARM: tegra: clock: Use rounded ActMon maximum rate

Used round rate API to determine maximum frequency of Tegra3 activity
monitoring shared users, instead of maximum rate directly. The former
takes into account available PLL/dividers and return actually
reachable frequency.

Bug 860618

Original-Change-Id: I48292c65bfbf58906ab59f86959b0e7155117558
Reviewed-on: http://git-master/r/45711
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Tested-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R2be5b1549b53d2b203ccfe6ea1d1cd2368359d91

5 years agoARM: tegra: cardhu: switch off PMU at high temperature
venu byravarasu [Wed, 3 Aug 2011 11:21:57 +0000]
ARM: tegra: cardhu: switch off PMU at high temperature

Add board support needed for PMU switch off when tsensor
detects temperature > TH3 threshold set.

bug 850047

Original-Change-Id: I7a283cedc735264dd8ea52801f7f1a103e9293cb
Reviewed-on: http://git-master/r/41531
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rddb801325d32043d1dd127a8850adc50c67b4fee

5 years agoarm: tegra: devices: Add PMC IO address in SE resources
Kasoju Mallikarjun [Wed, 3 Aug 2011 18:17:12 +0000]
arm: tegra: devices: Add PMC IO address in SE resources

Added PMC IO registers as platform resources of
Security Engine for storing context save buffer
address in PMC registes during context save.

Bug 855476

Original-Change-Id: I3bd5791743b157139d61ecea3d3e1ef131d8cce5
Reviewed-on: http://git-master/r/44808
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>

Rebase-Id: Rd5030cf1659887cedd9f60b00224ad7dddd7cd8c

5 years agoARM: tegra: la: Add debugfs to latency allowance.
Jon Mayo [Thu, 21 Jul 2011 01:49:00 +0000]
ARM: tegra: la: Add debugfs to latency allowance.

add /sys/kernel/debug/tegra_latency/la_info to print programmed latency
allowance settings.

Original-Change-Id: I65a7a04c42f8ac27aaf2c1c953d695bc0bba0c77
Reviewed-on: http://git-master/r/42285
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R540ef9a4ed274eae52800edcd6ad590e16b67e09

5 years agoARM: tegra: Disable PL310 double line fill feature
Scott Williams [Thu, 4 Aug 2011 04:56:02 +0000]
ARM: tegra: Disable PL310 double line fill feature

Bug 854424

Original-Change-Id: I53a86b023920978cee0e6804985dd35d1f286de5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/44930
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R0c3899291fd85be56c6e93c02d072fd9cd6dd116

5 years agoARM: Tegra: dvfs: Proc array indep of new T30 char SKUs
Diwakar Tundlam [Thu, 23 Jun 2011 04:17:19 +0000]
ARM: Tegra: dvfs: Proc array indep of new T30 char SKUs

- Make process_ids array independent of SKU to avoid confusion when
  detecting SKU, speedo_id and parsing process_id.
- Added SKU definitions for characterization SKUs of AP30, T30, T30S

Bug 855816

Original-Change-Id: I925d54ab6d35e8af038cbfe84ef4b4c076cd596d
Reviewed-on: http://git-master/r/43096
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R832f8fb1a34ab700af0c6389fbe5307f334cc54c

5 years agoarm: tegra3: Keep DAP2 in maximum driver strength
Laxman Dewangan [Tue, 2 Aug 2011 08:46:48 +0000]
arm: tegra3: Keep DAP2 in maximum driver strength

Setting maximum driver strength of DAP2 in all tegra3
based system by default.

bug 820361

Original-Change-Id: I2f992f4779e7babe76a5dc7a679bee53b3369c9a
Reviewed-on: http://git-master/r/44497
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R03343987d0b060291c323558f5eaf96b63cd2321

5 years agoarm: tegra: enterprise: EDP support
Diwakar Tundlam [Mon, 25 Jul 2011 22:50:18 +0000]
arm: tegra: enterprise: EDP support

Added EDP support for Enterprise board via ext temp sensor nct1008

Bug 824621

Original-Change-Id: I476b9ad2cb46620d4775e6ee6e102b45f2b4dc27
Reviewed-on: http://git-master/r/43144
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0a59e82334166da1abfbc5a748ff4285e66590a4

5 years agoarm: tegra: fuse: tsensor specific fuse public API added
Bitan Biswas [Thu, 21 Jul 2011 12:02:53 +0000]
arm: tegra: fuse: tsensor specific fuse public API added

Defined public fuse API to extract tegra3 tsensor configuration
parameters.

bug 851791

Original-Change-Id: Ia14e2d515ee1d695556492464e8ceaf4b0d13477
Reviewed-on: http://git-master/r/42367
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1090e6ad78bcef23670ff647de86e695780f5b76

5 years agoARM: tegra: power: Add package mask to IO pad control
Alex Frid [Sun, 24 Jul 2011 03:14:25 +0000]
ARM: tegra: power: Add package mask to IO pad control

Modified dynamic IO pad configuration control to support SoC package
dependencies: set into "no-io-power state" IO pads that are not bonded
out on the particular package. Updated IO power detect table to account
for differences in Tegra2 and Tegra3 architecture.

Bug 853132

Original-Change-Id: I5f0aedfa784173cc37251ccf4e1dfb4d919db96e
Reviewed-on: http://git-master/r/42785
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R46208845c32e25340de6b1cebfb6b617c6c7ce4d

5 years agovideo: tegra: dc: fix tiled memory efficiency
Xin Xie [Thu, 7 Jul 2011 21:05:04 +0000]
video: tegra: dc: fix tiled memory efficiency

Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.

BUG 847731

Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1
Reviewed-on: http://git-master/r/40074
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb0846a0b29dc838a3bb1e76c3a59da0bfc5bbf12

5 years agoarm: tegra: fuse: declare tegra_fuse_regulator_en() as extern
Varun Wadekar [Tue, 19 Jul 2011 09:26:23 +0000]
arm: tegra: fuse: declare tegra_fuse_regulator_en() as extern

platforms need to implement their fuse power on
functions if they do not use regulators to power
on the fuse block

Bug 836963

Reviewed-on: http://git-master/r/#change,41737
(cherry picked from commit 02747e1ddd8391dbb73ee04493417846508ebfbc)

Original-Change-Id: I1f462c1e92574e8f64ce2158a4fee8be7f5441ce
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/42821
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rf223f5756750cd010c55c69d68628107d46c5fa0

5 years agoARM: tegra: power: Control IO pad configuration dynamically
Alex Frid [Wed, 20 Jul 2011 23:15:25 +0000]
ARM: tegra: power: Control IO pad configuration dynamically

Tegra IO pads are automatically re-configured when IO power level is
changed. Current code keeps auto-detection cells in default, active
state all the time. This change will allow turning off cells when IO
power is stable, and activate them only during power transitions.

In addition IO pads will be set into "no-io-power" state after the
respective regulator is disabled, and re-configured back for regular
operations before regulator is re-enabled.

Dynamic IO pad control introduced in this commit is still disabled
by default on all tegra platforms.

Bug 853132

Original-Change-Id: Ifc7bbe2ac34929c14f8f8e9feaa4290b78fe6cf6
Reviewed-on: http://git-master/r/42263
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8b7c7863c1580816a2f3b28bdb3c228a97a18736

5 years agoarm: tegra: ahci/sata: enable sata rails/partition at init
Yen Lin [Sun, 10 Jul 2011 23:07:39 +0000]
arm: tegra: ahci/sata: enable sata rails/partition at init

Enable sata rails and sata partition when driver initializes
- add sata_oob and cml1 clocks to sata powergate partition.
- set sata and sata_oob clock source using clk_set_parent API.
- fix a bug in while(timeout) loop

Bug 836589

Original-Change-Id: Iddc08bf851ffc83d45bd6aed4df85cde3b13f0e4
Reviewed-on: http://git-master/r/41314
Tested-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R500e99ac50d1e3c0851958b1c83316dded00d617

5 years agoARM: tegra: power: Add throttling enable reference counting
Alex Frid [Sun, 10 Jul 2011 06:22:12 +0000]
ARM: tegra: power: Add throttling enable reference counting

Added throttling enable reference counting, so that it can be
controlled by drivers for different thermal sensors (e.g, on
chip and device skin sensors).

Fixed possible dead-lock when cancel delayed work synchronous is
called while locked with the very same mutex that protects work
function.

Bug 837005

Original-Change-Id: If2aa8aa16f4a3b3497def592503213522fd38e54
Reviewed-on: http://git-master/r/40534
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R893b5a7b402d327b40acb7adbadb53f930804c0d

5 years agoARM: tegra: clock: Unify CPU set rate paths
Alex Frid [Sun, 10 Jul 2011 04:33:37 +0000]
ARM: tegra: clock: Unify CPU set rate paths

Made sure that CPU thermal and edp limits are applied on all CPU set
rate paths: cpufreq governor, thermal throttling, edp notification,
power management notification. Also included auto-hotplug governor
state update in all these paths (current code does not apply the
limits, or does not include auto-hotplug on some rate change paths).
One exception - keep current functionality for suspend notification:
set pre-defined CPU rate, and force auto-hotplug idle state.

Original-Change-Id: I54531f8f919ce248b2b56f5aa56f39e2efcb568a
Reviewed-on: http://git-master/r/40533
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R1471a5f318644fa5a7f436d8ed73c12de8b76245

5 years agoARM: tegra: power: Re-factor power headers.
Alex Frid [Sun, 10 Jul 2011 01:38:04 +0000]
ARM: tegra: power: Re-factor power headers.

Renamed and moved tegra cpu related function prototypes from power.h
to tegra-cpu.h. No functional changes.

Original-Change-Id: I24c25c9434bf7008e0875d1f74be502cd902c4ba
Reviewed-on: http://git-master/r/40532
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3d90799453a86a5a9ed012d2bfe373715de6d5c3

5 years agoARM: tegra: Add GPIO_PEE3 for Tegra3
Harry Hong [Fri, 8 Jul 2011 06:18:35 +0000]
ARM: tegra: Add GPIO_PEE3 for Tegra3

Original-Change-Id: I9a02b7a79b4bbf0139b5f0a6ad26f7c2eaf9582d
Reviewed-on: http://git-master/r/40144
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R79516993533f5681445de76470cb90025e073474

5 years agoARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz
Alex Frid [Fri, 15 Jul 2011 04:35:48 +0000]
ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz

Original-Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b
Reviewed-on: http://git-master/r/41141
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R47886089e5b3b73c58372645ec7ea282a0cfa698

5 years agoARM: tegra: power: Added global EDP Capping table
Peter Boonstoppel [Fri, 15 Jul 2011 17:54:05 +0000]
ARM: tegra: power: Added global EDP Capping table

 - Added table with EDP Capping values for different SKUs/regulator
   currents in new file edp.c
 - New entry point tegra_init_cpu_edp_limits()
 - Added DebugFS entry under debug/edp to list the currently
   selected EDP table
 - Populated EDP table in edp.c with data from Bug 844268
 - edp.c keeps main EDP table; cpu-tegra.c and board-cardhu-power.c
   both read from there

Bug 840255

Original-Change-Id: I55c2ee16278be8cd3005218bedebe76846d137d8
Reviewed-on: http://git-master/r/40938
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc598b39c3517e10c3c5052258e5a3e444f092b96

5 years agoARM: tegra: clock: Fix activity monitor resume
Alex Frid [Mon, 18 Jul 2011 23:20:54 +0000]
ARM: tegra: clock: Fix activity monitor resume

Move call to clock get rate API (can sleep) outside of activity
monitor resume section protected by spin lock.

Original-Change-Id: I78d5bb8728f3a728a6ff952b1f3cba19b9dec0a0
Reviewed-on: http://git-master/r/41626
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1ab0bb59a88f078f85f125b968546c09aab9d176

5 years agoarm: tegra: Console suspend for all boards
Laxman Dewangan [Mon, 18 Jul 2011 06:17:13 +0000]
arm: tegra: Console suspend for all boards

Added the board level suspend/resume and call the console
suspend from board level suspend/resume.

bug 820536

Original-Change-Id: I246265241246dc0682870571c927bd23023e5aca
Reviewed-on: http://git-master/r/41448
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: R8cde19092af981f1ac31a423aa035924b4353142

5 years agoarm: tegra: suspend: Add board specific suspend/resume calls
Laxman Dewangan [Tue, 12 Jul 2011 10:46:14 +0000]
arm: tegra: suspend: Add board specific suspend/resume calls

Adding board specific suspend and resume call apis through platform
data.
Added call of these function at appropriate stage of suspend/resume.

Added mechanism to select the uart debug channel base address through
variable so that board file can directly change this.

bug 820536
bug 832273

Original-Change-Id: Ia9ff3b8a8d2faa1071a8ff634960e6a6c8a43d40
Reviewed-on: http://git-master/r/34494
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R5c4d212ab07463ecbdf263412d4c7a5962dac5a3

5 years agoARM: tegra: power: Don't use suspended kernel time
Alex Frid [Wed, 13 Jul 2011 19:56:13 +0000]
ARM: tegra: power: Don't use suspended kernel time

Do not use kernel time to time-stamp Tegra3 CPU ULP/G mode switch in
late suspend/early resume when timekeeping is suspended.

Original-Change-Id: Idb6c8f8c2dd2cfc1e00cec53392de12131d6bbe1
Reviewed-on: http://git-master/r/40958
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6ce7a5e7e06949f3536524ea675aa9c0fc2ab097

5 years agoarm: tegra: fuse: accept strings starting with 0x/x
Varun Wadekar [Thu, 14 Jul 2011 09:41:51 +0000]
arm: tegra: fuse: accept strings starting with 0x/x

some users might enter fuse data starting
with 0x/x. this will mess up the fuse programming.
do not consider 0x/x while programming the fuses.

also fix some compilation warnings

Reviewed-on: http://git-master/r/#change,38933

Original-Change-Id: I36b525c71b6d5c437affbaf0724667f8e5984aa6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/41016
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb6a134adfa8049865bb4154353763d43f743e052

5 years agoARM: tegra: clock: Clean tegra3_emc.c macro style
Alex Frid [Wed, 13 Jul 2011 02:34:35 +0000]
ARM: tegra: clock: Clean tegra3_emc.c macro style

Original-Change-Id: I472be800ad84b79783577264b51c6478aa4bb41b
Reviewed-on: http://git-master/r/40769
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0b3b4124618ecafc6f83ff165634ebba664a24a1

5 years agoARM: tegra: clock: Support Tegra3 EMC DFS table revision
Alex Frid [Tue, 12 Jul 2011 05:55:04 +0000]
ARM: tegra: clock: Support Tegra3 EMC DFS table revision

Support Tegra3 EMC DFS table revision 3.1 that includes two additional
EMC shadow registers (reserved with previous table revision 3.0).

Bug 836260

Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb
Reviewed-on: http://git-master/r/40749
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478

5 years agoARM: tegra: clock: Fix Tegra3 EMC clock change procedure
Alex Frid [Tue, 12 Jul 2011 04:43:45 +0000]
ARM: tegra: clock: Fix Tegra3 EMC clock change procedure

Fixed EMC clock change procedure to skip XM2CLKPADCTRL register during
shadow burst write, and set it within unshadowed section.

Bug 836260

Original-Change-Id: Ief92c7d3957c9685b8c528297da2e905159a530d
Reviewed-on: http://git-master/r/40748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R5016ffd224db2b3eb6639a6b33063d1c27456b24

5 years agoARM: tegra: add support for hardware statistic counter
Prashant Gaikwad [Tue, 12 Jul 2011 11:32:54 +0000]
ARM: tegra: add support for hardware statistic counter

Tegra2 chip has a hardware statistic counter for CPU/AVP/VDE/SYS
modules. This commit adds the support for AVP statistics gathering and
controlling avp clock during video playback.

Bug 831892

Reviewed-on: http://git-master/r/35647
(cherry picked from commit 145885b03cd9fc625f2ff3460c59ebbb3d93c98e)

Original-Change-Id: I441acbaf2cb8dd776529bafd4e13f50e31849afa
Reviewed-on: http://git-master/r/39657
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7271973f142f14fc8a11bdbc33ae6f76f6fd38b0

5 years agoARM: tegra: clock: Add Tegra3 emc high voltage bridge
Alex Frid [Wed, 29 Jun 2011 03:50:29 +0000]
ARM: tegra: clock: Add Tegra3 emc high voltage bridge

On Tegra3 platforms emc configurations for DDR3 rates below 300MHz
can not work at high core voltage; the intermediate step (bridge) is
mandatory when core voltage is crossing the 1.2V threshold (fixed for
Tegra3 arch). In addition emc must run above bridge rate if any other
than emc clock requires high voltage.

EMC bridge is implemented as a special emc shared user: its rate is set
once during emc dvfs table initialization; then, the bridge is enabled
or disabled when sbus and/or cbus voltage requirement is crossing the
threshold (sbus and cbus together include all clocks that may require
voltage above threshold - other peripherals can reach their maximum
rates below threshold).

Bug 846693

Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf
Reviewed-on: http://git-master/r/39919
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff

5 years agoarm: tegra: enterprise: init modem according to modem_id
Steve Lin [Mon, 11 Jul 2011 19:45:06 +0000]
arm: tegra: enterprise: init modem according to modem_id

Init baseband modems according to the modem_id passed from the bootloader.

Bug 842870

Original-Change-Id: Ib8cd37877eb50ac67a337ef20dd6c6f631169578
Reviewed-on: http://git-master/r/39273
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb3484d422dd0fbfbd80ac5ef62fe1aa7fa574c52

5 years agoarm: tegra: fuse: support to burn fuses on the field
Varun Wadekar [Thu, 16 Jun 2011 11:08:30 +0000]
arm: tegra: fuse: support to burn fuses on the field

- follow the new sequence shared by the hardware team
- merge Tegra2 and Tegra3.0 odm fuse burning into a single file

Bug 796825

Original-Change-Id: Ia06d589eba95254a410016dce244375f27e22be0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38404
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R740d7bd47eaa6231954ae98686272a755a4bce14