5 years agoarm: mach-tegra: Export dvfs frequencies
Arto Merilainen [Thu, 1 Aug 2013 10:58:51 +0000]
arm: mach-tegra: Export dvfs frequencies

This patch adds a function tegra_dvfs_get_freqs() that allows reading
the possible clock frequencies from dvfs table.

Bug 1330780

Change-Id: I7c1cdc054b0898495c22c2d7dde9cf20ed66d8f5
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/256863
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agodevfreq: Export profile frequency table to sysfs
Arto Merilainen [Thu, 1 Aug 2013 07:14:10 +0000]
devfreq: Export profile frequency table to sysfs

devfreq exported the frequencies based that were available from OPP,
however, some devices that use devfreq do not utilise OPP, but they
give the list of supported frequencies separately for devfreq. This
patch makes devfreq use the given table (if available) and fallback
to OPP.

Bug 1330780

Change-Id: I60ec2eade6066b0c3520f7e372384f0a42734048
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/256695
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra: dvfs: Add CL-DVFS tune high margin data
Alex Frid [Sun, 23 Jun 2013 02:18:37 +0000]
ARM: tegra: dvfs: Add CL-DVFS tune high margin data

Added CL-DVFS tune high threshold margin to dfll data in safe dvfs
table, so that margin value can be updated based on characterization
(rather than using constant macro). Fall back on current 20mV margin,
if safe dvfs does not contain margin data.

Change-Id: I27e18a6b6fa8f1121852dd245f1f25d98547fe84
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241237
(cherry picked from commit c4eb5fa8c641f5767d587e0e5266487ee33995ff)
Reviewed-on: http://git-master/r/262196
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Convert msenc to bus clock
Alex Frid [Thu, 25 Jul 2013 07:13:28 +0000]
ARM: tegra14: clock: Convert msenc to bus clock

Converted msenc to shared bus clock to add automatic parent selection,
and rate rounding up operations.

Bug 1330287

Change-Id: I9e9011896ab4b4368220835227fa3c3ac59f364a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253264
(cherry picked from commit 6e8c1860e2c64bc546d1824bad116702da527d5a)
Reviewed-on: http://git-master/r/262047
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: dvfs: Align core dvfs voltages
Alex Frid [Sun, 21 Jul 2013 01:14:03 +0000]
ARM: tegra14: dvfs: Align core dvfs voltages

Applied cvb voltage alignment to core dvfs steps (not just to nominal
voltage). This was done to avoid mismatch between cvb voltages for
c2bus and dvfs levels for all other core domains.

Change-Id: Ia4dd36bd18aa08b64b40eff3d5c889d6cf240af5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/251655
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 67fd98d52288099b759f5d33c0b9129f99653db1)
Reviewed-on: http://git-master/r/262046
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: clock: Update host1x bus operations
Alex Frid [Fri, 19 Jul 2013 03:10:57 +0000]
ARM: tegra14: clock: Update host1x bus operations

- Allowed low rates source pll selection for rates above low / high
threshold if it provides better approximation of target rate (kept
low rates pll as a sole source of rates below threshold).

- Added directional up-down rounding support

- Adjusted rounding algorithm to always round to closest rate within
+/-1 HZ range regardless of selected rounding direction (up or down).
This is done to avoid jumps across ladder of divider values when
parent rate is not an exact multiple of the divider.

- When switching from high rates source pll to low rates source pll,
skipped attempt to reduce intermittent divider, if it is already at
minimum possible for high rates source pll level (could not happen
anyway).

Change-Id: I41d39e6393216d849f2d58ae0cfdf15fb2be351a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/251165
(cherry picked from commit 9214fa6bf259e73c63b63d5ed0a59050416a2bdd)
Reviewed-on: http://git-master/r/262045
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: dvfs: Add CPU Vmax thermal profile
Alex Frid [Sat, 6 Jul 2013 02:33:42 +0000]
ARM: tegra14: dvfs: Add CPU Vmax thermal profile

Bug 1238772

Change-Id: I43345f42089576cb41267dabfeacbc96858fa136
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245718
(cherry picked from commit f240351a6657c9902c12e1cf788ab2fc0d75a3a0)
Reviewed-on: http://git-master/r/262044
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: dvfs: Synchronize soctherm with CL-DVFS range
Alex Frid [Sun, 23 Jun 2013 04:25:24 +0000]
ARM: tegra14: dvfs: Synchronize soctherm with CL-DVFS range

Added callbacks to adjust soctherm cpu zone configuration when CL-DVFS
is crossing boundary between high/low voltage ranges.

Bug 832603

Change-Id: I33b62055b1624b1ace436612498b99065119bf27
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241238
(cherry picked from commit 630e31fd3579f9a202c3366c780be80e8eb0e686)
Reviewed-on: http://git-master/r/262043
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: dvfs: Set CPU Vmax to 1.23V
Alex Frid [Sat, 6 Jul 2013 01:08:53 +0000]
ARM: tegra14: dvfs: Set CPU Vmax to 1.23V

Bug 1246952

Change-Id: Ia626ea207244b8fdbe5ae4c983b8d0414e0879e0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245717
(cherry picked from commit 43e711a6060b934226e0bceb26acf8a4057b2373)
Reviewed-on: http://git-master/r/262042
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: dvfs: Update tune high margin
Alex Frid [Sun, 23 Jun 2013 02:58:35 +0000]
ARM: tegra14: dvfs: Update tune high margin

Set cpu dfll tune high margin to 40mV (changed from default 20mV) to
match updated dvfs tables.

Change-Id: I3a342ada9e9cad1db475b6a751ca62af9f7f0b61
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245715
(cherry picked from commit 0ce4ee0185303b6da1d8e77446d23a9cbfaa20f5)
Reviewed-on: http://git-master/r/262041
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: clock: Apply thermal floor to EMC suspend
Alex Frid [Sat, 6 Jul 2013 00:19:32 +0000]
ARM: tegra14: clock: Apply thermal floor to EMC suspend

Accounted for VDD_CORE thermal floor when determining minimum required
voltage in EMC suspend.

Bug 1319638
Bug 1234031

Change-Id: Idd4dc9d5c047a0d182d5d14346bdc6950a1374b6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245673
(cherry picked from commit a198751be4857698c0f91dc59139ddd14ce402a3)
Reviewed-on: http://git-master/r/262034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: power: Use rate as pmc register update selector
Alex Frid [Fri, 5 Jul 2013 23:39:29 +0000]
ARM: tegra: power: Use rate as pmc register update selector

Used minimum emc rate required for modem operations in LP1BB/LP0BB to
select emc configuration data block loaded into pmc scratch registers
before entry to LP0 (this commit provides only template for selection:
block 1 is always selected, for now).

Bug 1319638

Change-Id: I0b0322d0d0749356052418d9bf9e3b9f9edf416e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245672
(cherry picked from commit 21843bddaebf3fc2122ae0943b6a56c4fb02aebc)
Reviewed-on: http://git-master/r/262033
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Check BB IPC interrupt in EMC suspend
Alex Frid [Sat, 15 Jun 2013 04:46:33 +0000]
ARM: tegra14: clock: Check BB IPC interrupt in EMC suspend

Bug 1300939

Change-Id: Ie2a637eaee9652d642c480c75a186817819da493
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241186
(cherry picked from commit e18e0da843bbd526fdd6bf4ca0cdda55cfc65303)
Reviewed-on: http://git-master/r/262032
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Update EMC suspend configuration
Alex Frid [Sat, 15 Jun 2013 03:41:53 +0000]
ARM: tegra14: clock: Update EMC suspend configuration

- Set EMC suspend rate to minimum requested by base-band controller
- Specify LP1BB voltage level based on EMC suspend rate (will actually
be set by LP1BB entry code)

Bug 1300939

Change-Id: Ida480539b5a71e13bfd8d00bb19724f4f85927e6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/240305
(cherry picked from commit 4777a040200d582b318ccb247299ddcd4675ac5d)
Reviewed-on: http://git-master/r/262031
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Set/restore emc rate across suspend
Alex Frid [Tue, 11 Jun 2013 06:18:15 +0000]
ARM: tegra14: clock: Set/restore emc rate across suspend

Added mechanism to set emc bus rate (including re-locking plls, when
necessary) on entry/exit to/from suspend. For now, always suspend emc
at 204MHz - this fixed setting will be changed dynamically per BBC
request. Restore original emc rate during resume.

Bug 1300939

Change-Id: I77059aa770fa1fe44f9ffc75887c009204968515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238778
(cherry picked from commit 8ef2a13bde7e798773996e6f03263ab3e9b98125)
Reviewed-on: http://git-master/r/262030
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: clock: Turn Off memory PLLs in resume
Alex Frid [Fri, 14 Jun 2013 02:59:36 +0000]
ARM: tegra14: clock: Turn Off memory PLLs in resume

Turned Off memory PLLs (PLLM or PLLC) in clock resume if they are left
enabled by LP0 or LP1 exit code, but not used as EMC clock sources.

Change-Id: Ife75cd1882a24dce91951577896b3a18cc457442
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/238777
(cherry picked from commit b52d26ef045381e82c0848e1ec2bafadf1abefe6)
Reviewed-on: http://git-master/r/262029
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra14: dvfs: Set core Vmin at cold
Alex Frid [Wed, 19 Jun 2013 06:23:37 +0000]
ARM: tegra14: dvfs: Set core Vmin at cold

Set VDD_CORE minimum voltage to 0.9V at temperatures below 20C.

Bug 1246952

Change-Id: I9f5e32db4be6682ca1b8ccaede046f627268fe9e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/240433
(cherry picked from commit 35771293500147fade86be591e5550e619626ba2)
Reviewed-on: http://git-master/r/262028
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agomedia: video: tegra: Add dependency on legacy DMA
Adam Jiang [Fri, 9 Aug 2013 10:45:19 +0000]
media: video: tegra: Add dependency on legacy DMA

The legacy driver of DTV interface depends on TEGRA_SYSTEM_DMA which was
valid before the new generic dma-engine driver was introduced to
downstream kernel. This patch adds the dependency of legacy DMA code to
prevent from installing DTV driver on new platforms.

Bug 1313737

Change-Id: I137591dd56a5a18056c0b31d318f1ede5bfdcc17
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/260032
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: Add IRQ and resources for DTV
Adam Jiang [Thu, 8 Aug 2013 08:43:16 +0000]
ARM: tegra: Add IRQ and resources for DTV

Change-Id: I3aeda48f5deec8b642270a00dc4a4f28ade65078
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/259891
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomedia: video: tegra: Avoid duplicated unmapping
Adam Jiang [Thu, 8 Aug 2013 08:40:46 +0000]
media: video: tegra: Avoid duplicated unmapping

Unmapped DMA buffers should not be unmapped again. Once DTV driver could
not get DMA channel, it should avoid to map memory for DMA operations.

Bug 1313737

Change-Id: I63e3bde6055a76e1fdf96b1fc55ac5254d18f40a
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/259890
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: loki: Register bq27441 fuel gauge for loki
Chaitanya Bandi [Tue, 6 Aug 2013 01:36:04 +0000]
ARM: tegra: loki: Register bq27441 fuel gauge for loki

Bug 1321186

Change-Id: I9a39270f0ea18ece96f23920aa4e134292df1f52
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/261287
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agopower: bq27441: Add bq27441 fuel gauge driver
Chaitanya Bandi [Tue, 6 Aug 2013 01:30:33 +0000]
power: bq27441: Add bq27441 fuel gauge driver

Added the fuel gauge driver for bq27441.

Bug 1321186

Change-Id: If07ed2ff0b893fc165d54c569c5d41fe4a7b0abe
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/259781
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Add dvfs tables to debugfs
Alex Frid [Wed, 14 Aug 2013 07:07:06 +0000]
ARM: tegra: dvfs: Add dvfs tables to debugfs

Change-Id: I71a1315744c7901e3f6f082debe2e07d7040cd08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/261716
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: hdmi: T148 Prod settings
Tom Cherry [Thu, 18 Jul 2013 01:05:27 +0000]
video: tegra: hdmi: T148 Prod settings

Bug 1250270
Bug 1316334

Change-Id: I3187dd7c890e8aacd1e17a9bb85c4ba871d4aa43
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/250461
(cherry picked from commit adae313395baf9047629162b0380b07abf9c8490)
Reviewed-on: http://git-master/r/261660
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: power: Keep interrupts ON for LP CPU delay
Alex Frid [Tue, 13 Aug 2013 07:14:20 +0000]
ARM: tegra: power: Keep interrupts ON for LP CPU delay

- Moved LP CPU minimum residency delay out of the interrupt-disabled
section of the cluster switch to reduce interrupt disabled time.

- Time stamped start of LP CPU residency, and rail statistic after the
cluster switch is completed, still within interrupt disabled section
to make sure LP residency restriction is applied on top of cluster
transition latency.

Change-Id: I55f769af197bbd757966bafe37a10a6e43b7bf2e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/261328
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: take out t11x references
Ray Poudrier [Mon, 12 Aug 2013 20:53:57 +0000]
ARM: tegra: loki: take out t11x references

Change-Id: I3386f2bbf6d752339fcc4943c9691fc03ea30d3a
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/261292
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: clean up audio initialization
Ray Poudrier [Mon, 12 Aug 2013 19:16:05 +0000]
ARM: tegra: loki: clean up audio initialization

Remove 5645 codec

Change-Id: I88a5d419a809e3c826170ee7a0ad5a69be161325
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/261291
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoarm: tegra12: loki: fix bruce modem pinmux
Vinayak Pane [Tue, 6 Aug 2013 02:50:50 +0000]
arm: tegra12: loki: fix bruce modem pinmux

Correcting the pinmux for modem signals.

Bug 1331728

Change-Id: I5cd29321aff9943f6a0c3bc23c7f09c6addb77ee
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/261290
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoARM: tegra: loki: Enable Invensense sensor
Ankit Pashiney [Sun, 4 Aug 2013 05:58:01 +0000]
ARM: tegra: loki: Enable Invensense sensor

bug 1342679

Change-Id: Ie549dd3b0ca6507b7fd6e3624416f35cc9ad76d5
Signed-off-by: Ankit Pashiney <apashiney@nvidia.com>
Reviewed-on: http://git-master/r/261289
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: config: tegra12: Enable JSA1127 ALS
Sri Krishna chowdary [Tue, 6 Aug 2013 14:00:35 +0000]
ARM: config: tegra12: Enable JSA1127 ALS

JSA1127 ALS sensor is used on Loki.
Hence enable CONFIG_SENSORS_JSA1127.

Bug 1327929

Change-Id: Idcc44bc172e1dcc30575aabb25c57f6734ff5698
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/261288
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: loki: Remove Cm32181 ALS
Sri Krishna chowdary [Tue, 6 Aug 2013 14:03:36 +0000]
ARM: tegra: loki: Remove Cm32181 ALS

Disable Cm32181 as Loki uses JSA1127 ALS
and not cm32181. Remove power tree entries.

Bug 1327929

Change-Id: I9521e2f985bf92e6d236b717dd4a5dc08d8789c7
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/261286
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: JSA1127: Add i2c registration
Sri Krishna chowdary [Tue, 6 Aug 2013 13:56:47 +0000]
ARM: tegra: JSA1127: Add i2c registration

Bug 1327929

Change-Id: I0145ec2d935fbf6fec506c44f42aaf67e1b64fc5
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/261285
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agostaging: iio: light: jsa1127: Add sensor driver
Sri Krishna chowdary [Tue, 30 Jul 2013 17:39:16 +0000]
staging: iio: light: jsa1127: Add sensor driver

Bug 1327929

Change-Id: I7e5468aca05bbc929c3926695a817f94d54bd7b9
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/261284
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: update codec configuration
Ray Poudrier [Sun, 4 Aug 2013 09:28:30 +0000]
ARM: tegra: loki: update codec configuration

Fix LDO_EN GPIO for audio codec

Bug 1343437

Change-Id: I4ef891a1a308f7f497518b429c0a6b06f62bc371
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/261283
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra12: loki: Fix wifi / bt.
Michael Hsu [Mon, 29 Jul 2013 19:43:04 +0000]
arm: tegra12: loki: Fix wifi / bt.

Loki board files were cloned from reference board, which had
different gpio assignments for wifi / bt.  Change gpio assignments
to actual signals used on loki board.

Add wifi power rail for wifi / bt.

Changes for gpio and sdmmc1 pins used by wifi / bt.

In addition to gpio toggling, also enable wifi power rails, when
turning wifi on.

Change-Id: I918261d5c0994a65b0c597b0440595d203a517a6
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: http://git-master/r/261282
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: corrected PMU board id
Mallikarjun Kasoju [Tue, 6 Aug 2013 01:10:59 +0000]
ARM: tegra: loki: corrected PMU board id

Change-Id: I11fdc6ddba96345561d2ed5fee8657a3bfb2e6f2
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/261281
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: set init panel mode flag
Ray Poudrier [Sun, 4 Aug 2013 10:21:44 +0000]
ARM: tegra: loki: set init panel mode flag

Will avoid glitch between bootloader to kernel

Change-Id: I2ecb61964093ad0322370ecd3d6805de55c711a9
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/261280
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: loki: Enable NCT72 config
Anshul Jain [Sat, 3 Aug 2013 07:11:34 +0000]
arm: tegra: loki: Enable NCT72 config

This change enables NCT72 config.

Change-Id: Ib3a45bd8445e30c8cf56f1f941a58d7008a81a1f
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/261279
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoboard-loki: change touch platform id
Jun Yan [Sat, 3 Aug 2013 06:39:59 +0000]
board-loki: change touch platform id

Change to the same id as it is in board-roth.c

Change-Id: Ib57d9d0fb14fee059d8cd134fab3af7585060e14
Signed-off-by: Jun Yan <juyan@nvidia.com>
Reviewed-on: http://git-master/r/261278
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: config: Enable BQ2419x
Anshul Jain [Sat, 3 Aug 2013 06:11:50 +0000]
arm: config: Enable BQ2419x

This change enables BQ24193 config.

Change-Id: I29b3534d7aa5215e1a9f2e1e916a321d2712754f
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/261277
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: roth: Config for BQ24193 charger
Anshul Jain [Sat, 3 Aug 2013 05:56:19 +0000]
arm: tegra: roth: Config for BQ24193 charger

This change adds board config for BQ24193

Change-Id: If95b40412f4ed95a683040d060522f024a80ce1b
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/261276
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: loki: Changes to boot into kernel
Ray Poudrier [Wed, 14 Aug 2013 18:05:20 +0000]
ARM: tegra: loki: Changes to boot into kernel

Change-Id: Ibfba185a6930629d11b58e60d53f373dd71eb93f
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/261275
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: loki: update power tree
siddardha naraharisetti [Sat, 27 Jul 2013 03:45:44 +0000]
arm: tegra: loki: update power tree

update power tree

Bug 1327962

Change-Id: Ia77858dc703153f223d628ca10f486d65d891cb8
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/261274
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: Enable BQ27441 Fuel gauge
Chaitanya Bandi [Tue, 6 Aug 2013 01:44:28 +0000]
ARM: tegra: Enable BQ27441 Fuel gauge

Bug 1321186

Change-Id: Id5fce45ce0f4a2d03c99dea9f091faab8de2a7f8
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/259784
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: loki: add initial board files
siddardha [Wed, 24 Jul 2013 17:39:21 +0000]
arm: tegra: loki: add initial board files

Added initial board files, power tree,
power mon changes for loki

Bug 1327962

Change-Id: I4c9e73b2560bd858fa623bbca640f7a5ea156f9f
Signed-off-by: siddardha <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/252996
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: configs: Enable TEGRA_GRHOST_VI on simulator
Alex Van Brunt [Thu, 15 Aug 2013 21:00:57 +0000]
ARM: configs: Enable TEGRA_GRHOST_VI on simulator

bonaire_sim needs TEGRA_GRHOST_VI just like the silicon builds.

Bug 1348023

Change-Id: I976334ab978cf688c42e0cd4551f3391b1f3d810
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/262065
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoARM: tegra: dvfs: Add debugfs node for GPU rail offset
Alex Frid [Wed, 14 Aug 2013 05:56:00 +0000]
ARM: tegra: dvfs: Add debugfs node for GPU rail offset

Change-Id: I83bbb4c24be150afc2ea2609ffe37732a5b5086b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/261351
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agomedia: video: tegra: PCL update
Charlie Huang [Wed, 17 Jul 2013 16:14:42 +0000]
media: video: tegra: PCL update

add edp client support.
add clock control.
add state report from sequence execution.

bug 1272149

Change-Id: Iafffce3294ddd92509521ec3b4335e93b5bb7e1a
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/250318
(cherry picked from commit 1adb9cd0fedce19be53db716a14a385e9d878ac4)
Reviewed-on: http://git-master/r/261169
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoARM: tegra12: clock: Add VI and ISP shared buses
Alex Frid [Sat, 10 Aug 2013 01:24:09 +0000]
ARM: tegra12: clock: Add VI and ISP shared buses

Created VI and ISP shared buses that connects scalable PLLC4 and
parking fixed rate PLLP to 4 shared users exposed to the nvhost VI/ISP
channels:

- via.vi.c4bus and ispa.isp.c4bus for channel A
- vib.vi.c4bus and ispb.isp.c4bus for channel B

Bus topology:

{pllc4*, pllp*} ---> c4bus
c4bus           ---> { vi.c4bus(vi*), isp.c4bus(isp*) }
vi.c4bus        ---> { via.vi.c4bus, vib.vi.c4bus }
isp.c4bus       ---> { ispa.isp.c4bus(ispa*), ispb.isp.c4bus(ispb*) }

(*) - physical clocks, all other - virtual
vvv(ppp*) - virtual shared bus user vvv with physical clock client ppp.

Bug 1328903

Change-Id: I2c347c7cd1f5cb219b5bdf76fb6749cd5d3a790b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/260248
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra12: dvfs: Update VI/ISP/TSEC dvfs tables, limits
Alex Frid [Fri, 9 Aug 2013 22:41:50 +0000]
ARM: tegra12: dvfs: Update VI/ISP/TSEC dvfs tables, limits

- Added ISP dvfs table (identical to VI)
- Increased VI maximum clock rate to 600MHz (identical to ISP)
- Changed VI/ISP/TSEC dvfs tables layout for readability

Change-Id: I75bc821e51a9fda835bd722d256b8ecc2a12aaad
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/260247
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra12: clock: Initialize duplicate clocks last
Alex Frid [Sat, 10 Aug 2013 02:51:35 +0000]
ARM: tegra12: clock: Initialize duplicate clocks last

Moved duplicate clock initialization after all original clock are done.

Change-Id: I4377de3b4a89c788fdf2182bfc5ddd3aecd4b007
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/260246
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: clock: Add common ISP mux and divider
Kaz Fukuoka [Fri, 9 Aug 2013 23:11:45 +0000]
ARM: tegra: clock: Add common ISP mux and divider

ISP mux and divider are shared among ISP and ISPB.
So it should be separated from ISP switch and ISPB switch.

Change-Id: Ibd8b5095b94c079534b0e45ab83f5ec82b0782c7
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/260172
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra12: Laguna: Unregister cl_dvfs for Laguna
Krishna Sitaraman [Thu, 8 Aug 2013 21:47:53 +0000]
ARM: Tegra12: Laguna: Unregister cl_dvfs for Laguna

Until correct cl_dvfs settings are programmed for laguna boards
cl_dvfs shoudl not be enabled

Change-Id: Iffa9bd98277bc32beca177705eb9ad29da4a06fd
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/259776
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra12: Clocks: Switch cpu to use DFLL
Krishna Sitaraman [Thu, 8 Aug 2013 21:43:49 +0000]
ARM: Tegra12: Clocks:  Switch cpu to use DFLL

Switch cpu to use DFLL instead of PLLX.

Change-Id: Ibf2832a6c3cdf390a5016bb64a19a3a71c46f36f
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/259773
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra12: Clocks: Enable CPU dvfs
Krishna Sitaraman [Thu, 8 Aug 2013 21:40:02 +0000]
ARM: Tegra12: Clocks:  Enable CPU dvfs

Enable cpu voltage scaling but keep core dvfs disabled.

Change-Id: Ia16f341723b2a71f466aea645b12fd84a45f017c
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/259771
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: Tegra12: Clocks: Update ardbeg board config file for cldvfs
Krishna Sitaraman [Thu, 8 Aug 2013 21:34:27 +0000]
ARM: Tegra12: Clocks: Update ardbeg board config file for cldvfs

Update the ardbeg board config file for cl-dvfs settings
needed for AMS (I2c) PMIC.

Change-Id: I8f4b5476b5752a1eccd9052cbf3d0868b17463b2
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/259769
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: Tegra12: Clocks: Add new parameters for CL-DVFS
Krishna Sitaraman [Thu, 8 Aug 2013 21:18:38 +0000]
ARM: Tegra12: Clocks:  Add new parameters for CL-DVFS

Update cl-dvfs parameters and cpu_process_id calculation.

Change-Id: If6628d70630b7d0892611f9e4c32adf2e90e12fa
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/259767
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: add GPU freq table for thermal throttling
Hyungwoo Yang [Thu, 8 Aug 2013 02:30:38 +0000]
arm: tegra: add GPU freq table for thermal throttling

Bug 1315460

Change-Id: I3407785a0328d35e2bfce9f3299943b18d982035
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/259418
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: gk20a: disable GPCPLL on gk20a off
Prashant Malani [Wed, 31 Jul 2013 00:26:25 +0000]
video: tegra: gk20a: disable GPCPLL on gk20a off

When gk20a is not being used, GPCPLL should be
switched off.

Bug 1332432

Change-Id: I727a7b0461dcd86fd36a5888cbe8a43eaaba98be
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/255824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agosound: soc: codecs: detect platform at runtime
Chetan Kumar N G [Mon, 1 Jul 2013 22:14:25 +0000]
sound: soc: codecs: detect platform at runtime

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I9435c1da78083ea1e1266c7a3ca2c4baafbdb050
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252567
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agousb: tegra: detect silicon platform at runtime
Chetan Kumar N G [Thu, 27 Jun 2013 17:54:40 +0000]
usb: tegra: detect silicon platform at runtime

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: If30e7571ec8138b3e2518207bf81a0d629d3112b
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252561
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: tegra: enable split mem config at runtime
Chetan Kumar N G [Thu, 20 Jun 2013 17:32:21 +0000]
ARM: tegra: enable split mem config at runtime

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I5dac33e6a3c8d2609fb57580658f05a2612e46df
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252560
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: detect platform at runtime.
Chetan Kumar N G [Mon, 17 Jun 2013 21:03:32 +0000]
ARM: tegra: detect platform at runtime.

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ide06d8c77409b6f57d13b0a2055736092096ea7c
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252559
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoARM: tegra: Disable dvfs on pre-si at runtime
Chetan Kumar N G [Fri, 7 Jun 2013 18:04:12 +0000]
ARM: tegra: Disable dvfs on pre-si at runtime

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: Ic8e5f14004dc4d4f6141889dff28afba035e55a6
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/252556
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: TLB_ACTIVE_LINES 0x20 for T124
Hiroshi Doyu [Fri, 5 Jul 2013 08:22:03 +0000]
iommu/tegra: smmu: TLB_ACTIVE_LINES 0x20 for T124

Set TLB_ACTIVE_LINES 0x20 for T124

Bug 1320358

Change-Id: I2f1abcd0677b6ff35056d79bf8c5c829223944b1
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260048
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: enable soc therm driver
Xue Dong [Thu, 8 Aug 2013 00:13:32 +0000]
arm: tegra: enable soc therm driver

bug 1342361

Change-Id: I1f22b2156cc888f06dacda274bdc002cedf99640
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/256642
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: Fix {TLB,PTC} reset value per SoC
Hiroshi Doyu [Mon, 1 Jul 2013 06:06:58 +0000]
iommu/tegra: smmu: Fix {TLB,PTC} reset value per SoC

TLB_RR_ARB and PTC_REQ_LIMIT is only valid for T124.

Bug 1320358
Bug 1315906

Change-Id: I1d57ac1fb525629966987483b6c8c871c4ed2d4e
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260878
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: Wrap the isomgr related codes with ifdef
Mark Zhang [Wed, 14 Aug 2013 10:05:25 +0000]
video: tegra: Wrap the isomgr related codes with ifdef

Add some missing "ifdef"s, this makes it build-able when some
system doesn't use isomgr.

Change-Id: I14c18e9928a37b92a3c27ae6efec65b797d166ce
Signed-off-by: Mark Zhang <markz@nvidia.com>
Reviewed-on: http://git-master/r/261482
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: fix the non-SMP build break
Bo Yan [Wed, 14 Aug 2013 00:48:32 +0000]
ARM: tegra: fix the non-SMP build break

For uni-processor build, simply use 0 as safe_state_index. This
gets around the undefined variable problem in uni-processor build
because CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not defined.

Currently, the SMP build also assigns 0 to safe_state_index and
does not change it afterwards.

Change-Id: Ib43870ba5dce761d55ed6a486ccb8777de3a0229
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/261255
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>

5 years agoiommu/tegra: smmu: Fix map linear at attach
Alex Van Brunt [Tue, 13 Aug 2013 18:04:24 +0000]
iommu/tegra: smmu: Fix map linear at attach

Fix map linear in the LPAE case where dma addresses are 64 bits
long. So, the printk's need to cast to u64 in all cases.

Bug 1297607

Change-Id: Ibf80d40139152bbdd080df6953e8ad2394f49a35
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/261102
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: host: gk20a comptag fix
Ken Adams [Tue, 13 Aug 2013 14:03:57 +0000]
video: tegra: host: gk20a comptag fix

Fix ctag off/overlap-by-one issue introduced with
6dac9ba.

bug 1331831
bug 1347412

Change-Id: Icbf5df0fe8324969cf22a4b5e829a8e49a32597b
Signed-off-by: Ken Adams <kadams@nvidia.com>
Reviewed-on: http://git-master/r/261063
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: ardbeg: Enable one-shot sharp 25x16
Animesh Kishore [Tue, 13 Aug 2013 12:42:09 +0000]
arm: tegra: ardbeg: Enable one-shot sharp 25x16

Bug 1347805

Change-Id: Iaac7464cc6cd5469893914542ffa57f3e07a0adb
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/261060
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dsi: Fix ganged mode packet sequence
Animesh Kishore [Tue, 13 Aug 2013 12:39:45 +0000]
video: tegra: dsi: Fix ganged mode packet sequence

Config lp transition after each line of dcs video.

Bug 1347805

Change-Id: If29f35b3afc0bd9099c5edd30c1701f5d616a962
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/261059
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: dsi: Fix OS idle suspend/resume
Animesh Kishore [Fri, 2 Aug 2013 13:37:06 +0000]
video: tegra: dsi: Fix OS idle suspend/resume

- Acquire all required locks atomically.
- Fix lock sequence

Bug 1334200

Change-Id: I286bb31207ba0ff5f60734f8e69e680d65166606
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/261058
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: host: Handle GPU class error
Terje Bergstrom [Tue, 13 Aug 2013 06:23:19 +0000]
video: tegra: host: Handle GPU class error

Handle GPU class error interrupt. For now, use the same method as for
illegal class.

Also returns an error to user space if a timed out context tries to
submit a new pushbuffer.

Change-Id: I6f4c1db45f5d57745f72083dacb5c2ff2f259b54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/260888
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: host: Fix vic03 resume code
Prashant Malani [Tue, 23 Jul 2013 02:48:42 +0000]
video: tegra: host: Fix vic03 resume code

There is no call to vic03_boot() during resume to
re-initialize VIC firmware when nvhost
powergating is disabled.

This change adds a call to vic03_boot() during
vic03 resume.

Bug 1346337

Change-Id: I251b675ac0bd2386afa7e9a7a0a420b2c08346ca
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/260074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agoarm: tegra: add program on updating
Chun Xu [Tue, 6 Aug 2013 08:24:48 +0000]
arm: tegra: add program on updating

Store_add_ports function in tegra wakeup monitor can add new pro-
gram to improve accuracy of nSaver apk wow statistics.

Bug 1230562

Change-Id: I522b77466128c94610859f061dce08444eab2d9a
Signed-off-by: Chun Xu <chunx@nvidia.com>
Reviewed-on: http://git-master/r/258629
(cherry picked from commit 8626206844aa3cf7f90e83c6c11e87520dccb84e)
Reviewed-on: http://git-master/r/260035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: replace uid with cmdline and add IPV6
chunx [Thu, 18 Jul 2013 09:25:49 +0000]
arm: tegra: replace uid with cmdline and add IPV6

Use process cmdline to identify a listened socket port in tegra_
wakeup_monitor.Add IPV6 support on network filter.

Bug 1185001

Change-Id: I73e69748adae901e0f7b4494a64a28406b35db28
Signed-off-by: Chun Xu <chunx@nvidia.com>
Reviewed-on: http://git-master/r/253455
(cherry picked from commit 61129a28e27bd4c5f794aa9af6903fd8ba68c746)
Reviewed-on: http://git-master/r/260034
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agonet: fix preempt_count non-zero schedule
Chun Xu [Mon, 5 Aug 2013 08:55:17 +0000]
net: fix preempt_count non-zero schedule

Resolve "BUG: scheduling while atomic" issue when
sk_get_waiting_task is being called.

Bug 1342554

Change-Id: I1673d56751a8a95b988b325b3857c8a5fe4c78ce
Signed-off-by: Chun Xu <chunx@nvidia.com>
Reviewed-on: http://git-master/r/258545
(cherry picked from commit 4516e7c330bb4c5da5020df0d2cc1cb5e9274d9f)
Reviewed-on: http://git-master/r/260033
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agonet: show cmdline in /proc/net/{tcp udp tcp6 udp6}
chunx [Fri, 5 Jul 2013 03:42:05 +0000]
net: show cmdline in /proc/net/{tcp udp tcp6 udp6}

Get process's cmdline from a sock's corresponding inode pointer,
 so that cmdline can't be used by Android active-standby app
to find the corresponding package name.

Bug 1185001

Change-Id: Idc8651e4bb85b8a152dfade9689a719f7d72687d
Signed-off-by: Chun Xu <chunx@nvidia.com>
Reviewed-on: http://git-master/r/253458
(cherry picked from commit 5dcfe4f561bd8d1767e0938dfd7565b2b7718478)
Reviewed-on: http://git-master/r/260013
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: {read,write}-only mapping
Hiroshi Doyu [Thu, 20 Jun 2013 04:45:50 +0000]
iommu/tegra: smmu: {read,write}-only mapping

Support {read,write}-only mapping via struct dma_attrs.

Bug 1309863

Change-Id: Ie20c768f821b93122274cc700634409ff0162688
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260010
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: dma-mapping: Pass DMA attrs as IOMMU prot
Hiroshi Doyu [Thu, 20 Jun 2013 04:44:36 +0000]
ARM: dma-mapping: Pass DMA attrs as IOMMU prot

Pass DMA attribute as IOMMU property, which can be proccessed in the
backend implementation of IOMMU. For example, DMA_ATTR_READ_ONLY can
be translated into each IOMMU H/W implementaion.

Bug 1309863

Change-Id: I0921ec35a4e056ea45a79acbea3e3b58a5a13a66
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260009
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agocommon: DMA-mapping: Add {read,write}-only attr
Hiroshi Doyu [Thu, 20 Jun 2013 04:42:30 +0000]
common: DMA-mapping: Add {read,write}-only attr

Adds DMA_ATTR_{READ,WRITE}_ONLY attribute to the DMA-mapping
subsystem. This sets mapping attribute read-only or write-only to be
set by each IOMMU H/W.

Bug 1309863

Change-Id: Ie3203014d83a519653d292c243e863244daa9675
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/260008
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: dsi: Enable MIPI auto calibration
Vineel Kumar Reddy Kovvuri [Thu, 8 Aug 2013 09:26:24 +0000]
video: tegra: dsi: Enable MIPI auto calibration

Implementation of DSI MIPI auto calibration

Bug 1319070

Change-Id: If8956107752a3852b29f1f8669b8c7baed7a2382
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/259576
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoarm: tegra: hard code calib_base values
Xue Dong [Thu, 1 Aug 2013 23:58:33 +0000]
arm: tegra: hard code calib_base values

bug 1342361

Change-Id: Ibae05540ebb8abeab8e880172fd112a620aae0e7
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/257179
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: fuse spare_realignment_reg change
Xue Dong [Thu, 1 Aug 2013 21:33:10 +0000]
arm: tegra: fuse spare_realignment_reg change

spare_realignment_reg fuse along with fuse from tsensor8_calib
are used to obtain the required 32 bit value.

bug 1309557

Change-Id: I0eb4c7941feb47a70555c80315314920097d406a
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/257006
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: config: tegra: Enable EHCI Boost CPU Freq
Jeetesh Burman [Wed, 31 Jul 2013 14:59:18 +0000]
ARM: config: tegra: Enable EHCI Boost CPU Freq

Enable CONFIG_TEGRA_EHCI_BOOST_CPU_FREQ=800 in tegra11_defconfig
to boost the cpu frequency so that usb host data transfer rates
improve and usb devices detection works properly.

Bug 1249335

Change-Id: If42323e9eb894841fdbede232b562809df31e7ee
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/256378
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: enable Ardbeg USB2 UHSIC PHY wakeup
Mark Kuo [Thu, 1 Aug 2013 08:52:32 +0000]
ARM: tegra: enable Ardbeg USB2 UHSIC PHY wakeup

Icera Bruce modem is using tegra_ehci2_device on t124 Ardbeg with HSIC
phy, so enable USB2 UHSIC PHY wakeup source so that remote wakeup can
work in LP0.

Also add a generic function tegra_set_wake_source() in wakeups-t12x.c,
which can be used to modify tegra_wake_event_irq table from board files.

Bug 1333745

Change-Id: Ia58998fc71c0575d87fc65b00a7bd6e7cd49a3f7
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://git-master/r/254199
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoOV5640: move to right place and update power_on()
Bryan Wu [Thu, 9 May 2013 00:33:59 +0000]
OV5640: move to right place and update power_on()

Add .s_power() function and power on sensor before chip probing

Change-Id: Iba342333e0c84db601c8ab455f94c6f3afe7f23a
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246273
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoOV5650: move to right place and update power_on()
Bryan Wu [Thu, 9 May 2013 00:31:29 +0000]
OV5650: move to right place and update power_on()

Power on sensor for chip probing and update .s_power()

Change-Id: Iff875f1a84bc956cb10f43a2659d0b50a71cad0a
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246272
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agomedia: tegra: move V4L2 soc_camera driver to the right place
Bryan Wu [Fri, 28 Jun 2013 22:46:35 +0000]
media: tegra: move V4L2 soc_camera driver to the right place

Also update DeviceTree entries and some API changes

Change-Id: I3588b706f2b91e379ba6008f737ba2d21e4ec7a8
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246271
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agomedia: videobuf2: move NVMAP driver to the right place
Bryan Wu [Fri, 28 Jun 2013 22:32:54 +0000]
media: videobuf2: move NVMAP driver to the right place

Also update nvmap_pin() API

Change-Id: Ia5c2478d06d7a13a02a3c65764696c8c66691231
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246270
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agomedia: tegra_v4l2: add dual camera support
Bryan Wu [Mon, 24 Jun 2013 21:32:10 +0000]
media: tegra_v4l2: add dual camera support

Add support for dual cameras from both CSI-A and CSI-B:
 - move all the CSI settings into video buffer struct
 - queue the video buffer struct to a dedicated queue
 - process one video buffer struct from the queue at one time

Change-Id: Ibd4f56c66c479ee862c95807a7e2e57e8f8e0b34
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246269
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoARM: defconfig: build nvhost VI and V4L2 drivers as modules only for tegra3_defconfig
Bryan Wu [Thu, 28 Feb 2013 01:28:17 +0000]
ARM: defconfig: build nvhost VI and V4L2 drivers as modules only for tegra3_defconfig

Build nvhost VI driver and related to modules as well as
soc_camera and tegra_v4l2_camera drivers. This change will make one
tegra3_defconfig support both nvhost VI driver and tegra_v4l2_camera
driver.

Still select to built-in nvhost VI driver into kernel for other
defconfigs.

Bug 1240806

Change-Id: Ifcc593664dc38a98534abfc0f508df8edc027abc
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246268
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agomedia: tegra_v4l2: pass platform_data via soc_camera_link
Bryan Wu [Mon, 3 Jun 2013 21:40:25 +0000]
media: tegra_v4l2: pass platform_data via soc_camera_link

soc_camera_link supports passing power on/off control callback to
soc_camera stack. So the power control can be handled by soc_camera
stack instead of our Tegra V4L2 host driver.

Also pass other platform_data fields via soc_camera_link instead of
a hacking nvhost_device_data struct.

Bug 1240806

Change-Id: I625c17680603ecd930f934bc37362a66705d90e5
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246267
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agovideo: tegra: host: make host1x client VI driver can be a module
Bryan Wu [Thu, 28 Feb 2013 18:00:57 +0000]
video: tegra: host: make host1x client VI driver can be a module

VI driver will use the same register, i2c and host1x resources
which is shared by tegra-camera V4L2 driver. So make it can be
a module.

Bug 1240806

Change-Id: I8949b9abc3a4f0719e6daaa9aeecdd9c57154e2c
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/246265
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoi2c: tegra: Implement the bit banging method for i2c transfer after shutdown
Laxman Dewangan [Tue, 13 Aug 2013 10:18:28 +0000]
i2c: tegra: Implement the bit banging method for i2c transfer after shutdown

Implement bit banging method of doing i2c transfer after shutdown call back
get called. For bit banging method, driver will use bit algo for i2c transfer.

Make this as optional and can be selected through platform data.

bug 1213113

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/260041
(cherry picked from commit 74e591524d6dbff96d133a254e363ecee90094c9)

Change-Id: Id68c53f9685ea93e2e16d5523619cf9254ef4dac
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/261007
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: call pm_power_reset() if it is implemented and no reset command
Laxman Dewangan [Tue, 13 Aug 2013 10:17:30 +0000]
ARM: tegra: call pm_power_reset() if it is implemented and no reset command

If there is no reset command issued and if system specific reset is
implemented then call the specific reset APIs for resetting the
system.

The system specific reset is implemented through pm_power_reset().

bug  1213113

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/260040
(cherry picked from commit 1bacac7cd3204369bd62842a676ffd9cfe73dab2)

Change-Id: I170616b2f681d6f6c9cf98d03e8817f8b1dcb46a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/261006
GVS: Gerrit_Virtual_Submit

5 years agomfd: max77660: implement system reset through PMIC
Laxman Dewangan [Fri, 9 Aug 2013 11:25:10 +0000]
mfd: max77660: implement system reset through PMIC

Implement pm_power_reset() to reset system through PMIC.
This is done by writing the COLDRST bit to 1.

bug  1213113

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/260039
(cherry picked from commit cfa67260cc5f9caeeec6949b96793aaf3dccd772)

Change-Id: I994a1a4273be7cd576ee062896c863d070d1fcc3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/261005
GVS: Gerrit_Virtual_Submit

5 years agoARM: kernel: add pm_power_reset to implement system specific reset
Laxman Dewangan [Tue, 13 Aug 2013 10:15:11 +0000]
ARM: kernel: add pm_power_reset to implement system specific reset

To implement the platform/PMIC specific power reset functionality,
add the pm_power_reset() definition.

The PMIC or any driver will implement this API for platform reset
and get called when actually system reset is required.

bug  1213113

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/260038
(cherry picked from commit 129b94affc0c4c0cc796458f119d965521b19715)

Change-Id: Ia73ed93c739fa9e54fbbb2a7cd364bedda3df2e1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/261004
GVS: Gerrit_Virtual_Submit