5 years agogpu: nvgpu: Add GM20b RAM SVOP PDP fuse registers
Alex Frid [Tue, 16 Sep 2014 23:00:10 +0000]
gpu: nvgpu: Add GM20b RAM SVOP PDP fuse registers

Bug 1550997

Change-Id: I25551fdcb9f7d43dc8631305b784aa9c04040139
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/499553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agousb: gadget: xudc: UASP handling parallel cmds
venkat Tammineedi [Tue, 7 Oct 2014 07:05:16 +0000]
usb: gadget: xudc: UASP handling parallel cmds

The current UASP driver processes the command, data, and
status stages of each command serially. Made changes to
handle multiple commands in parallel. Also made changes
for UASP to accept any valid command tag value(1457592)
The changes for both the Bugs are interdependent. So
submitting one change for both the Bugs 1457592,1414327.

Bug 1414327
Bug 1457592

Change-Id: I6b506fc1fb27bbdf67bca0f7644466e540140c4e
Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Reviewed-on: http://git-master/r/554098
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hui Fu <hfu@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agousb: gadget: xudc: Support UASP + Android
venkat Tammineedi [Tue, 7 Oct 2014 06:54:28 +0000]
usb: gadget: xudc: Support UASP + Android

Currently the USB gadget protocol UASP is part
of the composite framework and is standalone.
Making changes to include it as part of Android
framework which also controls other protocols like
MTP, ADB, BOT etc for communicating with the Host
over USB.

Bug 1525578

Change-Id: Ie91e2e2c24bea5d2b04b9614260d67ddb9693998
Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Reviewed-on: http://git-master/r/554095
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hui Fu <hfu@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>

5 years agousb: gadget: xudc: defconfig change to enable UASP
venkat Tammineedi [Tue, 7 Oct 2014 06:47:19 +0000]
usb: gadget: xudc: defconfig change to enable UASP

The USB's UASP gadget protocol depends on the
Linux SCSI Target-LIO module which is disabled
in the current configuration. Made changes to
enable this that allows our device to communicate
with a USB Host using the UASP protocol.

Change-Id: I8d57fb5c04ccb86178d1e9d7a8e8961d4f7e92fb
Signed-off-by: Venkat Tammineedi <vtammineedi@nvidia.com>
Reviewed-on: http://git-master/r/554092
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hui Fu <hfu@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agoclock: tegra21: Invalidate EMC DVFS if no boot rate
Alex Frid [Wed, 8 Oct 2014 20:48:59 +0000]
clock: tegra21: Invalidate EMC DVFS if no boot rate

Invalidated EMC DVFS table if it does not include boot rate entry.

Bug 1562590

Change-Id: Idad321c3627d979cc20dffe7128a3cf25b7fce8b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/554769
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoRevert "drivers: tegra: mmc: Support for setting dynamic pad strengths"
Alex Frid [Wed, 8 Oct 2014 00:09:45 +0000]
Revert "drivers: tegra: mmc: Support for setting dynamic pad strengths"

This reverts commit 0a188b23faecd0e39b17a4b6d43088390f5d65f7 since
it causes the following crash while boot-up:

[    7.332115] Unable to handle kernel NULL pointer dereference at virtual address 00000018
...
[    7.434107] PC is at pinctrl_select_state+0x50/0x1a0
[    7.439067] LR is at sdhci_tegra_init_pinctrl_info+0x1f8/0x288

Change-Id: Idfa78bd98df340a965dd913c3977ff83e4fcab10
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/554474
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoconfig: delete old MODS defconfigs
Chris Dragan [Mon, 6 Oct 2014 12:38:01 +0000]
config: delete old MODS defconfigs

Bug 1561851

Change-Id: Iba90c8d1c620ec49921888ee1024cb8b8dda1e18
Signed-off-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-on: http://git-master/r/553803
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stefan Becker <stefanb@nvidia.com>
Reviewed-by: Tope Yang <topey@nvidia.com>
Reviewed-by: Vivek Aseeja <vaseeja@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agogpu: nvgpu: Improve error handing in fifo
Terje Bergstrom [Fri, 3 Oct 2014 11:13:25 +0000]
gpu: nvgpu: Improve error handing in fifo

When initializing fifo, we ignore several error conditions. Add
checks for them.

Change-Id: Id67f3ea51e3d4444b61a3be19553a5541b1d1e3a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553269

5 years agoRevert "ARM64: configs: Enable GPU scaling on T210"
Mitch Luban [Tue, 7 Oct 2014 18:44:55 +0000]
Revert "ARM64: configs: Enable GPU scaling on T210"

This reverts commit 60e13a9ad1fe180849b8964fdc8fc42b25f55917.

Change-Id: I072cf3f1747c66974b59d3ff8c98f09571b49f8e
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/554298

5 years agoarm64: rename tegra210 common dtsi
Mitch Luban [Tue, 7 Oct 2014 18:58:27 +0000]
arm64: rename tegra210 common dtsi

tegra210-ers-common.dtsi was a common dtsi for t210. Renaming
to make clear that it's not just common for ERS.

Change-Id: I04bc3fd8d2b37535715c50290bee30487d290831
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/554310

5 years agoARM64: tegra21: Fix EMC DVFS voltage requirements
Alex Frid [Tue, 7 Oct 2014 21:36:52 +0000]
ARM64: tegra21: Fix EMC DVFS voltage requirements

Bug 1562590

Change-Id: I5883cc4e94212cbe3c434e42d498eebff23dba08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/554358
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoarm64: dts: tegra: move emc table to ers file
Ray Poudrier [Tue, 7 Oct 2014 18:09:25 +0000]
arm64: dts: tegra: move emc table to ers file

The common file is shared across more than just LP3 platforms.
Move the emc table to a board-specific file.

Change-Id: Ia5384123ff66fe678136aa18473b79be1f08fdfd
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/554276
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoarm: dts: panel specific nvidia,edid prop
Min-wuk Lee [Thu, 18 Sep 2014 06:02:48 +0000]
arm: dts: panel specific nvidia,edid prop

Move nvidia,edid property underneath panel node

Bug 1371533
Bug 1536393

Change-Id: I292e313d6e059c7fc53631ac20c462a144b0e5cc
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/500170
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: dc: panel specific nvidia,edid prop
Min-wuk Lee [Thu, 18 Sep 2014 05:39:37 +0000]
video: tegra: dc: panel specific nvidia,edid prop

nvidia,edid property needs to be prepared underneath
target panel node since this information is panel
specific.

Bug 1371533
Bug 1536393

Change-Id: I076f6c2aa467ce11091aec7d2fe961408b041ffe
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/500131
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM64: configs: Enable GPU scaling on T210
Arto Merilainen [Thu, 4 Sep 2014 05:39:28 +0000]
ARM64: configs: Enable GPU scaling on T210

This patch enables devfreq based GPU scaling on T210.

Change-Id: I9ba09f6d01f836d6d7f79fe3be4af90ededf15b6
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/500616
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agodvfs: tegra21: limit gpu rail voltage to 1150mv
Seshendra Gadagottu [Tue, 30 Sep 2014 21:51:50 +0000]
dvfs: tegra21: limit gpu rail voltage to 1150mv

When gpu dvfs enabled, system is running into EDP
issues with max gpu rail voltage as 1.225V. Until SV
tables available, max gpu rail voltage is limited to 1.15V.

Bug 1552464

Change-Id: I025257929cbd9e497edd44dbaa2132cf3e833905
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/552217
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoxhci: tegra21: WAR for incorrectly detected LFPS
JC Kuo [Thu, 2 Oct 2014 16:32:39 +0000]
xhci: tegra21: WAR for incorrectly detected LFPS

In the path of LGO_U3, there is some noise on the bus before actual
electrical idle, the idle detector circuit in the new UPHY design
seems to be sensitive to this noise and it is detected as LFPS.

Disabling LPFS detector before direct U3 as a workaround.

bug 1560603
bug 200041375
bug 200042008

Change-Id: I2b2149959cb38f29fbbb21dfb3dbdef2f8cb15f8
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/552933
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

5 years agodrivers: tegra: mmc: Support for setting dynamic pad strengths
Raveesh Kote [Mon, 22 Sep 2014 04:59:58 +0000]
drivers: tegra: mmc: Support for setting dynamic pad strengths

-Setting dynamic pad strengths depending on the
 type of sd card inserted.

- This requirement is for automotive platforms
  in which the pad strengths change depending
  on the type of sd card inserted.

Bug 1477749

Change-Id: Ied4670e591000a8a95ca0eaf746c18517c4b5d0a
Signed-off-by: Raveesh Kote <rkote@nvidia.com>
Reviewed-on: http://git-master/r/496939
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoplatform: tegra21: vi: emc clk_duplicate
Sudhir Vyas [Tue, 30 Sep 2014 07:12:28 +0000]
platform: tegra21: vi: emc clk_duplicate

Define emc clk_duplicate for VI_ONE_DEVICE.

Bug 1555925

Change-Id: Ia83ce15f7cbcc4ec891ae229fa29a0e709bc93b7
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/551948
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agovideo: tegra: host: enable actmon watermark intr
Shridhar Rasal [Sat, 5 Jul 2014 14:30:44 +0000]
video: tegra: host: enable actmon watermark intr

Add support to use watermark interrupts:

- Adds nvhost interrupt callback to actmon interrupts,
  if actmon_irq is set for device.
- Adds callbacks to set high and low watermark values.
- Removes unused counter code.

Bug 1515087

Change-Id: Ibff29a534c4580225a7a7b2e18af18dfe150565b
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/497377
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: host: allow registering isrs to host
Shridhar Rasal [Sat, 5 Jul 2014 14:30:44 +0000]
video: tegra: host: allow registering isrs to host

This patch adds support to register ISRs to host interrupts.

Bug 1515087

Change-Id: If8aecb6fb9942c3bb9033aaa5dae05cda591b79f
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553266

5 years agoPM / devfreq: add watermark events
Shridhar Rasal [Thu, 25 Sep 2014 13:15:13 +0000]
PM / devfreq: add watermark events

This patch adds support for watermark events. These events inform
the governor that the device load has gone below (low watermark) or
above (high watermark) certain load value.

Bug 200041268

Change-Id: I617369080fc42f623fe944d8ddea84543ce06bf5
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553265
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoPM / devfreq: add new watermark devfreq governor
Shridhar Rasal [Thu, 25 Sep 2014 13:15:13 +0000]
PM / devfreq: add new watermark devfreq governor

This patch adds new watermark devfreq governor.

Governor decides next frequency from frequency table
based on type of watermark interrupt.

Bug 200041268

Change-Id: Id6e6cd53476b7e72215ff9dc5cb6e06ae5b76575
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/538933

5 years agoRevert "iommu: of: tegra/smmu: asprops sanity check"
Arto Merilainen [Tue, 7 Oct 2014 13:02:50 +0000]
Revert "iommu: of: tegra/smmu: asprops sanity check"

This reverts commit 35a1fa354c7e8033eb36233b25176e97d2c3bd3f.
The commit causes large screen corruption on T210.

Change-Id: I598b0a0627626847708d6b7fae750495a32f20c3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/554215
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agodrivers: media: tegra: enable camera auto detect
Charlie Huang [Sun, 11 May 2014 06:12:33 +0000]
drivers: media: tegra: enable camera auto detect

updates:
1. register chips from DT at probing.
2. move power on/off sequences and regulators from chip data
   to device data, to avoid conflicts when multiple devices
   of the same chip type but have different power sequence
   and regulators.
3. split camera.h, the internal function prototypes are moved
   to camera_common.h.
4. debugfs now supports new layout format - version 0 and 1.
5. remove depricated commands, edp and pinmux.
6. enable auto detection in a seperate worker thread.
7. other minor optimizations.

bug 1509855

Change-Id: I2f619e12744a63e0c3c9b6088a9a12b0e0f25973
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/407924
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM64: dts: loki: Add DeviceTree entries for Sysedp
Anand Prasad [Thu, 18 Sep 2014 20:15:23 +0000]
ARM64: dts: loki: Add DeviceTree entries for Sysedp

Change-Id: Idc52f08f4ee5eea28576e61c8608ee5047cdfc54
Signed-off-by: Anand Prasad <anprasad@nvidia.com>
Reviewed-on: http://git-master/r/500414
Reviewed-by: Timo Alho <talho@nvidia.com>

5 years agodt-bindings: memory: do not use TEGRA_SWGROUP_GPU
Sri Krishna chowdary [Tue, 7 Oct 2014 05:49:03 +0000]
dt-bindings: memory: do not use TEGRA_SWGROUP_GPU

GPU swgroup is disabled at hardware level.
Add warning to prevent its usage for programming smmu.

Change-Id: I7f3c274fcb6a96ad9f4a9af612e794798ccb8a04
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/554087
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoiommu/tegra: smmu: Nullify stale pointer
Sri Krishna chowdary [Tue, 30 Sep 2014 15:19:26 +0000]
iommu/tegra: smmu: Nullify stale pointer

The map* in smmu_map_prop points to the dma_iommu_mapping
which was destroyed. It may be possible that a client which registers
to this swgroup will be using the stale pointer and not create one
new dma_iommu_mapping * if this pointer is not set NULL.
Fix it by setting it NULL just before domain is destroyed.

Bug 200031739

Change-Id: I05ac3456074d6bbfe11cbc766e47de257d0e0ae5
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/552080
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoasoc: codec: es755: change spi operation speed
Dara Ramesh [Tue, 7 Oct 2014 04:57:54 +0000]
asoc: codec: es755: change spi operation speed

change spi operation speed to 4 Mhz as audience
firmware verified with this frequency.

Change-Id: I5c05469e45c9ff86b4ed58463b34d1ee2984c2e6
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/554057
Reviewed-by: Chandrakanth Gorantla <cgorantla@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm64: mm: Modify __flush_dcache_op
Sri Krishna chowdary [Sun, 14 Sep 2014 14:05:24 +0000]
arm64: mm: Modify __flush_dcache_op

On Denver, complete cache flush takes about ~10 msec sometimes when
cisw instruction is used. However, breaking the operation into
cache_clean_all and cache_invalidate_all helped reduce the overhead
to < 1 msec. So, moving ahead with this useful optimization.

Bug 200035864

Change-Id: I0a64d1e3f7d622db4e88ea33f8bfd51b46a400e2
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/498652
(cherry picked from commit 1823577974bb1470f4fe44321105433c3c83ffa7)
Reviewed-on: http://git-master/r/501468
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agotegra: nvadsp:record stats for load init and start
Ajay Nandakumar [Tue, 30 Sep 2014 08:42:34 +0000]
tegra: nvadsp:record stats for load init and start

Adding a framework which profiles load init start. By default,
profiling stats is disabled and needs to be enabled using the
pre-processor RECORD_STATS.

Bug 200009727

Change-Id: I68dbe9a6aa3a038e750b9adf00dcc6920cb84d75
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/551913
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years agoplatform: nvadsp: Add support for global TSC
Ajay Nandakumar [Tue, 30 Sep 2014 08:47:55 +0000]
platform: nvadsp: Add support for global TSC

need a global timestamp counter(TSC) to synchronize across different
modules across the system(SOC).Add API to access global timestamp
counter(TSC).

Bug 200009727

Change-Id: I69a191bcbf71457558de5b05316c336c0d52cbaa
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/551975
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years agoplatform: nvadsp: remove un-needed print in load
Ajay Nandakumar [Tue, 30 Sep 2014 08:51:57 +0000]
platform: nvadsp: remove un-needed print in load

Removing print during second load which causes 6ms delay.

Bug 200009727

Change-Id: I795a919ab940134a89154461c15a087e76f046bb
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/551976
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years agotegra: nvadsp: Use table to choose frequency
Ajay Nandakumar [Mon, 29 Sep 2014 07:03:58 +0000]
tegra: nvadsp: Use table to choose frequency

Use a frequency table so that the adsp clk frequency is a multiple of
the lowest frequency. This is so that timer prescalar values set does
not result in errors.

Bug 200007507

Change-Id: I03e8dc055e74cada13221d76126d77e006f2aab5
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/542548
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Tested-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>

5 years agovideo: tegra: host: Add mm engine name bindings
Arto Merilainen [Mon, 6 Oct 2014 14:37:27 +0000]
video: tegra: host: Add mm engine name bindings

This patch adds bindings for nvdec and nvjpg. Currently we trust
that they are named correctly, however, device tree names may not
follow the current standard naming.

Change-Id: I4a8e3490b5c0fdb95d5cc437f2fe907d3538a209
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553839

5 years agovideo: tegra: host: mm: Add hooks for T186
Arto Merilainen [Mon, 6 Oct 2014 12:40:06 +0000]
video: tegra: host: mm: Add hooks for T186

This patch adds T186 hooks for nvdec, nvenc and nvjpg.

Change-Id: I7302d561448ed09cbd1452b67bbd62be7a676316
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553838
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agogpu: nvgpu: dump falcon stats in mmu fault handler
Konsta Holtta [Fri, 3 Oct 2014 07:45:23 +0000]
gpu: nvgpu: dump falcon stats in mmu fault handler

If engine status is in context switch in the fifo mmu fault handler,
dump falcon stats and gr stats for each engine.

Bug 1544766

Change-Id: Idfa9772b7e67072941144ac3bdd73e791fdc2b23
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/553205
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: vgpu: fix build break
Aingara Paramakuru [Tue, 7 Oct 2014 01:10:10 +0000]
gpu: nvgpu: vgpu: fix build break

Switch struct definitions to use nvgpu version instead of
nvhost one.

Bug 1509608

Change-Id: Id8c1b0c198536766f0399437bdf2c35c6a6bfe85
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/554027
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm64:dts:DTS for E2220 RCM & QSPI boot support.
Ambika Prasad [Mon, 6 Oct 2014 11:57:32 +0000]
arm64:dts:DTS for E2220 RCM & QSPI boot support.

Changes:
- QSPI clock & pin-mux related config changes.

Change-Id: I2329458d42fb7029887a409cbe77dcaf5055cd00
Signed-off-by: Ambika Prasad <ambikap@nvidia.com>
Signed-off-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-on: http://git-master/r/539963
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm64: foster: Add E01 foster dts support
David Dastous [Thu, 2 Oct 2014 19:01:33 +0000]
arm64: foster: Add E01 foster dts support

Separated out extcon OTG detection.

Bug 1557030

Change-Id: Ic2c7f24b3185afc3d87896b9f6f617f7bf37f201
Signed-off-by: David Dastous <ddastoussthi@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/552963

5 years agoarm64:t210: configs : embedded config changes
Ambika Prasad [Fri, 26 Sep 2014 10:09:28 +0000]
arm64:t210: configs : embedded config changes

Changes:
  - Enable USB Host and device enumeration
  - Enable SATA
  - Enable other changes related to t210 taken from
    L4T config

bug 200041031

Change-Id: If26b2204514942e35446c762e8b3853a3e86ff60
Signed-off-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-on: http://git-master/r/551981
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ambika Prasad <ambikap@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agovideo: tegra: host: vi/isp: set la for vi/isp
Charles Kong [Tue, 23 Sep 2014 01:30:01 +0000]
video: tegra: host: vi/isp: set la for vi/isp

When setting latency allowance of camera,
both ptsa and latency allowance should be set.

Bug 1544612

Change-Id: Ib3e0f792387e078071f4eee36f69f42da4854218
Signed-off-by: Charles Kong <charlesk@nvidia.com>
Reviewed-on: http://git-master/r/501431
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agodrivers: host: t210: increase number of vi channel
David Wang [Tue, 23 Sep 2014 00:59:04 +0000]
drivers: host: t210: increase number of vi channel

Increment the number of vi channels in host device data
definition to 6.

bug 1545729

Change-Id: I8d1b91be5f678c8067ddc600d6919bbb852b97a5
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/533988
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agomisc: mods: Implements new IOCTLs
tope yang [Thu, 18 Sep 2014 23:20:06 +0000]
misc: mods: Implements new IOCTLs

This patch implements new IOCTLs for access ADSP API

Change-Id: Id85d8685c423a486a8b0c8d325a296707d2e531d
Signed-off-by: tope yang <topey@nvidia.com>
Reviewed-on: http://git-master/r/500471
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agommc: tegra: support to disable auto calibration
Seshagir.H [Wed, 1 Oct 2014 06:20:04 +0000]
mmc: tegra: support to disable auto calibration

Provide support to parse disable-auto-cal dt flag to disable
auto calibration.

bug 200035711

Change-Id: Ieb2e0405266154825269966e2eacf0e701159cc4
Signed-off-by: Seshagiri.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/552430
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: vcm30t124: disable auto cal for SDMMC2B
Seshagir.H [Wed, 1 Oct 2014 06:08:33 +0000]
arm: vcm30t124: disable auto cal for SDMMC2B

The max freq that SDMMC2B supports is 80Mhz. Due to this freq limit,
auto calibration is not required for SDMMC2B.

This change enables "disable-auto-cal" dt flag for SDMMC2.

bug 200035711

Change-Id: Ic35d0e1198593a71c660626e905b47fc6b68a35d
Signed-off-by: Seshagiri.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/552429
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agommc: tegra: support to parse auto-cal-step
Seshagir.H [Wed, 1 Oct 2014 04:57:26 +0000]
mmc: tegra: support to parse auto-cal-step

AUTO_CAL_STEP[18:16] has bit position in
SDMMC_AUTO_CAL_CONFIG_0. This value indicates
calibration step interval for automotive platforms.

bug 200035711

Change-Id: I59efd890f5b2e67dbc9ef27a94916d0ed5997fee
Signed-off-by: Seshagiri.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/552428
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: tegra: vcm30t124: update dt properties for SDMMC
Seshagir.H [Wed, 1 Oct 2014 04:55:08 +0000]
arm: tegra: vcm30t124: update dt properties for SDMMC

Update dt properties of calib-1v8-offsets, calib-1v8-offsets
and auto-cal-step as per golden register configurations for SDMMC1, SDMMC3
and SDMMC4 controllers.

bug 200035711

Change-Id: I4c49503bee211a4d8fd0a49106554f31dc9a59ab
Signed-off-by: Seshagiri.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/552427
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Tested-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoarm: tegra: vcm30t124: Modify machine name to p1859
Vipin Kumar [Tue, 9 Sep 2014 11:57:21 +0000]
arm: tegra: vcm30t124: Modify machine name to p1859

Modify the machine name to p1859 and remove vcm30t124 machine from
sources

bug 1527003

Change-Id: I28c4d7ba5e4153c450f42bba5e5dea0ebce6c5b2
Signed-off-by: Vipin Kumar <vipink@nvidia.com>
Reviewed-on: http://git-master/r/496873
GVS: Gerrit_Virtual_Submit
Reviewed-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agoiommu: of: tegra/smmu: asprops sanity check
Hiroshi Doyu [Mon, 6 Oct 2014 23:28:20 +0000]
iommu: of: tegra/smmu: asprops sanity check

swgroups should be compatible with asprops. IOW swgroup ID bitmap is a
part of or is equal to asprops's swgid_mask.

Change-Id: I2c39b944624d9f67b4d5679d3e6fb89378a1b681
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/553987
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: dts: Remove TEGRA_SWGROUP_GPU
Hiroshi Doyu [Mon, 6 Oct 2014 23:05:51 +0000]
arm: dts: Remove TEGRA_SWGROUP_GPU

MC_SMMU_GPU_ASID_0 indicates bypassing SMMU so that this isn't used at
all for IOMMU path.

Change-Id: Ie57851aafb82c3ec8e6cf7b3b8c9946e9af0cd4a
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/553986
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm64: t210: dts: add se* in PPCS domain
Hiroshi Doyu [Mon, 29 Sep 2014 08:35:50 +0000]
arm64: t210: dts: add se* in PPCS domain

Add se* in PPCS domain, based on the current t210 fixup table.

Change-Id: Id85e552e212117235dafd94ff39ff63fae0481b1
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/542578
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agodt-bindings: memory: swgroup supports 5 cells macro
Hiroshi Doyu [Mon, 29 Sep 2014 08:35:21 +0000]
dt-bindings: memory: swgroup supports 5 cells macro

Add TEGRA_SWGROUP_CELLS5.

Change-Id: I49d5c7d6e4ce228672bd9f11971bc3f3f83e9e7f
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/542575
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm64: t210: dts: fix ppcs domain
Hiroshi Doyu [Mon, 29 Sep 2014 06:26:06 +0000]
arm64: t210: dts: fix ppcs domain

PPCS domain should include PPCS2 too.

Change-Id: Ifb46a46e9fd01cb8a876754dfa9e1a2a2e0f9ac3
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/542550
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm64: t132: dts: fix ppcs domain
Hiroshi Doyu [Mon, 29 Sep 2014 06:25:10 +0000]
arm64: t132: dts: fix ppcs domain

PPCS domain should include PPCS2 too.

Change-Id: Icc87df8e766b0b0430a2a50f0adec810ee3a9204
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/542549
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoASoC: codecs: max98090: free_irq during module remove
Shreshtha SAHU [Wed, 24 Sep 2014 15:33:35 +0000]
ASoC: codecs: max98090: free_irq during module remove

Bug 1550880

Change-Id: I54697780893c17a1c117483fd9bf271ba31209d4
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/538459
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoASoC: tegra: max98090: fix error return paths
Shreshtha SAHU [Wed, 24 Sep 2014 15:21:29 +0000]
ASoC: tegra: max98090: fix error return paths

- Remove switch_dev_unregister and call tegra_asoc_switch_unregister
instead in error return path corresponding to tegra_asoc_switch_register.

- Skip max97236 registration for laguna erss platorm.

Issues surfaced out on making max98090 as removable KO module.

Bug 1550880

Change-Id: I6a6c0185a3980efab3592f0733bda214aac4fc81
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/538458
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra12_defconfig: max98090 as loadable module
Shreshtha SAHU [Wed, 24 Sep 2014 15:37:42 +0000]
arm: tegra12_defconfig: max98090 as loadable module

Bug 1550880

Change-Id: I6278cde7643dd3b298d72c54497cb5274a5de544
Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/538460
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm64: configs: t210: enable emc scaling
Seema Khowala [Fri, 3 Oct 2014 22:28:36 +0000]
arm64: configs: t210: enable emc scaling

Change-Id: Ib626710c8e964ff64cf720d2c9c1bd2e30426212
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/553485
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agotmp: add some LP3 tables to the ERS DTB
Alex Waterman [Thu, 2 Oct 2014 23:27:48 +0000]
tmp: add some LP3 tables to the ERS DTB

Change-Id: I7cbab72afa8cf6a669873c407f4586c1e3956450
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/553086
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: tegra: mc: Allow reading carveout info
Alex Waterman [Wed, 6 Aug 2014 21:25:43 +0000]
ARM: tegra: mc: Allow reading carveout info

Provide an API for reading carveout information such as
base address and size. This helps avoid other drivers reading
MC registers on their own.

This API only works after the MC driver has been initialzed.

Bug 1540908

Change-Id: I14176ce2742583ee81d473d8b805bcfac6c28e94
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/453652
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM64: tegra: t210: DT for 6 camera support
David Wang [Mon, 22 Sep 2014 21:26:04 +0000]
ARM64: tegra: t210: DT for 6 camera support

Adding support for 6 cameras in device tree, including
new camera profiles, module definitions.

bug 1545729

Change-Id: I689a4b8915ea4ec613b0dc4cd9737356530ed330
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/533989
Reviewed-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM64: tegra: t210: Board file for 6 camera
David Wang [Mon, 22 Sep 2014 21:29:12 +0000]
ARM64: tegra: t210: Board file for 6 camera

Adding support for 6 cameras in t210 board file, added
capability structures and platform data.

bug 1545729

Change-Id: I9f5abf392fed34cfa7ff69a62940f7b7616bdaa0
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/533990
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agodrivers: i2c: Update i2c mux driver for 6 cameras
David Wang [Thu, 2 Oct 2014 21:57:09 +0000]
drivers: i2c: Update i2c mux driver for 6 cameras

Updating i2c mux driver to support 6 cameras using one
i2c input and outputing to 6 i2c buses.

bug 1545729

Change-Id: I5f982583cab497e3676d24e6b842adc7266b303b
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/533991
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agodvfs: tegra21: Restore VDD_CORE max limit
Alex Frid [Sat, 4 Oct 2014 04:45:50 +0000]
dvfs: tegra21: Restore VDD_CORE max limit

Restored 1.0V VDD_CORE maximum limit accidentally lifted by commit
a50710717c59f0f4a024c8dd77ed5d0167d9decf

Change-Id: Ibf96ba60b8a75497cc7b0be8a69db35ee5bd2467
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/553579
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoplatform: tegra: Only update target_state on error
Sai Gurrappadi [Fri, 3 Oct 2014 21:28:11 +0000]
platform: tegra: Only update target_state on error

Update the target cluster state only if the cluster switch request
fails. If the cluster switch doesn't fail then target_state is
already correct so no need to update it.

Bug 1561095
Bug 200022475

Change-Id: I1ad6b049145c796521158f49fd8a5e3f7a1cc006
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/553477
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoplatform: tegra: Fix auto cluster enable
Sai Gurrappadi [Fri, 3 Oct 2014 21:23:31 +0000]
platform: tegra: Fix auto cluster enable

The enable sysfs node now properly removes any pending cluster switch
requests if disabled and starts the cluster switch update loop if
enabled.

Bug 1561095
Bug 200022475

Change-Id: Ibb9fa90f0f7cfc925b671e0b2c7d3496dc06fca1
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/553476
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoplatform: tegra: Remove unnecessary timer
Sai Gurrappadi [Fri, 3 Oct 2014 20:55:53 +0000]
platform: tegra: Remove unnecessary timer

Use a delayed work struct instead of a separate timer for clusterswitch
work.

Bug 1561095
Bug 200022475

Change-Id: I375077d9df8f7f7f2a26f7575b92e967cee51858
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/553475
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agotegra: thermal: t210: enable thermal actions in dt
Diwakar Tundlam [Thu, 2 Oct 2014 21:47:15 +0000]
tegra: thermal: t210: enable thermal actions in dt

Enable shutdown, heavy throttling and balanced throttling on soctherm
zones via of-thermal device tree configuration per platform.

Presently enabled for ers E2220 and Loki-E platforms.

Note: Since any changes to trip temperatures via sysfs nodes is
handled in of-thermal layer and not propagated to the underlying
thermal-sensor driver, we currently don't support the ability to
change shutdown and hw-throttle trip points. This would be supported
once the required enhancements to of-thermal code is done.

Change-Id: I16d3daf3fcb08eefefbdd565e3025489bdcfeea4
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/553056

5 years agoasoc: codec: es755: change spi operation speed
Dara Ramesh [Mon, 6 Oct 2014 14:24:08 +0000]
asoc: codec: es755: change spi operation speed

change spi operation speed to 4.8 Mhz.

bug 200043159

Change-Id: I5230e6f2c4785a1c647c11629ec1eaa61c999f3b
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/553833
GVS: Gerrit_Virtual_Submit
Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com>
Tested-by: Niranjan Wartikar <nwartikar@nvidia.com>
Reviewed-by: Pierre Gervais <pgervais@nvidia.com>

5 years agoarm64: dts: t18x: support for linsim CL 33688874
Adeel Raza [Fri, 3 Oct 2014 23:44:22 +0000]
arm64: dts: t18x: support for linsim CL 33688874

Going forward T18x will support multiple snaps of the HW tree. Each snap
will require its own device tree. This process is being started with
linsim CL 33688874.

Bug 1561645

Change-Id: Ia410c1e25b841d29a7cdae9add25e8873d79a41d
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/553519
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

5 years agoplatform: tegra: cluster switch tracing
Antti P Miettinen [Sat, 4 Oct 2014 10:09:40 +0000]
platform: tegra: cluster switch tracing

Add trace points for T210 cluster switch.

Change-Id: I665b2dfec8fd89ec704bf060f1117a92c306bbfe
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/553627
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Track error notifiers per-job
Arto Merilainen [Sun, 5 Oct 2014 15:18:48 +0000]
video: tegra: host: Track error notifiers per-job

Currently error notifiers are tracked per-channel, however, this
does not work correctly in case we have jobs from multiple
applications (channel instances).

This patch modifies the notifiers to be tracked in job level hereby
allowing to have multiple notifiers per channel.

Change-Id: I324c99eb454efd87ad754bf230b41ae7930acc18
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553633
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoArm: tegra: p2360: Remove max155669 platform data
sreenivasulu velpula [Sun, 14 Sep 2014 17:51:47 +0000]
Arm: tegra: p2360: Remove max155669 platform data

Remove platform data, Pass from DT.

Bug 200032624

Change-Id: Ia32fb0f50b0c08e339fc47ddddd0d12ddba2f3c0
Signed-off-by: sreenivasulu velpula <svelpula@nvidia.com>
Reviewed-on: http://git-master/r/498363
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>

5 years agovideo: tegra: host: Boot devices when pm disabled
Arto Merilainen [Fri, 3 Oct 2014 13:56:12 +0000]
video: tegra: host: Boot devices when pm disabled

This far nvhost has assumed that pm runtime is always available and
hence booting devices has been managed by restore_state callback.
This patch modifies nvhost_module_busy call so that it calls
.finalize_poweron() callback in case pm runtime is disabled.

Change-Id: Id2e204c78d7847e915e7650b2e00642d19cc00a0
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553280
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: vic: Add T186 hooks
Arto Merilainen [Fri, 3 Oct 2014 12:14:15 +0000]
video: tegra: host: vic: Add T186 hooks

This patch adds hooks to initialise VIC on T186.

Change-Id: I1696f66fb24018555f92a5a7ef0283c2622bc00d
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/553277
Reviewed-by: Automatic_Commit_Validation_User

5 years agousb: xhci: tegra: call elpg exit for all cases
Krishna Yarlagadda [Wed, 16 Jul 2014 09:42:48 +0000]
usb: xhci: tegra: call elpg exit for all cases

we can get a wake event when SS partition is powergated and
host partition is still not powergated. Handle this case

Bug 200008910

Change-Id: I79a4df297e0e222e64b7f646bf4c532bf2268c4a
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/501463
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agovideo: tegra: host: free sync point synchronously
Deepak Nibade [Mon, 29 Sep 2014 11:01:53 +0000]
video: tegra: host: free sync point synchronously

For a host managed sync point in nvhost_free_syncpt(),
we first check if MIN != MAX and in that case print an
error and return without freeing the sync point.

This causes a sync point leak.

To fix this, wait until MIN == MAX instead of returning.
We wait for MAX_TIMEOUT in this case. Even if sync point
is stuck, recovery process should help to free the
sync point

Bug 200039324

Change-Id: If5240e007e26ff4fd819ec47694dd56eeaa82f6a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/542638
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Tested-by: Arto Merilainen <amerilainen@nvidia.com>

5 years agoARM64: dt: tegra210: disable iommu for sdmmc2
Manikanta [Wed, 1 Oct 2014 10:58:33 +0000]
ARM64: dt: tegra210: disable iommu for sdmmc2

enabling iommu causing regression in wi-fi perf vaules,
disable iommu until perf issue is fixed.

bug 200042955

Change-Id: I14dc9edcf6895cb18398f828aa15868fc43d1907
Signed-off-by: Manikanta <mmaddireddy@nvidia.com>
Reviewed-on: http://git-master/r/552512
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoplatform: tegra: pmc: Fix void function parameter
Amit Sharma [Mon, 29 Sep 2014 13:49:12 +0000]
platform: tegra: pmc: Fix void function parameter

Fixed void function parameter list sparse warning for following functions:
- tegra_get_pm_data()
- tegra_pmc_set_dpd_sample()
- tegra_pmc_clear_dpd_sample()
- tegra_pmc_remove_dpd_req()

Bug 200032218

Change-Id: I32bfe96f546ab9161b9fdba4d50f21c183e6a6bb
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/542671
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm64: t210: Enable WDT based on odmdata value
Jay Bhukhanwala [Mon, 15 Sep 2014 23:07:50 +0000]
arm64: t210: Enable WDT based on odmdata value

Bug 1554432

Change-Id: I32a37f7ac8a394ab0c2440a60367b84a6df8b97c
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/499033

5 years agoata: ahci: skip calling tegra_ahci_pad_config()
Preetham Chandru R [Tue, 23 Sep 2014 16:23:47 +0000]
ata: ahci: skip calling tegra_ahci_pad_config()

Skip calling tegra_ahci_pad_config() for T210.
In T210 case clearing the SW Control of SATA PADPLL
and SATA PHY are taken care in uphy initialization
and for PLLE it is taken care by tegra clock framework
Also removed the below instructions as it was redundant.
val = clk_readl(CLK_RST_CONTROLLER_PLLE_MISC_0);
val &= ~(T124_PLLE_IDDQ_SWCTL_MASK | PLLE_IDDQ_OVERRIDE_VALUE_MASK);
clk_writel(val, CLK_RST_CONTROLLER_PLLE_MISC_0);

Bug 1555570

Change-Id: Ie9a66b8174c23937b1732f88ac7dcf07e7b87e62
Signed-off-by: Venkata Jagadish <vjagadish@nvidia.com>
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/500717
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm64: dts: remove DSI pad dpd
Min-wuk Lee [Fri, 3 Oct 2014 17:38:37 +0000]
arm64: dts: remove DSI pad dpd

Remove DSIC and DSID deep power mode
in Bowmore_FFF

Bug 1371533

Change-Id: Id353a98ebb10fdc638a2af695ca1d8ea33db78a2
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/553329
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Tested-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: delete TEGRA_USE_SECURE_KERNEL usage
Varun Wadekar [Wed, 1 Oct 2014 03:36:52 +0000]
arm: tegra: delete TEGRA_USE_SECURE_KERNEL usage

We do not use this flag in the kernel.

Change-Id: I720448091c2817238d3b36a012240f810a316804
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/552336

5 years agoarm64: t210-ers: map unused display regulators to battery
Vineel Kumar Reddy Kovvuri [Mon, 29 Sep 2014 04:42:03 +0000]
arm64: t210-ers: map unused display regulators to battery

Map unused display regulators to battery source on T210 ers

Change-Id: I8d7ff3852772219d57d7bbe414e781535aaeed34
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/542519
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm64: remove data cache flush
Antti P Miettinen [Thu, 2 Oct 2014 07:17:47 +0000]
arm64: remove data cache flush

Flushing the complete data cache upon CPU reset is totally bogus.
If we are worried about bogus valid entries in the data cache
we should be just invalidating the data cache, not cleaning and
invalidating it. Flush would just push the bogus data to memory.
Also, with multiple CPUs, you do not want to invalidate shared
caches as those can contain the currently valid copy of some
data. Therefore the invalidation should be done only to the
appropriate level e.g. LoUIS. However, modern CPUs typically come
out of reset with caches invalid and the arm64 boot spec requires
that kernel is entered with cache disabled and invalid.

Upstream dropped the flush in

commit bff705950e2cdcf35641dee35eb14bad9ed49e8f
Author: Mark Rutland <mark.rutland@arm.com>
Date:   Wed Aug 14 09:54:54 2013 +0100

    arm64: remove unnecessary cache flush at boot

Change-Id: If30022339f36598d98f69fb3e7e94c9ae3646bed
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/552837
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agogpu: nvgpu: calculate zcull_sm_num_rcp using tpc_count
David Li [Tue, 23 Sep 2014 07:33:27 +0000]
gpu: nvgpu: calculate zcull_sm_num_rcp using tpc_count

old value is for 1 SMs so on gm20b with 2 SMs it resulted in half zcull coverage

bug 1553171

Change-Id: I269f9a333a059b2ef533672df63ccaa90b2d00c7
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/500517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agogpu: nvgpu: Fix gpu identification for 3demc
Samuel Russell [Mon, 29 Sep 2014 20:06:03 +0000]
gpu: nvgpu: Fix gpu identification for 3demc

Modify GPU detection in 3demc-bw-ratio to use the SOC Id.

Bug 1364894

Change-Id: If52e8c5153e76b29d67d28c52303b095df2e8bf0
Signed-off-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-on: http://git-master/r/542770
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoRevert "video: tegra: nvmap: remove support for Deprecated GET_ID/FROM_ID ioctl's"
Krishna Reddy [Sat, 4 Oct 2014 02:07:49 +0000]
Revert "video: tegra: nvmap: remove support for Deprecated GET_ID/FROM_ID ioctl's"

This reverts commit a67ea4b45e012e5342abf0ab5404ced4ae809e2b.

Change-Id: I74c9bb1cca69f62925a6c2133d79525ae1e66883
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/553568

5 years agoarm64: dts: remove low-v-win
Jon Mayo [Fri, 19 Sep 2014 20:45:01 +0000]
arm64: dts: remove low-v-win

T210 does not support low voltage windows.

Bug 1556342

Change-Id: Ib42fc4211166ad3e9ac4e21df91f9f7630419839
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/500896
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dc: remove alt dvfs support
Jon Mayo [Fri, 19 Sep 2014 21:35:01 +0000]
video: tegra: dc: remove alt dvfs support

remove low_v_win support.

Bug 1556347

Change-Id: I52093ca2705e62b4cebd88b9223a54bb956128d1
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/500909

5 years agovideo: tegra: nvmap: remove support for Deprecated GET_ID/FROM_ID ioctl's
Maneet Singh [Mon, 29 Sep 2014 18:24:15 +0000]
video: tegra: nvmap: remove support for Deprecated GET_ID/FROM_ID ioctl's

Remove support and add warning message for deprecated IOCTL's -
NVMAP_IOC_FROM_ID and NVMAP_IOC_GET_ID. These ioctl calls
are deprecated by corresponding FD ioctl calls.

Bug 1553082

Change-Id: I3cd531422293f19496687f346692fa91ebe58a40
Signed-off-by: Maneet Singh <mmaneetsingh@nvidia.com>
Reviewed-on: http://git-master/r/498045
(cherry picked from commit 420dce0a99231453ebbd091f110d0de816e4885e)
Reviewed-on: http://git-master/r/539095
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: fix use-after-free race condition
Maneet Singh [Fri, 12 Sep 2014 03:12:33 +0000]
video: tegra: nvmap: fix use-after-free race condition

Incremented nvmap_handle ref count in utility function
nvmap_get_id_from_dmabuf_fd() before the function release reference
to dma buffer. This is required to avoid race conditions in nvmap
code where nvmap_handle returned by this function could be freed
concurrently while the caller is still using it.

As a side effect of above change, every caller of this utility
function must decrement nvmap_handle ref count after using the
returned nvmap_handle.

Bug 1553082

Change-Id: Iffc2e5819f8b493d5ed95a9d0c422ccd52438965
Signed-off-by: Maneet Singh <mmaneetsingh@nvidia.com>
Reviewed-on: http://git-master/r/498135
(cherry picked from commit afddea745cc4f4a824be501ecbbb50f55e7e6f04)
Reviewed-on: http://git-master/r/539094
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: dc: Fix parse_mode for fake dp
Vinod G [Thu, 2 Oct 2014 22:43:39 +0000]
video: tegra: dc: Fix parse_mode for fake dp

Display_timing variables are not being parsed
for dp or fake_dp from DT. Adding the support
for the fake_dp.

Change-Id: I7b92cb93437ea04c248a29ed15ca106bfd654750
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/553069
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aron Wong <awong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: Code correction for simulation support
Vinod G [Wed, 1 Oct 2014 05:20:09 +0000]
video: tegra: dc: Code correction for simulation support

Add nvdisp_get_line_stride function
Enabled fake_dp connection variable

Change-Id: Ieea3a4820bbf30e70ba967cedb2c16abc4adc71f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/552376
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agoDNI: Disable syncpoint checking for nvdisplay
Vinod G [Wed, 1 Oct 2014 05:15:14 +0000]
DNI: Disable syncpoint checking for nvdisplay

Syncpoint is not properly functional with simulation.
Disabling the syncpoint check code for nvdisplay.
Should be reverted later.

Change-Id: I4a0aee77caece8669c97ec8e962fdee587ff25c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/552368
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: dc: Avoid Setting Active state
Vinod G [Wed, 1 Oct 2014 05:01:53 +0000]
video: tegra: dc: Avoid Setting Active state

SW driver is not suppose to set MUX_ACTIVE state to
DC_CMD_STATE_ACCESS. As this was used for previous chips
adding checking to set only MUX_ASSENBLY for nvdisplay.

Change-Id: I0bb3e61641639c2222ed53c32b1e53fe00965552
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/552362
Reviewed-by: Chao Xu <cxu@nvidia.com>
Tested-by: Chao Xu <cxu@nvidia.com>

5 years agousb: gadget: tegra-xudc: disable u1
Hui Fu [Thu, 2 Oct 2014 00:13:53 +0000]
usb: gadget: tegra-xudc: disable u1

Disable U1 to improve link stability.

Bug 200039349

Change-Id: I00c3ed65729666b235c292bc66f118ebc179fdca
Signed-off-by: Hui Fu <hfu@nvidia.com>
Reviewed-on: http://git-master/r/553047
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Ashutosh Jha <ajha@nvidia.com>

5 years agovideo: tegra: dp: always write OUI on DP enable
Daniel Solomon [Thu, 2 Oct 2014 21:24:15 +0000]
video: tegra: dp: always write OUI on DP enable

The OUI value is stored on the sink side, which gets
cleared whenever it's powered off. The OUI value
needs to be re-written whenever the sink gets powered
on (i.e., during DP enable).

Bug 1347562

Change-Id: I24a672b26f1dc3e415e083721beae7ebfc39d3ff
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/553042
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: sor: Add missing NVSR_DP flag
Daniel Solomon [Wed, 1 Oct 2014 00:39:03 +0000]
video: tegra: sor: Add missing NVSR_DP flag

Add missing TEGRA_DC_OUT_NVSR_DP flag in output
interface check.

Bug 1315461

Change-Id: Ib864675f3ec668c23d5d4d09160959f2bde35857
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/552288
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>