5 years agovideo: tegra: support display board PM313
Hyungwoo Yang [Mon, 24 Oct 2011 22:06:17 +0000]
video: tegra: support display board PM313

This change supports PM313 with 19X12 panel.
The change uses PM313 in "Single input to Dual output" mode

Bug ID : 822980
Reviewed-on: http://git-master/r/50215
(cherry picked from commit b83e795747fa860b5b7fb66b2067ebe4f15bcfd0)

Change-Id: Iabf707ded2976e9877481c215d0b1f1940781f14
Reviewed-on: http://git-master/r/60085
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rfd752366b937526a13b755a13edaa5986c681665

5 years agoarm: tegra: use non-blocking api to cancel work from mc error isr
Nitin Kumbhar [Fri, 21 Oct 2011 12:50:13 +0000]
arm: tegra: use non-blocking api to cancel work from mc error isr

An api (del_timer_sync), which can sleep, should not be used in
hardirq context. This gives warnings for potential deadlock. Use
non-sleeping api to cancel the work instead. In this case, if the
work is already running, it would unthrottle mc error prints.

BUG 889717

Change-Id: I4c0205766d82a45a04d1c0125bb8ed5927757456
Reviewed-on: http://git-master/r/59604
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>

Rebase-Id: R713c536217d0169f395ffb199ec2a97b274b9914

5 years agoarm: tegra: Handler for parsing kernel command max_cpu_curr
Laxman Dewangan [Sat, 15 Oct 2011 10:14:04 +0000]
arm: tegra: Handler for parsing kernel command max_cpu_curr

Adding handler for parsing the kernel command max_cpu_curr and api
for retruning the max_cpu_current.

bug 888679

Reviewed-on: http://git-master/r/58626
(cherry picked from commit 4d2da03c37a1a1401b4ef87b888f487a99b175b7)

Change-Id: Ic5a53fe4e41317f48b986867081f3e7d96103f0d
Reviewed-on: http://git-master/r/59290
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Ra426e2b10268bc7eadbe394c107528378f043e15

5 years agoARM: tegra: power: Force FW bit when SMP is enabled.
Alex Frid [Tue, 11 Oct 2011 03:32:49 +0000]
ARM: tegra: power: Force FW bit when SMP is enabled.

Set FW bit in CP15 auxiliary control register after LP=>G CPU mode
switch if SMP bit in the same register is set. On Tegra3 in LP mode
FW bit is always zero, even though SMP bit is retained. Hence, this
change recovers FW bit on return from LP to G-mode.

Change-Id: I9f0021ab90866cb8686d73eb6ad5bbedbb2ceb90
Reviewed-on: http://git-master/r/57203
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R37dbe2079eafcfb47babaf41b53818a9130d2bbe

5 years agoARM: tegra: power: Do not switch Tegra3 to PLLP
Alex Frid [Sat, 1 Oct 2011 01:38:59 +0000]
ARM: tegra: power: Do not switch Tegra3 to PLLP

Do not switch Tegra3 to PLLP on sleep entry: no need - unlike Tegra2
PLLX on Tegra3 is not disabled when CPU is rail gated; also G/LP mode
switch clock configuration is set by mode switch prolog and should not
be overwritten at the last moment.

Change-Id: I9aa8463c6b1c04c0a70e70c1e2cd4113a679e100
Reviewed-on: http://git-master/r/57202
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R9a8d78a363c261d45e48832fcbed7fa2854f7da8

5 years agoarm: tegra: cardhu: Initialize gpio pins mode
Laxman Dewangan [Tue, 4 Oct 2011 12:58:57 +0000]
arm: tegra: cardhu: Initialize gpio pins mode

Initializing the pins which is used in gpio to their inital state.

bug 876305

Reviewed-on: http://git-master/r/57516
(cherry picked from commit 3f33cb777295669e71e291bb05651d3c6c4b37d5)

Change-Id: Ie05862e5184bb95c85cf7aa96ce2eca497c01c93
Reviewed-on: http://git-master/r/57817
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3886fa24fc77365529b86eef67f10a428764aee4

5 years agoarm: tegra: Avoid negative number parsing for debug port
Laxman Dewangan [Wed, 28 Sep 2011 09:12:49 +0000]
arm: tegra: Avoid negative number parsing for debug port

Avoiding negative number parsing for debug port id.

bug 854995

Reviewed-on: http://git-master/r/57328
(cherry picked from commit 81ce6594db0a2b9131e3a1317ef1f10e8310aad5)
Change-Id: I38e9e545c06a61b79d292c86dcbf8c595d2eddca
Reviewed-on: http://git-master/r/57787
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R2fe0b743db9f2b87f0a0715aeda12e7c00b041a7

5 years agoarm: tegra: Support for kernel command audio_codec
Laxman Dewangan [Sun, 18 Sep 2011 11:19:10 +0000]
arm: tegra: Support for kernel command audio_codec

Adding the handler to parse the kernel command "audio_codec".

bug 876544

Reviewed-on: http://git-master/r/56623
(cherry picked from commit b82c518354864c7dba03beea3c576edfab428efd)

Change-Id: Icb42164ea1276f4f5af941b8ba2f80076759af8b
Reviewed-on: http://git-master/r/57779
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rf3a0eed42103ef830c9697da42eb685fde6f6fe9

5 years agoarm: tegra: pm: issue a pl310 cache sync for tegra2
Mayuresh Kulkarni [Thu, 15 Sep 2011 09:26:10 +0000]
arm: tegra: pm: issue a pl310 cache sync for tegra2

this needs to be done when the lp2 is aborted before the
stipulated programmed time to wake-up

for bug 867094

Change-Id: I02102ed8afa69d782de5950118352e80edc79df4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/52581
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R5938771982b7cceb9ea23ee73852ca8b9b3490ae

5 years agoarm: tegra: gpio: API to configure pins as gpio with init value
Laxman Dewangan [Fri, 30 Sep 2011 10:44:27 +0000]
arm: tegra: gpio: API to configure pins as gpio with init value

Adding api to configure pins in gpio mode with init value before
gpio library is up. This will provide to configure the pins in
initial state and avoid any glitch in pins.

bug 876305

Reviewed-on: http://git-master/r/56630
(cherry picked from commit 9e357b69d25f96c13acb660860bcdf8e0ab0a1ef)

Change-Id: Ia14721c0bf96e1a45561139fdbbf2d995b9a4963
Reviewed-on: http://git-master/r/57265
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc775d23898a6275d633e4474e6cf9b10395697e2

5 years agoarm: tegra: Add handle for kernel option power_supply
Laxman Dewangan [Sun, 4 Sep 2011 11:40:13 +0000]
arm: tegra: Add handle for kernel option power_supply

Adding the handler function for the kernel command line
option "power_supply".

Reviewed-on: http://git-master/r/50674
(cherry picked from commit 8d9e6bbe59ab68f44a4713f5d1bcc7877baf8180)

Change-Id: I07796b6ee5893d73ac7557e81aac5d26b299c491
Reviewed-on: http://git-master/r/57262
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rd64bf314bcdfe3f7bdbcdee946ed261bfce5938f

5 years agoarm: tegra: Remove T30 SPDIF DMA resource info
Sumit Bhattacharya [Tue, 4 Oct 2011 12:02:36 +0000]
arm: tegra: Remove T30 SPDIF DMA resource info

Bug 872652

Change-Id: Iaea76918169f3270f865122f824f60678c419b50
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/55970
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R70b9408e1c66c97a63a9408dda43aacd369c3178

5 years agoarm: tegra: whistler: add headphone debouncetime and irq
Nikesh Oswal [Mon, 10 Oct 2011 12:06:28 +0000]
arm: tegra: whistler: add headphone debouncetime and irq

add entries for headphone detection irq and debouncetime in
whistler specific board files

Bug: 862023

Change-Id: Ia72ec10f51a1bde0f81eb488b36a8b1439cedf1d
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/57034
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7fe99f98b6d8c11562af00da3bef9ba5bfd56d1c

5 years agoarch: arm: Enable SPDIF driver for Tegra30
Sumit Bhattacharya [Wed, 28 Sep 2011 12:29:22 +0000]
arch: arm: Enable SPDIF driver for Tegra30

Bug 872652

Change-Id: Ic170dc2fc86f74d9e67d3b73a6f83368597dafcb
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/54975
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra59bdfb6b9109169935b3d5c9275053290d741ad

5 years agoarm: tegra: parse kernel command line for debug port id
Laxman Dewangan [Thu, 8 Sep 2011 14:06:17 +0000]
arm: tegra: parse kernel command line for debug port id

Parsing the linux command line for the debug port id.

bug 795847

Reviewed-on: http://git-master/r/51370
(cherry picked from commit f988c97564f9ecf4b78f4e935e2cfc4ca1b6db0e)

Change-Id: Ib1bbdd9f671ab4c22cffdf379d3b9fd79a5a8736
Reviewed-on: http://git-master/r/57042
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R8b31dafaa124fb7e99d219bb464703b5696da0ff

5 years agoarm: tegra: fix "malformed early option" warning
Deepesh Gujarathi [Fri, 7 Oct 2011 09:48:30 +0000]
arm: tegra: fix "malformed early option" warning

early_param expects return value 0 for success as
opposed to 1 in case of set_param handler.

Bug 875134

Change-Id: I3eaf540a44fef4d211add399cedc258314266ed0
Reviewed-on: http://git-master/r/56638
Tested-by: Deepesh Gujarathi <dgujarathi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: Rbcbd37982e85a4cbad71319945efbc0ab6052d90

5 years agoARM: tegra: fuse: Fix tegra_chip_uid
Dan Willemsen [Wed, 5 Oct 2011 22:26:57 +0000]
ARM: tegra: fuse: Fix tegra_chip_uid

This now matches what the bootloader thinks the chip ID is (and the lot
code is no longer all zeros).

Change-Id: I46dc677b983dd28f7f77e49919860fef66da8f51
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/56316
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfb7b961acd57447df95600d4f1678d84242ed1b9

5 years agoARM: tegra: power: Add Tegra3 cpu idle parameters
Alex Frid [Sat, 1 Oct 2011 04:27:37 +0000]
ARM: tegra: power: Add Tegra3 cpu idle parameters

Add Tegra3 cpu idle parameters: lp2_0_in_idle and lp_n_in_idle
to independently control LP2 mode for boot and secondary cpus.

Change-Id: I7e526b9bd78a9d5c3235307bbc89f5fb507bec2b
Reviewed-on: http://git-master/r/55630
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rc6a468b2e9e065c344b2386366d5a47d77ddf037

5 years agoARM: tegra: power: Update Tegra3 LP2 time prediction
Alex Frid [Thu, 29 Sep 2011 05:42:06 +0000]
ARM: tegra: power: Update Tegra3 LP2 time prediction

Use local timer count to predict time to be spent by secondary CPU
in LP2 state instead of scheduler timing. This is more accurate, as
local timer wakes CPU after counts down to zero.

Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35
Reviewed-on: http://git-master/r/55629
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>

Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631

5 years agoarm: tegra: move core_edp parsing to early_init
Deepesh Gujarathi [Thu, 15 Sep 2011 08:27:02 +0000]
arm: tegra: move core_edp parsing to early_init

since the dvfs init was being called before the kernel commandline was
parsed, it resulted in an incorrect core_edp voltage being set further
leading to an incorrect emc clock.

move parsing of core_edp voltage value to early_param handler.

fixes bug 875134
partial fix for bug 877315

Change-Id: Iab90e35ecb9145f028dd9c7bae7c7c4b49186b55
Originally Reviewed-on: http://git-master/r/52570
Reviewed-on: http://git-master/r/56181
Tested-by: Deepesh Gujarathi <dgujarathi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Sridhar Lavu <slavu@nvidia.com>
Tested-by: Sridhar Lavu <slavu@nvidia.com>

Rebase-Id: Rda263df02e386b4b2f455196c3f6ade7526c45ed

5 years agoARM: tegra: clock: Re-factor shared bus locking
Alex Frid [Sat, 1 Oct 2011 23:00:51 +0000]
ARM: tegra: clock: Re-factor shared bus locking

Current code:
- on tegra2 unnecessary covers with bus lock shared user state update
- on tegra3 does not cover shared bus rate update at all
Modified to cover with bus lock shared bus rate update only on both
tegra2 and tegra3.

Change-Id: Iaa2597136a521adf4285c61eb579c917c2c7965c
Reviewed-on: http://git-master/r/55640
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1b28f32ae37d47c56855023b18c943bf8fd93c74

5 years agoARM: tegra: power: Clean Tegra3 LP2 entry procedure
Alex Frid [Wed, 28 Sep 2011 05:33:50 +0000]
ARM: tegra: power: Clean Tegra3 LP2 entry procedure

- Do not save/restore local timer configuration across secondary CPU
LP2 state. It is always preserved, since local timer is neither power
gated nor reset when secondary CPU is in LP2.

- Do not configure external timer for secondary CPU wake up, since we
can use local timer instead. Moreover, in current code external timer
interrupt is registered too late on secondary CPU after it is brought
on-line, so the timer may not always be able to wake CPU up from LP2.

Change-Id: I864e9910fe7112bbce3ea4dbaef12be4b42fb5dc
Reviewed-on: http://git-master/r/55070
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R3407f05d200d81e29994daf278170d3619714bef

5 years agoARM: tegra: power: Initialize and update LP2 exit latency
Alex Frid [Wed, 28 Sep 2011 03:14:55 +0000]
ARM: tegra: power: Initialize and update LP2 exit latency

Change-Id: Id6bacc252774758d9ea03b7f2cc91897b5817e10
Reviewed-on: http://git-master/r/55069
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Ra8e8dfed500041886700a8fd44b0b917367225b3

5 years agoARM: tegra: timer: Update twd suspend/resume
Alex Frid [Wed, 21 Sep 2011 06:37:36 +0000]
ARM: tegra: timer: Update twd suspend/resume

- Preserve twd periodic load register across suspend and LP2 on main
CPU. Keep timer disabled on resume, since it will be re-configured
later when timekeeping switches from global system timer.

- Generate "load equal zero" warning in twd suspend/resume code only
when timer is in periodic mode.

Change-Id: If7df8be08c0ef4e355f315e3f0b7e3cf1b358f0f
Reviewed-on: http://git-master/r/55068
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R75f3950a915e0953a098620dea9ea32a7d5e9482

5 years agoARM: tegra: dvfs: Disable all rails if one failed to connect
Alex Frid [Fri, 30 Sep 2011 03:50:12 +0000]
ARM: tegra: dvfs: Disable all rails if one failed to connect

Change-Id: I0aa4debdb0bed160c6ff9d6e5863bfa06a693017
Reviewed-on: http://git-master/r/55370
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rfb9dea2f471f257a15d9da163226573f5330ce32

5 years agoARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.
vdumpa [Wed, 4 May 2011 18:48:38 +0000]
ARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.

Bug 804805

(cherry picked from commit 068e6789bd335640ad2b444fae1e74fd9ca974c5)

Change-Id: If79b491133e6080b8b9c90c5adb0f59239ea275f
Reviewed-on: http://git-master/r/54842
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R16eabb01ed2c8197632d6063b5c9f35bed5714dd

5 years agoarm: tegra: smmu: Remove IORESOURCE use from SMMU IOVA range
Hiro Sugawara [Wed, 14 Sep 2011 00:20:35 +0000]
arm: tegra: smmu: Remove IORESOURCE use from SMMU IOVA range

SMMU simply needs to know its assigned IOVA range, but does not need
address space resources.
Bug 874438

Change-Id: I0b9943d06c49363cfc0355586866f3bd6b217274
Reviewed-on: http://git-master/r/54534
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3f4045ef2858960cd987a7477ec6869168ccec7d

5 years agoARM: tegra: Disable AUTO_HOTPLUG for Tegra2.
Gaurav Sarode [Wed, 28 Sep 2011 08:38:39 +0000]
ARM: tegra: Disable AUTO_HOTPLUG for Tegra2.

AUTO_HOTPLUG is not supported on Tegra2 platform.

Change-Id: Id6332b8a5e784bfada42c58803075ee2c70ec019
Reviewed-on: http://git-master/r/54915
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R02328774cd3588a6091446937229983e9131f87c

5 years agoARM: tegra: nvavp: registering new nvavp driver
Bharat Nihalani [Mon, 26 Sep 2011 13:51:08 +0000]
ARM: tegra: nvavp: registering new nvavp driver

Also re-arranged tegra_nvavp code so that it is common accross boards

Bug 880623

Change-Id: I7d634a718e07e07e945fb512466b3a0672aea7e2
Reviewed-on: http://git-master/r/54487
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R188282334f9e0d18985b87c6241f96f663b8f540

5 years agoarm: tegra: correcting wfi sequence
venu byravarasu [Tue, 27 Sep 2011 06:56:46 +0000]
arm: tegra: correcting wfi sequence

As per hardware documentation, dsb should precede wfi.
Hence fixing it.

Change-Id: I1c98581dfe3891d425ab36c1a2bb313e19ad046d
Reviewed-on: http://git-master/r/54626
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3d7e46306d7d97c2cdfa0ec7ce658a1658724a76

5 years agoarch: arm: tegra: Add SPDIF driver support
Sumit Bhattacharya [Sun, 18 Sep 2011 18:48:34 +0000]
arch: arm: tegra: Add SPDIF driver support

Bug 872652

Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>

Change-Id: I7b948b820434721511c008f644b69d93c23865e1
Reviewed-on: http://git-master/r/53094
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R769f97e31513f4479b20d7dff995e06cc72e19bd

5 years agoarm: tegra: Disable LP2 mode by default.
Krishna Reddy [Thu, 22 Sep 2011 02:27:30 +0000]
arm: tegra: Disable LP2 mode by default.

LP2 should be enabled through board specific init rc file.

Change-Id: I2772ad0ccd04fd3933a2286c6335304d2bef60cd
Reviewed-on: http://git-master/r/53920
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra46b97752305db9e3ac2400162872c5e5863034e

5 years agoARM: tegra: power: Flush cache just before cpu shutdown
Alex Frid [Wed, 21 Sep 2011 01:45:53 +0000]
ARM: tegra: power: Flush cache just before cpu shutdown

Re-arranged cpu die procedure to flush L1 cache just before shutdown.
This is necessary as code executed after L1 flush included spin-lock
protected sections, and the unlock operation was not properly detected
by SCU. As a result CPUs that stayed on-line hanged trying to acquire
the same spin-lock.

Bug 864256

Change-Id: I415160d60686094059e62d91cdcf4b264a4fb69f
Reviewed-on: http://git-master/r/53637
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0663eac9b5c3c84d8b7380873bde6af6b2a74a9f

5 years agoARM: tegra: timer: Fix mismatch in twd suspend/resume code
Alex Frid [Tue, 20 Sep 2011 02:27:19 +0000]
ARM: tegra: timer: Fix mismatch in twd suspend/resume code

Change-Id: Ied49d7517574b62ebc54ba8a5ef04d26408f0145
Reviewed-on: http://git-master/r/53347
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Rd540ebbeb48903eea556508be45580c5d260941e

5 years agoARM: tegra: reduce LP0 resume CPU power on time
Jin Qian [Wed, 14 Sep 2011 18:53:35 +0000]
ARM: tegra: reduce LP0 resume CPU power on time

cherry-picked from adf08ef4030598a6bf9036f45584be8acc008fea

Bug 862504

Change-Id: I79460aa4abdccc4f2ca17867197bb12668d59dea
Reviewed-on: http://git-master/r/52420
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rffc2d7314a61f04274e0db116c5a1cb7004dc77d

5 years agoarm:tegra: Add EXPORT_SYMBOL and ioctls for test framework
Rahul Mittal [Wed, 14 Sep 2011 09:34:32 +0000]
arm:tegra: Add EXPORT_SYMBOL and ioctls for test framework

Added EXPORT_SYMBOL to functions to be used by loadable kernel module
for audio test framework. Also added ioctl declarations for the same.

Change-Id: Id8a023c1d76fd031c042c7c663bb0e1df2d33b5c
Reviewed-on: http://git-master/r/52333
Tested-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R88ac0ceb719d9fae5d68d5f9a1894a3562e82b25

5 years agoARM: tegra: power: fix build error on tegra_pm_enter routines
Jin Qian [Mon, 12 Sep 2011 19:33:15 +0000]
ARM: tegra: power: fix build error on tegra_pm_enter routines

Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c
Reviewed-on: http://git-master/r/51852
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861

5 years agoARM: tegra: Add enterprise audio support
Sumit Bhattacharya [Wed, 7 Sep 2011 09:42:51 +0000]
ARM: tegra: Add enterprise audio support

Bug 862023

Change-Id: I0ba560f471088302d6197c564f02606a25f2a5db
Reviewed-on: http://git-master/r/51072
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Raafdfa1c8ada5731492222e59228da084c0905d9

5 years agoARM: tegra: power: do not check time after kernel time suspend
Jin Qian [Fri, 2 Sep 2011 23:24:01 +0000]
ARM: tegra: power: do not check time after kernel time suspend

cluster switch for LP0 is called after linux timekeeping suspend,
which turns off timer.

Bug 862504

Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe
Reviewed-on: http://git-master/r/50611
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a

5 years agoARM: tegra: power: save cluster switch status before entering LP0
Jin Qian [Fri, 2 Sep 2011 23:22:18 +0000]
ARM: tegra: power: save cluster switch status before entering LP0

warm boot reads SCRATCH4 to choose wake-up from LP or G

Bug 862504

Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94

5 years agoARM: tegra: power: move cluster switch to syscore for LP0
Jin Qian [Thu, 1 Sep 2011 02:47:26 +0000]
ARM: tegra: power: move cluster switch to syscore for LP0

move printk as well since they rely on uart resume in syscore

Bug 862504

Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e
Reviewed-on: http://git-master/r/50240
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b

5 years agoARM: tegra: power: fix lp0 suspend
Jin Qian [Thu, 1 Sep 2011 02:39:57 +0000]
ARM: tegra: power: fix lp0 suspend

enable pllm and skip io_dpd for lp0

Bug 862504

Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7
Reviewed-on: http://git-master/r/50239
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0

5 years agoARM: tegra: power: move cluster switch prolog/epilog from suspend
Jin Qian [Wed, 31 Aug 2011 00:23:55 +0000]
ARM: tegra: power: move cluster switch prolog/epilog from suspend

They're called only when doing cluster switch so move them to
cluster control function.

Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c
Reviewed-on: http://git-master/r/49952
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363

5 years agoARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache
Jin Qian [Wed, 24 Aug 2011 20:51:43 +0000]
ARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache

Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f

5 years agoARM: defconfig: tegra3: use REPORT_PRESENT_CPUS
Jon Mayo [Thu, 28 Jul 2011 00:01:57 +0000]
ARM: defconfig: tegra3: use REPORT_PRESENT_CPUS

enable reporting of present cpus in /proc/cpuinfo and /proc/stat

Bug 849167

Original-Change-Id: I8651079ff63c7399942d937cb0af126aa67a2fd7
Reviewed-on: http://git-master/r/43632
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R24122a5d7e8b2517e99518a698f89ac3946a76ec

5 years agoARM: tegra: power: restore reset handler after lp0
Jin Qian [Wed, 24 Aug 2011 01:15:32 +0000]
ARM: tegra: power: restore reset handler after lp0

Bug 862504

Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7
Reviewed-on: http://git-master/r/50241
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400

5 years agoARM: tegra: Update copyrights
Scott Williams [Wed, 7 Sep 2011 19:21:06 +0000]
ARM: tegra: Update copyrights

Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/51157

Rebase-Id: R5aa782b116daefeb126b3bf58af90a7fd78f648d

5 years agoARM: tegra: whistler: Add sound support
Sumit Bhattacharya [Tue, 30 Aug 2011 16:34:55 +0000]
ARM: tegra: whistler: Add sound support

Bug 862023

Change-Id: I32d8406a7c1d88b09156b94dda2a2b47e89e515f
Reviewed-on: http://git-master/r/49874
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R1114efe2768c40b0615a8e22639b01372688a5be

5 years agoARM: tegra: Clean up the chip revision decoder
Scott Williams [Wed, 7 Sep 2011 00:19:18 +0000]
ARM: tegra: Clean up the chip revision decoder

Replace the chip revision decoder with something that is more
extensible and maintainable.

Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50931
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136

5 years agoARM: Tegra: Pinmux: Fix drive strength configuration
Pavan Kunapuli [Fri, 2 Sep 2011 10:02:00 +0000]
ARM: Tegra: Pinmux: Fix drive strength configuration

In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.

Bug 870369

Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704
Reviewed-on: http://git-master/r/49872
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd

5 years agoARM: tegra: power: Tune Tegra3 hotplug algorithm
Alex Frid [Wed, 24 Aug 2011 05:52:42 +0000]
ARM: tegra: power: Tune Tegra3 hotplug algorithm

- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.

- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%

Added tunables:

/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level

Bug 865176
Bug 867186

Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128

5 years agoARM: tegra: pinmux: Prevent access to uninitialized pin groups
Scott Williams [Wed, 31 Aug 2011 15:37:27 +0000]
ARM: tegra: pinmux: Prevent access to uninitialized pin groups

There is no guarantee that every element in the pin group array
will be used (i.e., initialized) for a particular SOC. Prevent
access to pin group array elements that are not initialized.

Original-Change-Id: I90ea3616f8508b12ffe4a7daf9ff4b2bac057075
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50059
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd6c206b805d180fb3c52be52edfeebed701ca73d

5 years agoARM: tegra: speed up framebuffer copy
Jon Mayo [Tue, 30 Aug 2011 01:09:16 +0000]
ARM: tegra: speed up framebuffer copy

Use a memcpy with less overhead in tegra_move_framebuffer, this makes
this function about 30 times faster.

Bug 843089

Original-Change-Id: I4ae9127db6d5ff5d9680e3ff2c3d28463395e39b
Reviewed-on: http://git-master/r/49735
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: R0906917433643ac4ce9ac97284007527ef2d67df

5 years agoarm: tegra: iovmm: Fixed configurablability advertised in Makefile
Hiro Sugawara [Thu, 25 Aug 2011 21:14:02 +0000]
arm: tegra: iovmm: Fixed configurablability advertised in Makefile

CONFIG_TEGRA_IOVMM_SMMU now can be independently disabled and
the kernel still builds.

Original-Change-Id: I009319352f4b125941a58132d2be8d5f36411aab
Reviewed-on: http://git-master/r/49278
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb663949db3e3fcfa6418f71cdc74662dded08fc6

5 years agoARM: tegra: Use SATA and PCIE SOC architecture conditionals
Scott Williams [Thu, 1 Sep 2011 23:20:47 +0000]
ARM: tegra: Use SATA and PCIE SOC architecture conditionals

Use the SOC architecture conditionals for determining the
presense of PCIE and SATA.

Change-Id: I312d0d1b45fc08e4938260b978d083b113ed9d66
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50379
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra949d477a8e96ccc7760c4974ae93909ea054bbb

5 years agoARM: tegra: Only enable fuse programming on silicon platforms
Scott Williams [Tue, 30 Aug 2011 00:31:46 +0000]
ARM: tegra: Only enable fuse programming on silicon platforms

Fuse programming is possible only on silicon platforms.
Do not enable it for simulation or FPGA platforms.

Change-Id: If1bec072eeaae1ee95720a37e37fcb7c8e8ee464
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49724
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R71d2073c18353d32a2b5373819f2e27e1e8bb680

5 years agoARM: tegra: Clean up makefile conditionals
Scott Williams [Thu, 1 Sep 2011 22:07:44 +0000]
ARM: tegra: Clean up makefile conditionals

Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50358
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2

5 years agoARM: tegra: Clean up power gating code
Scott Williams [Thu, 1 Sep 2011 22:03:48 +0000]
ARM: tegra: Clean up power gating code

Clean up conditionals.
Use the generic name of CELP for the LP partition.

Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a

5 years agoARM: tegra: Remove unnecessary SOC conditionals
Scott Williams [Thu, 1 Sep 2011 21:59:01 +0000]
ARM: tegra: Remove unnecessary SOC conditionals

Change-Id: I4ad09ea97db373dbed0764214fc5d98be2e29f7a
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50356
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5c2b9b638a4e150eb1fa6e1d4f587bb71622efea

5 years agoARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets
Scott Williams [Thu, 1 Sep 2011 21:55:13 +0000]
ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets

Determine the number of GPU register sets based upon the setting
of ARCH_TEGRA_DUAL_3D.

Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50355
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96

5 years agoARM: tegra: Only Tegra3 has TSENSOR
Scott Williams [Thu, 1 Sep 2011 21:47:32 +0000]
ARM: tegra: Only Tegra3 has TSENSOR

Change-Id: I232d3ae5e037d491d1d8d185e75c1c9a7035cd4c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50354
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R899f3aaf97ca7f21785749a8675ba1bc461f81f9

5 years agoARM: tegra: Use forward looking architecture conditionals
Scott Williams [Thu, 1 Sep 2011 02:24:56 +0000]
ARM: tegra: Use forward looking architecture conditionals

Change-Id: I31f2717327a627ad83e4cc2f083b71fd68fb1465
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50221
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcaef7248cf06aa01c40b8e5eae13e3a20ed097d3

5 years agoARM: tegra: Add SOC architectural capabilities
Scott Williams [Thu, 1 Sep 2011 15:56:31 +0000]
ARM: tegra: Add SOC architectural capabilities

Add architectural capabilities the at are selected by the top-level
architecture type rather than deriving this knowledge directly from
the top-level type in the code.

Change-Id: I1c1e5d986a65301cf2e474d866f01e4f8c2a5505
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50298
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R118b523b4c6cac8f4f530f01a1d14ed961d5a085

5 years agoARM: tegra: Fix warnings
Scott Williams [Thu, 25 Aug 2011 21:28:10 +0000]
ARM: tegra: Fix warnings

Change-Id: Ic2cecccf0f4f6e6ca612af2ee07acdbca2ce07a5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49281
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R59e04e0a46099403284a036de7f35d21c6188d81

5 years agoARM: tegra: power: Call cluster_switch_prolog/epilog for LP1
Yudong Tan [Thu, 18 Aug 2011 22:29:08 +0000]
ARM: tegra: power: Call cluster_switch_prolog/epilog for LP1

cluster_switch_prolog is needed to set up car/flow controller registers
for LP1 entry. epilog is needed to clean up some flags in flow controller
after LP1 exit.

Bug 862502

Change-Id: Ib9eeac6fc541cfa644d782071dbd4187255404d8
Reviewed-on: http://git-master/r/47585
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2c72673ba1b7f04ffa1b760ff54aaf73cf23f09e

5 years agoARM: tegra: power: Correct settings for the BURST_POLICY register
Yudong Tan [Wed, 17 Aug 2011 18:30:00 +0000]
ARM: tegra: power: Correct settings for the BURST_POLICY register

This is needed to allow clusters come up on CLKM

Bug 862502

Change-Id: I667cccbf6cbc5af0d47ebc07a5c6c83f14a1cc4c
Reviewed-on: http://git-master/r/47584
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2c7ae1605c0d1561c7fa40f45d09ee073d920497

5 years agoARM: tegra: power: Enable LP1 power mode for cluster switch
Yudong Tan [Wed, 17 Aug 2011 18:29:12 +0000]
ARM: tegra: power:  Enable LP1 power mode for cluster switch

Bug 862502

Change-Id: Id119be010eadeaaebeea9a3c78313500f8dc481b
Reviewed-on: http://git-master/r/47583
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R80a63d66336349a3c05da17e4565902390763e74

5 years agoARM: tegra: power: implement LP1 suspend/resume for Tegra3
Yudong Tan [Thu, 18 Aug 2011 22:26:52 +0000]
ARM: tegra: power: implement LP1 suspend/resume for Tegra3

Bug 862502

Change-Id: If70e54fb32ce14d5f13dde1d7fb4c1f1499a6722
Reviewed-on: http://git-master/r/47398
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra77a54e6930692bca628a97bf1de10a30408cdef

5 years agoARM: tegra: power: fix cpu context save page mapping
Jin Qian [Tue, 23 Aug 2011 04:29:48 +0000]
ARM: tegra: power: fix cpu context save page mapping

Change-Id: Ie2bcc74d4a4fb76ee29c4a01e5dae72261da4885
Reviewed-on: http://git-master/r/48623
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5ee134042966de7a620f60095169e3aba823cd82

5 years agoARM: tegra: power: Fix non-SMP LP2 timer registration issues
Scott Williams [Fri, 26 Aug 2011 01:48:42 +0000]
ARM: tegra: power: Fix non-SMP LP2 timer registration issues

Don't call irq_set_affinity() on non-SMP systems.

Change-Id: I728d5163bff3fb2bd4a2ea7946d2e57cb0854589
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49346
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R470db120396c95bdcafc48ba357652a43d63da82

5 years agoARM: tegra: power: Fix build error on non-SMP systems
Scott Williams [Fri, 26 Aug 2011 01:39:56 +0000]
ARM: tegra: power: Fix build error on non-SMP systems

Can't use NR_CPUS on non-SMP systems. Just use the maximum.

Change-Id: Ie0d6289c3b8bdaada6335e4670c9f6b5ab2bcc93
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49344
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R58abf556bf542b8cf0ee6dd0f091806235f49623

5 years agoarm: tegra: Increase max irq of system by 64.
Laxman Dewangan [Wed, 24 Aug 2011 13:26:38 +0000]
arm: tegra: Increase max irq of system by 64.

Increasing the maximum irqs of system to +64 from
internel irqs of socs.

bug 822562

Original-Change-Id: Ib032232efd59ea7c1ccaa36b62d1fffcaa2c09b1
Reviewed-on: http://git-master/r/48984
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R7f7869796b99a52466d815412792f0357a902269

5 years agoARM: tegra: timer: Use common chip id functions
Scott Williams [Wed, 24 Aug 2011 20:43:42 +0000]
ARM: tegra: timer: Use common chip id functions

Original-Change-Id: Ibf7a37c0751924f0a8de4932d0d31b6fe6c3c4e8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49049
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rfcfb080975c0f844487b91167fc455882f0cb5f4

5 years agoarm: tegra: add edp limit to debugfs
Joseph Lehrer [Fri, 19 Aug 2011 22:36:13 +0000]
arm: tegra: add edp limit to debugfs

bug 865842

Original-Change-Id: I54dcf3e2e968692746f1d8b17bdf912305f547a2
(cherry picked from commit 5b9dce25485824036f86db093b28a45a3cd86c76)
Reviewed-on: http://git-master/r/48257
Reviewed-by: Joseph Lehrer <jlehrer@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1adb1ca832e0f63f1e5b7e405f4c87c4a8a7aabe

5 years agoarm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values
Mayuresh Kulkarni [Mon, 22 Aug 2011 13:37:25 +0000]
arm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values

The pin-func set by board-xxx-pinmux.c should be one of the 4 possible
values of the pin-func in master pinmux table. Also the safe pin-func
setting should follow the same rule.

If this is not followed then, warnings will be seen whenever a driver
tries to set a pin-func that is not in the master pinmux table. This is
specically seen for the mux values RSVD_X.

The hardware is always programmed with the bit value of setting
(00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table.

For bug 865503

Change-Id: I3933ca0002e099376798cc131690922fefa16868
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48197
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R6d5a11f9f3ab523a2557a512ab85c3ef5f90815a

5 years agoarm: tegra: pinmux: fix a few warnings for Tegra2
Mayuresh Kulkarni [Fri, 19 Aug 2011 13:52:17 +0000]
arm: tegra: pinmux: fix a few warnings for Tegra2

APIs lock_name(), od_name(), ioreset_name() are called from code for
Tegra3 and above. However, their implementation was not taking care
of this. This was causing 3 warnings during Tegra2 builds.

Change-Id: I4ac4d394c68fd1f8bab5938b2af76c8b92d04a64
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48195
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R4e7e7a4ec3cd7b31a2297bdeedccedc8cbcb5a01

5 years agoARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster control
Scott Williams [Tue, 23 Aug 2011 21:23:18 +0000]
ARM: tegra: Use CONFIG_TERGA_CLUSTER_CONTROL for cluster control

Change-Id: I07c389092132e52e2bdd3deab22c10f8e1e6035c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48798
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1e0c9acc87c81f9d0dc394c09d6a7b8b94c48d3f

5 years agoARM: tegra: Add CONFIG_TEGRA_CLUSTER_CONTROL
Scott Williams [Tue, 23 Aug 2011 20:42:44 +0000]
ARM: tegra: Add CONFIG_TEGRA_CLUSTER_CONTROL

Change-Id: I562fb5abaf767572094f3c163a105dc4974a7139
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48797
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb67f65cb0866e66787eddb16533f0928ddcb3ea9

5 years agoARM: tegra: Fix build errors when PM_SLEEP is not selected
Scott Williams [Tue, 23 Aug 2011 22:52:45 +0000]
ARM: tegra: Fix build errors when PM_SLEEP is not selected

Change-Id: I2037be4b1309ac1fe9af0ec3e644e0a1a4924857
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48796
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R0840ee98b17984f73f9a5396ab6f86d4d92b744e

5 years agoARM: tegra: power: Fix premature clock event broadcast mode
Scott Williams [Tue, 23 Aug 2011 18:00:41 +0000]
ARM: tegra: power: Fix premature clock event broadcast mode

Do not switch to clock event broadcast mode until the final CPU
is going into LP2. Switching into broadcast mode on the secondary
CPUs can cause double ticking and/or kernel panics on the primary.

Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48743
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5

5 years agoARM: tegra: Enable CONFIG_TEGRA_EDP_EXACT_FREQ
Diwakar Tundlam [Fri, 19 Aug 2011 02:19:35 +0000]
ARM: tegra: Enable CONFIG_TEGRA_EDP_EXACT_FREQ

Toggle to using exact EDP table frequencies as default

Bug 863761

Original-Change-Id: Idbcbe870ae3266c2e5d5aefad6869632284b052b
Reviewed-on: http://git-master/r/47991
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7c305f4357d5cbb0700176fa37c6adf4fe39a9a1

5 years agoARM: tegra: Avoid timer calibration on slave cpu's.
Krishna Reddy [Fri, 19 Aug 2011 01:55:05 +0000]
ARM: tegra: Avoid timer calibration on slave cpu's.

Use the value calibrated by master cpu.
Bug 843553

Original-Change-Id: I88939f37050873e0633782f6a927ffaf9b8d776d
Reviewed-on: http://git-master/r/47988
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6520764a88346d5ab4a180810636b04ce474f4d7

5 years agoARM: tegra: pm: Do not use ioremap for sys mem
Prashant Gaikwad [Wed, 3 Aug 2011 09:19:20 +0000]
ARM: tegra: pm: Do not use ioremap for sys mem

ARMv6+ architecture does not allow ioremap on system memory.
lp0 is relocated using ioremap on DRAM. If lp0 vector start address
is in system memory then use memblock_reserve and do not relocate.
Else if it is overlapping with carveout/fb then first remove the
carveout/fb using memblock_remove and then use ioremap.

Bug 827199

Reviewed-on: http://git-master/r/43685
(cherry picked from commit 1753408edc65ebfc0d4d203f2be960d49ca747a8)

Original-Change-Id: Ic4abfbc98b43aafb2756cb3e69d0ee178204ec7d
Reviewed-on: http://git-master/r/44717
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re90d5554c301471fd177632887741109318c2c97

5 years agoarm: tegra: pm: Relocate lp0 vector
Prashant Gaikwad [Wed, 3 Aug 2011 09:11:14 +0000]
arm: tegra: pm: Relocate lp0 vector

LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.

Bug 827199

Reviewed-on: http://git-master/r/42113
(cherry picked from commit 9a3993d39599d1637d7c04218e6a634f914e9f91)

Original-Change-Id: If862f6ff61a316c478806b7dc3deff70a2861410
Reviewed-on: http://git-master/r/44716
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R085bc615567c70b7ff3b0ba1aee375fb29a72bfd

5 years agoARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x441/551
Diwakar Tundlam [Mon, 8 Aug 2011 18:55:15 +0000]
ARM: Tegra: cpu: Set G-CPU L2 cache latency to 0x441/551

Bugid 860893

Original-Change-Id: Ia48b5b98917d75fd4fe9cafe595558e6dd17906b
Reviewed-on: http://git-master/r/45883
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd737556e04ed64c42e4fbb7f5477aa8441a00616

5 years agoARM: tegra: Fix warnings when CONFIG_PM_SLEEP is not selected
Scott Williams [Wed, 17 Aug 2011 22:53:11 +0000]
ARM: tegra: Fix warnings when CONFIG_PM_SLEEP is not selected

Change-Id: If06bd6a9030c8b1502c96459eb6657a6bff4b0fa
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47634

Rebase-Id: R2982ec1b130417178376a06bb37f24aaf65ec19f

5 years agomedia: tegra: avp: Clear interrupt registers when AVP starts
Kaz Fukuoka [Thu, 26 May 2011 01:21:32 +0000]
media: tegra: avp: Clear interrupt registers when AVP starts

There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.

This change also removes the workaroud for the bug.

bug 827353
bug 826234

Original-Change-Id: I51546400f0bace67dfcdb23f667c051c060d3983
Reviewed-on: http://git-master/r/33083
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Re8d35d9a62267d2a66f7eb4e754651edafdbb536

5 years agoarm: tegra: pinmux: Fix RSVD search condition.
Jin Park [Fri, 19 Aug 2011 08:11:42 +0000]
arm: tegra: pinmux: Fix RSVD search condition.

There is the potential problem in RSVD search routine, if mux function
index is masked by 0x3.

Original-Change-Id: Ieb823db5a304c0db6e898f29193d32bac3e34c38
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/48093
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Rdcf3a9747fab2f3aace0f7ee4b5b39f5ae497549

5 years agoARM: tegra: power: Don't clip EDP limits to cpufreq tables
Peter Boonstoppel [Tue, 16 Aug 2011 19:01:29 +0000]
ARM: tegra: power: Don't clip EDP limits to cpufreq tables

Always use maximum possible frequency when applying EDP
capping. Toggled through CONFIG_TEGRA_EDP_EXACT_FREQ.

Bug 863761

Original-Change-Id: I327440546991ad4f3abc78100a3a18017f3464b6
Reviewed-on: http://git-master/r/47169
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rdafcd7202975dd85631b4d281012343c5cda08be

5 years agoARM: tegra: power: Wait for power-gate toggle completion
Alex Frid [Tue, 9 Aug 2011 04:02:51 +0000]
ARM: tegra: power: Wait for power-gate toggle completion

Bug 857044

Original-Change-Id: I80c8c2183426fbaa8b7d5316c09709c9de7ea39d
Reviewed-on: http://git-master/r/45970
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd8c46b56d4ca22e05e40c664329d64f7bd6710f7

5 years agoARM: tegra: la: set LA to max for zero bandwidth requests
Michael Frydrych [Mon, 15 Aug 2011 12:23:06 +0000]
ARM: tegra: la: set LA to max for zero bandwidth requests

Requesting to set LA for zero bandwidth would otherwise
cause division by zero exception in LA computation. LA can
safely be set to max in this case.

Original-Change-Id: Id234e2432c7c21b7ab3d13614d0f9fbd82199cde
Reviewed-on: http://git-master/r/47132
Reviewed-by: Michael Frydrych <mfrydrych@nvidia.com>
Tested-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R58676140d46d2b7b2b2c117a03f088944a8f4382

5 years agoARM: tegra: dvfs: Retry rail update
Alex Frid [Sat, 13 Aug 2011 07:38:41 +0000]
ARM: tegra: dvfs: Retry rail update

Since rail voltage change may be limited by from-relationship with
another rail, retry rail update to account for circular dependencies.

Bug 864112

Original-Change-Id: Ie45f656a74eac925ab2383fbe620fad47742d02f
Reviewed-on: http://git-master/r/47233
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R8f9435fb610c27605cdc043ebf2ef13a29377c3d

5 years agoARM: tegra: Added CONFIG_TEGRA_EDP_EXACT_FREQ
Peter Boonstoppel [Tue, 16 Aug 2011 18:58:30 +0000]
ARM: tegra: Added CONFIG_TEGRA_EDP_EXACT_FREQ

Used to toggle using exact EDP table frequencies

Bug 863761

Original-Change-Id: I5e6963504a7b472ff8431fe2e646bee52a26aaec
Reviewed-on: http://git-master/r/47362
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R294e6875dfeb503f5a9880dea15e17cebb7a36de

5 years agoarm: tegra: tsensor: fuse revision corrected
Bitan Biswas [Fri, 12 Aug 2011 09:32:31 +0000]
arm: tegra: tsensor: fuse revision corrected

tsensor functionality is enabled based on fuse revision.
The fuse revision is to be interpreted as an unsigned integer
while it is interpreted as a decimal number. Corrected this
in platform source file.

bug 863460

Original-Change-Id: Iaf9676d559bb7fb3555c7b731aa018f949441c8e
Reviewed-on: http://git-master/r/46901
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R8a85e2ce060dd3110c374b30d0018c7512b22113

5 years agoARM: tegra: power: Support for resetting module
Chris Johnson [Fri, 12 Aug 2011 05:58:17 +0000]
ARM: tegra: power: Support for resetting module

Add support for resetting a module.

Bug 625545

Original-Change-Id: Ibc5e57d73085e85f3d1184d0657d9bc650b28e4e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/46870
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcaa388b315159b1cc69dd29dd03176f4136bd285

5 years agoARM: tegra: power: Separate throttling code
Alex Frid [Wed, 10 Aug 2011 21:42:54 +0000]
ARM: tegra: power: Separate throttling code

Moved tegra CPU throttling algorithm implementation into a separate
file. For now, the same algorithm is used for both Tegra2 and Tegra3
architecture.

Original-Change-Id: I478c32b5adee4c946472129b89615580c10b41e1
Reviewed-on: http://git-master/r/46748
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R2340f78e1d22942022e171044d6b20f260e2d312

5 years agoARM: Tegra: Cardhu: Setting sdmmc drive strengths
naveenk [Fri, 12 Aug 2011 14:16:35 +0000]
ARM: Tegra: Cardhu: Setting sdmmc drive strengths

configuring sdmmc drive strengths as suggested
by HW team based on Characterization results

Bug 799568

Original-Change-Id: Id30505659aefb9c63a24f8baa8296a62723710b4
Reviewed-on: http://git-master/r/46949
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R557938d130efb48eaa6f9e1b584f13505aa200a6

5 years agoARM: tegra: la: remove printf warning
Jon Mayo [Wed, 10 Aug 2011 23:20:48 +0000]
ARM: tegra: la: remove printf warning

arch/arm/mach-tegra/latency_allowance.c:499: warning: format '%4u'
expects type 'unsigned int', but argument 4 has type 'long unsigned int'

Original-Change-Id: Idfea3e60da375bfe903e1a517505c727ecc83d72
Reviewed-on: http://git-master/r/46495
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R8eeb5ccc518d9591fa1a9a521913b17ec28c6b52

5 years agoARM: tegra: power: Update to EDP table
Peter Boonstoppel [Thu, 11 Aug 2011 00:38:44 +0000]
ARM: tegra: power: Update to EDP table

 - updated EDP table for AP30 A02 2.5A to match data from Bug 844268
 - updated EDP cap for single core on AP30 A02 to 1.3Ghz
 - changed EDP table for A01 to match AP30 A02

Original-Change-Id: I1722768f235d63a2f311d082d8126ba071226eb6
Reviewed-on: http://git-master/r/46482
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc98aaffd4568b9ad642696eef5f559d9c7fd7237

5 years agoARM: tegra: la: use lower LA for display clients
Jon Mayo [Wed, 10 Aug 2011 23:16:10 +0000]
ARM: tegra: la: use lower LA for display clients

In order to prevent display underflow until latency allowance scaling is
enabled, use the LA value corresponding to low threshold, instead of max
LA for full FIFO.

Bug 840688

Original-Change-Id: If405e5931b817cdadec0294d487af1a4b921894a
Reviewed-on: http://git-master/r/46342
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: Rca14600452178655a8864b0b7bc7bf66576b8ca1