6 years agoARM:tegra:ardbeg: various senor bringup on TN8
David Wang [Thu, 5 Sep 2013 01:09:07 +0000]
ARM:tegra:ardbeg: various senor bringup on TN8

Modified ardbeg board file to support ov5693,
ov7695 sensors and ad5823 focuser to work on TN8.
Also added matching reguatlor names for
ov5693 and ov7695 in tn8 board power file.

Bug 1349826
Bug 1349914

Change-Id: I8a4268a23d0fe46a290719261fdfbd4f235443e3
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/270941
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoARM: tegra: powergate: Removing the warning message
Chao Xu [Mon, 9 Sep 2013 22:25:23 +0000]
ARM: tegra: powergate: Removing the warning message

for dispB refcount underflow. This is an expected behavior for the
boards with some specific PMUs.

Bug 1357978
Bug 1364243

Change-Id: Ie1ce7c2b770463078655f7b1a94f046fa67cb2ea
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/272165

6 years agovideo: tegra: fb: Set FB smem_start value regardless LPAE setting
Chao Xu [Mon, 9 Sep 2013 22:11:41 +0000]
video: tegra: fb: Set FB smem_start value regardless LPAE setting

This workaround allows FB driver works if FB buffer address is no
more than 32bits, even if LPAE is enabled.

A complete fix is tracked by bug 1356233.

Change-Id: I733c73b4cade88f0dd9399906473bea7b62fff01
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/273313
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Xue Dong <xdong@nvidia.com>

6 years agoARM: tegra12: dvfs: Move GPU Vmin thermal profile
Alex Frid [Thu, 12 Sep 2013 03:47:40 +0000]
ARM: tegra12: dvfs: Move GPU Vmin thermal profile

Moved definition of GPU Vmin thermal profile to GPU cvb dvfs table, so
that different profiles can be defined for different SKUs.

Bug 1273253

Change-Id: Ibb304c5cbbf09f1083bccfd3efc975f78a733aa4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/273479
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra12: dvfs: Enable CPU Vmin thermal profile
Alex Frid [Thu, 12 Sep 2013 03:31:49 +0000]
ARM: tegra12: dvfs: Enable CPU Vmin thermal profile

Change-Id: Ibcc153b28cd9f9d3bebbbd923fce1fa9345cae11
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/273478
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: dvfs: Rename cvb dvfs thermal trips field
Alex Frid [Thu, 12 Sep 2013 00:21:58 +0000]
ARM: tegra: dvfs: Rename cvb dvfs thermal trips field

Renamed cvb dvfs data field therm_trips_table to vmin_trips_table, so
that field designation is clear.

Change-Id: I6a8295b1bebca248960829ed67c32addf1679cca
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/273477
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoiommu/tegra: smmu: Optimize alloc_ptbl
Hiroshi Doyu [Wed, 11 Sep 2013 11:56:28 +0000]
iommu/tegra: smmu: Optimize alloc_ptbl

Without TEGRA_IOMMU_SMMU_LINEAR, zero initialized page table is
enough. Optimize the way to zero initialize.

Bug 1290869

Change-Id: Iaf71157c999663bc6216a9d086d2ccb093add1e6
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/273152
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoiommu/tegra: smmu: Remove page validataion
Hiroshi Doyu [Wed, 11 Sep 2013 11:43:59 +0000]
iommu/tegra: smmu: Remove page validataion

This page is returned from alloc_ptbl() and it's ensured that page is
valid at this point. This code is inside of loop for map_sg/map_pages
so that this affects the perf.

Bug 1290869

Change-Id: I2b2165851a320496d650d6335127168f02882bed
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/273151
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoiommu/tegra: smmu: Optimize smmu_iommu_map_sg()
Hiroshi Doyu [Wed, 11 Sep 2013 11:39:42 +0000]
iommu/tegra: smmu: Optimize smmu_iommu_map_sg()

Avoid nested loop in it for the better perf.

Bug 1290869

Change-Id: Id87a7233f1118dfc76c130bc7f3c7ccaad5ec507
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/273150
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra: power: Disable CPU sensors for cluster switch
Alex Frid [Wed, 11 Sep 2013 05:12:27 +0000]
ARM: tegra: power: Disable CPU sensors for cluster switch

Disabled soctherm CPU sensors before switch to LP cluster, if CRAIL
is controlled by s/w. Re-enabled sensors respectively after switch
back to G cluster. This is done to avoid bogus temperature reading
during cluster switch when s/w is turning CPU rail on/off.

Bug 1351735

Change-Id: Ia4864cdbfa622ca42533fe717a358a89dd262bc0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/272916
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: power: Fix suspend initialization
Alex Frid [Wed, 4 Sep 2013 19:43:29 +0000]
ARM: tegra: power: Fix suspend initialization

Added initialization for crail suspend platform data entries missed
by commit 14ddff697632b88f1f89aa2c62f5a053e37c7e27.

Moved CL-DVFS initialization to regulator init call (from fixed
regulator init) to setup dfll bypass call-backs before suspend
initialization.

Bug 1351735

Change-Id: Ia4bbf260873630db40e7fdf0966cd319fe265a4f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270294
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoiommu/tegra: smmu: Rename "nents" to "npages"
Hiroshi Doyu [Wed, 11 Sep 2013 11:02:24 +0000]
iommu/tegra: smmu: Rename "nents" to "npages"

The parameter "nents" is confusing. Actually this is number of pages,
"npages". Rename this for the following changes in map_sg().

Bug 1290869

Change-Id: If9ff6740e4f3954f9742d9fe4c4039ca601970e1
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/273149
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agomedia:video:tegra: Add Fuse ID read for IMX132.
Amey Asgaonkar [Fri, 26 Jul 2013 23:08:14 +0000]
media:video:tegra: Add Fuse ID read for IMX132.

Adds support for reading fuse ids for IMX132 sensor.

Bug 1307361

Change-Id: I7b750a91d3ead5fac383e85df013b78d7fe4c6a2
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-on: http://git-master/r/254573
(cherry picked from commit 77b2dc05d8d051659140343531d9ce34e01efeea)
Reviewed-on: http://git-master/r/272670
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agonet: mhi mhi_dgram Fix warning messages
Philip Rakity [Tue, 9 Jul 2013 09:33:39 +0000]
net: mhi  mhi_dgram  Fix warning messages

printk arguments not in correct order
___func__ is the char *

Change-Id: I7c39e64dcb20026ac015942380dbd523f198cd5e
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/246607
(cherry picked from commit d2ba6bacbacfcd94b54785c9a8afb4136003805d)
(cherry picked from commit 7bb3b61ce23ca715e3847101c7defba6278b17c8)
(cherry picked from commit f9f6b595db1fd0e33347a447e717a9d7aae82570)
Reviewed-on: http://git-master/r/269574
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoinput: misc: Fix unused compiler warning
Philip Rakity [Fri, 5 Jul 2013 12:09:41 +0000]
input: misc:  Fix unused compiler warning

use direct functions rather than read / write wrappers
removes compiler warning about unused code.

Change-Id: I95682dcd24ed2e27eed6022352d6829cd29e2317
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/245374
(cherry picked from commit 86d030622f296bf5667dd3967ebc7cf6c2351d01)
(cherry picked from commit 8f9e2896a2bc4f04b44f954ce1da235611f20deb)
Reviewed-on: http://git-master/r/271478
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoxhci-tegra fix warnings on unused function
Philip Rakity [Mon, 9 Sep 2013 16:29:45 +0000]
xhci-tegra fix warnings on unused function

remove unused function warning for save_ctle_context()
the function IS used for T12x but not T11x

/nvidia/DEV_KERNEL/kernel/drivers/usb/host/xhci-tegra.c:1768:13:
warning: 'save_ctle_context' defined but not used [-Wunused-function]

Change-Id: I22aa17fcb4afca9db1356f3017b86d09c28c1814
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/272034
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agohwmon: ina230: fix negative power readings
Deepak Nibade [Mon, 26 Aug 2013 13:47:33 +0000]
hwmon: ina230: fix negative power readings

- show_power2 api calculates power using shunt voltage
- if shunt voltage is negative, power and current readings
  are also calculated negative
- fix this by taking absolute value of shunt voltage

Bug 1353426

Change-Id: I10deb33a0297af52da88385b105edd9bc2649d94
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/266129
(cherry picked from commit bdfa16243edcac9b07bbbe7133374494f4ef3b6f)
Reviewed-on: http://git-master/r/273608
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoarm: tegra12: spi: Set RX_TAP_DELAY depending on speed
Shardar Shariff Md [Wed, 11 Sep 2013 13:04:27 +0000]
arm: tegra12: spi: Set RX_TAP_DELAY depending on speed

Set rx_tap_delay to 10 when speed > 35MHz and board
specific rx_clk_tap_delay data is zero.

Bug 1245131

Change-Id: Ie38469dac8d80737da5e45b9022ef1276b7fc883
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/273189
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agousb: pmc: ensure pmc base is not null
Krishna Yarlagadda [Wed, 11 Sep 2013 12:48:08 +0000]
usb: pmc: ensure pmc base is not null

If tracking data is called before pmc init is set, it
would result in kernel panic. Fill pmc base before accessing
pmc registers.

Bug 1334159

Change-Id: I0bd80cef9cdd873792a3d6ece49a56d4b11de608
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/273183
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Tested-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoARM: tegra: pinmux-t124: Change drive for UART2/3
Pradeep Goudagunta [Tue, 10 Sep 2013 09:47:44 +0000]
ARM: tegra: pinmux-t124: Change drive for UART2/3

Change default drive for UART2 and UART3 CTRL pads as per
HW suggestion.

Bug 1346563

Change-Id: I2f5d376e17955d91407fe7f9d8e67e88adbc6641
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/272483
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: dma-mapping: Fix build warning
Hiroshi Doyu [Thu, 12 Sep 2013 06:36:11 +0000]
ARM: dma-mapping: Fix build warning

Inconsistent type for set_dma_ops()

Change-Id: I78ebecaa335cafe627dc673cf54590d3354a7dc8
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/273536
Reviewed-by: Vandana Salve <vsalve@nvidia.com>

6 years agoARM: tegra12: clock: set/clear XUSB pll pad iddq
Leo He [Wed, 28 Aug 2013 13:17:51 +0000]
ARM: tegra12: clock: set/clear XUSB pll pad iddq

Set XUSB pll pad override and iddq when disable pll clock.
Clear XUSB pll pad override and iddq when enable pll clock.

Bug 1350181

Change-Id: Iefe1dba52d861ad1d2892e6cdfa89b5b53825cb8
Signed-off-by: Leo He <leoh@nvidia.com>
Reviewed-on: http://git-master/r/267371
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

6 years agoregulator: palmas: fix voltage configuration with LDO8
Laxman Dewangan [Wed, 11 Sep 2013 11:04:03 +0000]
regulator: palmas: fix voltage configuration with LDO8

When LDO8 is in tracking mode, the voltage output is
Vout = 450000 + selector * 25000

and when it is non-tracking mode then the voltage output is
Vout = 900000 + selector * 50000

Based on the tracking mode of the LDO8, setting register for voltage.

bug 1366215

Change-Id: I44080a5fdd3b0bb2828f550477592cdd6d556c9f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/273055
GVS: Gerrit_Virtual_Submit
Tested-by: Terry Wang <terwang@nvidia.com>

6 years agoarm: tegra: tn8: Add regulator client for as364x
Hayden Du [Thu, 12 Sep 2013 06:02:10 +0000]
arm: tegra: tn8: Add regulator client for as364x

bug 1361907

Change-Id: I8977349516040e02f652a51babd0d435a15044c9
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/273522
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agomedia: platform: tegra: IMX135: 1920x1080 settings
Kushal Shah [Wed, 11 Sep 2013 20:17:20 +0000]
media: platform: tegra: IMX135: 1920x1080 settings

Set correct clock, size, timing and gain settings value
in various registers for 1920x1080 mode.

Bug 1364810

Change-Id: I17b2187dc06902fb9774666b63784c713ba38f2a
Signed-off-by: Kushal Shah <kshah@nvidia.com>
Reviewed-on: http://git-master/r/273325
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarm: tegra: tn8: set vdd_rtc voltage to 0.9v
Hunk Lin [Wed, 11 Sep 2013 03:32:34 +0000]
arm: tegra: tn8: set vdd_rtc voltage to 0.9v

LDO8 tracking is disabled in TN8, so set it to always 0.9v per HW.

Bug 1292907

Change-Id: I5bb4eccf93bab2f175b9a911df014316ad501aac
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/272879
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoxhci: tegra: support hsic pretend connect
JC Kuo [Mon, 12 Aug 2013 07:54:35 +0000]
xhci: tegra: support hsic pretend connect

When HSIC port is being used to connect some HSIC device which gets
powered-on before Tegra XUSB does, the HSIC CONNECT signal sent by
device is likely missed. In addition, HSIC device isn't likely to resend
CONNECT.
Tegra XUSB supports "hsic pretend connect" which means firmware can
manually direct HSIC ports from "RxDetect" to "Polling". We added one
firmware mailbox message for this purpose. That allows driver to makeup
for the missed CONNECT.

bug 1341852

Change-Id: Ibf87b4790ce587f37f4f46cb660c25782562cccb
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/267195
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

6 years agoARM: tegra: ardbeg: Pass vcore limits in plat data
Naveen Kumar Arepalli [Wed, 11 Sep 2013 13:25:10 +0000]
ARM: tegra: ardbeg: Pass vcore limits in plat data

Pass boot core voltage, nominal core voltage, min vcore override
voltage limits through platform data for sdmmc1/3/4.

Bug 1344651
Bug 1344649
Bug 1340258

Change-Id: Ibb234f03f0c750c3ba645280ca2d72485959a74e
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/273195
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agoRM: tegra: Enable TEGRA_VDD_CORE_OVERRIDE
Naveen Kumar Arepalli [Wed, 11 Sep 2013 13:09:42 +0000]
RM: tegra: Enable TEGRA_VDD_CORE_OVERRIDE

Select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
is enabled.

SDMMC Driver uses dvfs API's to set override voltages.
Hence TEGRA_VDD_CORE_OVERRIDE should be enabled.

Bug 1344651
Bug 1344649
Bug 1340258

Change-Id: Ibe4d3d1eb0a92abde98590436bc87f4a7bb2ed76
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/273194
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

6 years agodma: tegra: De-init channel isr_handler when releasing
Chaitanya Bandi [Wed, 11 Sep 2013 08:16:18 +0000]
dma: tegra: De-init channel isr_handler when releasing

Set the isr_handler to NULL while releasing a channel

Bug 1354798

Change-Id: Idad5b3f257d1613b7a5de1e47e684ed0457fa093
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/272992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agomedia:platform:tegra:fuse id for ar0261
Amey Asgaonkar [Fri, 30 Aug 2013 02:20:44 +0000]
media:platform:tegra:fuse id for ar0261

adds code for reading fuse id for ar0261.

Bug 1330898

Change-Id: Iad27adafe34e1d0ed6165b1f8ae9c7d257beef11
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-on: http://git-master/r/268282
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: clock: Add PERIPH_ON_APB to MIPI-CAL
Kaz Fukuoka [Wed, 11 Sep 2013 18:06:42 +0000]
ARM: tegra: clock: Add PERIPH_ON_APB to MIPI-CAL

bug 1363948

Change-Id: I8df09b8d121358a56255e32147cbc6345f69151b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/273275
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra12: clock: Add PERIPH_ON_APB to SATA
Kaz Fukuoka [Wed, 11 Sep 2013 17:41:50 +0000]
ARM: tegra12: clock: Add PERIPH_ON_APB to SATA

Ported from Tegar30 Change-Id: I12be16dbc2614224ba852216a645d0f84c795334

bug 1363948

Change-Id: If9e59db37969431f5c1f0a51da4c8fe82a22eb9c
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/273269
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agovideo: tegra: dc: Fix CRC read on one shot mode
Michael Frydrych [Tue, 10 Sep 2013 12:44:33 +0000]
video: tegra: dc: Fix CRC read on one shot mode

Wait for frame_end interrupt at most once per flip
in one shot mode, even if CRC is read multiple times
after the flip.

bug 1366106

Change-Id: Ie872e81e85bda500caab48728b7cd4c3b7db535f
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-on: http://git-master/r/272580
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoarm: tegra12: Add CPU EDP support for SKU 1
Diwakar Tundlam [Tue, 10 Sep 2013 22:00:35 +0000]
arm: tegra12: Add CPU EDP support for SKU 1

Bug 1342499

Change-Id: I4913e9981df6c3222af94d3e415910bb82434ece
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/272740
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoALSA: HDA: wait for IRQ handlers
Sang-Hun Lee [Wed, 28 Aug 2013 21:11:10 +0000]
ALSA: HDA: wait for IRQ handlers

Problem description:
 - Even after disabling interrupts on the module, interrupt handlers
   could be running on other CPUs.

Fix description:
 - When disabling interrupts, also wait for any interrupt handler
   to finish as well

Bug 1353286

Change-Id: I59bde67c51341cf52ca5f7f7a31a45d9f9887666
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/267543
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

6 years agomedia:video:tegra:as364x deafult max torch current
David Wang [Fri, 16 Aug 2013 01:31:49 +0000]
media:video:tegra:as364x deafult max torch current

Added deafult max torch current to the as364x config
and limit calculation based on max total current for
2 leds.

bug 1346615

Change-Id: I006f041728b74cc2171bebb34532af4d40d94f87
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/270955
Reviewed-by: Michael Stewart <mstewart@nvidia.com>
Reviewed-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoarm:mach-tegra:ardbeg max torch current for as364x
David Wang [Fri, 16 Aug 2013 01:39:12 +0000]
arm:mach-tegra:ardbeg max torch current for as364x

Added max torch current for as364x pdata in the
ardbeg sensor board file.

bug 1346615

Change-Id: If412fbecf61ba0f719ad7db94693042a7ee60d95
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/270954
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoregulator: palmas: pass regulator voltage through descriptor
Laxman Dewangan [Wed, 11 Sep 2013 09:22:59 +0000]
regulator: palmas: pass regulator voltage through descriptor

In place of adding callback to get the rail voltage of fixed rail like
extreg, chargepmup, pass the regulator voltage through descriptor.

Change-Id: I028344f363584a66c8bb46dadacb53f35b51a210
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/273023
GVS: Gerrit_Virtual_Submit

6 years agoregulator: core: provide fixed voltage in desc for single voltage rail
Laxman Dewangan [Wed, 11 Sep 2013 09:18:41 +0000]
regulator: core: provide fixed voltage in desc for single voltage rail

If given rail has the single voltage (n_voltages = 1) then provide the
rail voltage through regulator descriptor so that core can use this
value for finding voltage.

This will avoid the implementation of the callback for get_voltage() or
list_voltage() callback on regulator driver.

Change-Id: Ia148194cde37df2e5b1447e8c550072d8738af71
signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/273021
GVS: Gerrit_Virtual_Submit

6 years agovideo: tegra: host: Use new MC flush API
Terje Bergstrom [Mon, 9 Sep 2013 10:52:25 +0000]
video: tegra: host: Use new MC flush API

Use new tegra_mc_flush() and tegra_mc_flush_done() to have a better
control on which MC clients are reset.

Bug 1355069

Change-Id: I759cdecbdf9e76254bcc4cd6441bbb464d0ea45b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272009
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra: New tegra_mc_flush() API
Terje Bergstrom [Mon, 9 Sep 2013 10:51:01 +0000]
ARM: tegra: New tegra_mc_flush() API

Introduce new tegra_mc_flush() and tegra_mc_flush_done() calls. They
give better granilarity on which client is flushed than
tegra_powergate_mc_flush() and tegra_powergate_mc_flush_done().

Bug 1355069

Change-Id: I1723238f0b25809cabef10a3fa6a063736d92a2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272008
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Add ISPB hotreset on powergate
Terje Bergstrom [Mon, 9 Sep 2013 08:37:13 +0000]
video: tegra: host: Add ISPB hotreset on powergate

ISPB was not set to hotreset when power gating.

Bug 1355069

Change-Id: Ibdc53f4e9dea399e29660d75d361ab09359d96cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272006
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Add VI reset sequence
Terje Bergstrom [Mon, 9 Sep 2013 07:18:07 +0000]
video: tegra: host: Add VI reset sequence

We do not reset VI from CAR, but instead only reset its MCCIF.

Bug 1355069

Change-Id: I152fdb62d3b0b82731634ed3f891ee4a7f085e0f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271961
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Alloc iomem before module init
Terje Bergstrom [Mon, 9 Sep 2013 07:46:28 +0000]
video: tegra: host: Alloc iomem before module init

Allocate and request IOMEM resources for all clients before calling
nvhost_module_init(). Also moves setting of callbacks to the SoC
specific file.

Bug 1355069

Change-Id: Ic7483dba969be8e5e985d5abbba11393afdc2a2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271960
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Add reset override
Terje Bergstrom [Mon, 9 Sep 2013 06:51:36 +0000]
video: tegra: host: Add reset override

Add a reset callback that drivers can use for overriding the default
reset sequence.

Bug 1355069

Change-Id: I789f28978d60e20e2244251e395d665da098c769
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Add register access to vi.1
Terje Bergstrom [Fri, 6 Sep 2013 10:16:18 +0000]
video: tegra: host: Add register access to vi.1

Tegra124 has one VI, but we have two channels for it, vi and vi.1. We
do that by creating a platform device vi.1. The aperture of VI needs
to be accessible from both channels.

Bug 1346075
Bug 1355069

Change-Id: I555244f14488551770f037277f4a8c267fb9aa69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271510
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agovideo: tegra: host: Make second ISP a real device
Terje Bergstrom [Thu, 5 Sep 2013 13:15:36 +0000]
video: tegra: host: Make second ISP a real device

Second ISP is actually a separate ISP unit, not a part of first ISP.
Reflect that in device setup.

Bug 1346075
Bug 1355069

Change-Id: I5ef6c1c50b6114b97942a85ab438e49da19fce47
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271509
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoregulator: max77660: fix compile warnings
Philip Rakity [Mon, 22 Jul 2013 10:11:20 +0000]
regulator: max77660: fix compile warnings

Change-Id: Ifd2202d642c8d8c7e29c9f8cdbd1a3ace03d54ac
Signed-off-by: Philip Rakity <prakity@nvidia.com>
(cherry picked from commit fde0f5498800b09a13b3f50d92a025a24459a991)
Reviewed-on: http://git-master/r/271470
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agonet: mhi: Fix compiler warnings
Philip Rakity [Fri, 5 Jul 2013 10:08:51 +0000]
net: mhi:  Fix compiler warnings

Change-Id: Ib862e0c63309b5fb57636a413747e414bca4cda4
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/245336
(cherry picked from commit 3bcc5973b22bcba4a14c1ba4f75f60969c867af4)
(cherry picked from commit 12ca14abb53cb653583149add13681b0133c3e90)
(cherry picked from commit 063da7274c54ccf9418eddceff4cb88c8bb6368c)
Reviewed-on: http://git-master/r/269575
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agousb: hub: enable autosuspend for all devices
Krishna Yarlagadda [Fri, 6 Sep 2013 13:47:18 +0000]
usb: hub: enable autosuspend for all devices

enable autosuspend for all the devices enumerated to
save power. If device is wakeup capable and inactive it
will suspend and no need to manually set it.

Bug 1324116

Change-Id: Ic53e4d49ededa68626e16c73d2e4babb2c84e5b4
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/271522
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoarm: tegra: spi: fix rx_tap_delay
Shardar Shariff Md [Fri, 6 Sep 2013 11:11:15 +0000]
arm: tegra: spi: fix rx_tap_delay

Instead on using rx_tap_delay value, tx_tap_delay value
is passed to SPI_RX_TAP_DELAY macro resulting in
undesired value in command2 reg.

Change-Id: I4592e98b240a7d23a81507bddf80e81008f73a7d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/271475
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: tegra: spi: Make rx_tap_delay = tx_tap_delay
Shardar Shariff Md [Tue, 10 Sep 2013 06:06:31 +0000]
arm: tegra: spi: Make rx_tap_delay = tx_tap_delay

rx_tap_delay is not being used in spi tegra driver
instead tx_tap_delay been used in place of rx_tap_delay
Making rx_tap_delay equal to tx_tap_delay to avoid any
issues when fixing rx_tap_delay issue

Change-Id: I8a06766fc217a8a2bd46ab676d579ec56ff3e22d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/272341
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agousb: xhci: set tracking data using pmc api
Krishna Yarlagadda [Thu, 5 Sep 2013 17:28:19 +0000]
usb: xhci: set tracking data using pmc api

set tracking data using pmc api for snps when there is
atleast one snps port in use.

Bug 1334159

Change-Id: Id15f31ba487d8ad07485509002392821b99bf8f8
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270910
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agousb: snps: move tracking data to pmc
Krishna Yarlagadda [Thu, 5 Sep 2013 17:25:34 +0000]
usb: snps: move tracking data to pmc

move tracking data api to pmc code and update
using thsi api

Bug 1334159

Change-Id: Iaf9172545749c558716e94c49fb1e57587a0d25b
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270909
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoARM: tn8: SMPS10-OUT1 source the sw regulator for HDMI
Laxman Dewangan [Wed, 11 Sep 2013 07:45:40 +0000]
ARM: tn8: SMPS10-OUT1 source the sw regulator for HDMI

HDMI switch regulator is sourced by SMPS-OUT1. Registering
SMPS10-OUT1 and correcting supply of HDMI switch regulator.

bug 1364346

Change-Id: I62703d60d0e4f544dbc3c7c55ea6f3ea8652c459
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272967
Tested-by: Hayden Du <haydend@nvidia.com>

6 years agoARM: tegra: Ardbeg: Changing LDO8 LP0 voltage
Terry Wang [Wed, 4 Sep 2013 11:53:42 +0000]
ARM: tegra: Ardbeg: Changing LDO8 LP0 voltage

Changing ldo8 LP0 voltage from 1V to 0.9V for
Ardbeg with TI PMIC module E1735.

Bug 1317293

Change-Id: I3766ee888156591bca5bb6816409a43f91b4ec52
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/264216
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tn8: register all fixed regulator as part of arch init
Laxman Dewangan [Tue, 10 Sep 2013 13:26:53 +0000]
ARM: tn8: register all fixed regulator as part of arch init

In place of doing all fixed regulator registration on sys_initcall_sync(),
registering it during the tn8 drivers initialisation.

Change-Id: I1d3cd353430b893687157d414f9c8cd5e584e69c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272608

6 years agoARM: move the FIXED_REG macro definition to pmu board files.
Laxman Dewangan [Tue, 10 Sep 2013 13:25:30 +0000]
ARM: move the FIXED_REG macro definition to pmu board files.

This will avoid the duplication of the macro definition across
the power file.

Change-Id: I26573f4f0be77274a7385528ec69256b9252ff22
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272607

6 years agoregulator: fixed: add provision to register driver little late
Laxman Dewangan [Tue, 10 Sep 2013 13:20:59 +0000]
regulator: fixed: add provision to register driver little late

Some of i2c based devices register themself as the GPIO. Deferring
the fixed regulator little bit late by using subsys_initcall_sync
level of initialisation to have fixed regulator registration after
the GPIO initialisation so that driver can get all the GPIOs.

Change-Id: I21c41e13242d37dbae3e9b9164c3600d2ac02c55
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272606

6 years agoregulator: palmas: remove sleep_mode callback
Laxman Dewangan [Tue, 10 Sep 2013 07:00:58 +0000]
regulator: palmas: remove sleep_mode callback

The sleep mode of the rails are configured through the mode-sleep
property and hence providing the sleep mode callbacks duplicate the
same. Hence removing the sleep mode callbacks.

Change-Id: I9f174813dd03041ed020a9e8c5090766efbfd5fc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272351
Reviewed-by: Automatic_Commit_Validation_User

6 years agoRevert "vide: tegra: host: fix nvmap handle leak"
Krishna Reddy [Wed, 11 Sep 2013 03:23:02 +0000]
Revert "vide: tegra: host: fix nvmap handle leak"

This reverts commit 818bd872f47e2ad5088406a101d13e1a42ff20b8.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Change-Id: I82c7968acb0543db4e4fcc0618043aae6f37bf5f
Reviewed-on: http://git-master/r/272872
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agomedia: platform: tegra: IMX135: Add preview mode
Frank Chen [Fri, 6 Sep 2013 22:26:32 +0000]
media: platform: tegra: IMX135: Add preview mode

Add 2104x1560 HDR preview mode

Bug 1359962

Change-Id: Iec82164e38b06addb18eb6f4844ea111971a8dc9
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/272247
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoARM: tegra12: dvfs: update gpu table data
Prashant Malani [Wed, 11 Sep 2013 01:04:21 +0000]
ARM: tegra12: dvfs: update gpu table data

Incorporate latest SiVal data from 09/10/13.

Bug 1352610

Change-Id: I73d20a3d7f0be7d2acf22a5eccec98dbfb43da6f
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/272846
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

6 years agomisc: tegra-baseband: enable auto PM for Bruce
Vinayak Pane [Wed, 28 Aug 2013 01:16:32 +0000]
misc: tegra-baseband: enable auto PM for Bruce

Enable auto PM functionality for Bruce modem.

Change-Id: Ida7555691c198e1ef13ddbdfff2d39f32648414a
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/270445
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoARM: Tegra12: Clocks: Update CPU dvfs table
Krishna Sitaraman [Thu, 5 Sep 2013 18:34:39 +0000]
ARM: Tegra12: Clocks: Update CPU dvfs table

Update CPU dvfs table with first cut of post silicon parameters and
SKU information.

Bug 1342499

Change-Id: I2737d4635c59b9361fc07bfeb6b4b4b1998bc062
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/270939
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: Tegra12: Clocks: Decode SKU information for clocks
Krishna Sitaraman [Thu, 5 Sep 2013 18:20:01 +0000]
ARM: Tegra12: Clocks: Decode SKU information for clocks

Update the speedo and procees ids for cpu to reflect the
appropriate SKU.

Bug 1342499

Change-Id: I79ec4ef57b8f8af27469900ac42f0a04cb3e3a69
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/270933
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Enable PLLE spread spectrum
Kaz Fukuoka [Tue, 10 Sep 2013 18:17:52 +0000]
ARM: tegra12: clock: Enable PLLE spread spectrum

bug 1361458
bug 1346041

Change-Id: I79057b2437ceab44e7969913c0d449d349852840
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/272669
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: loki: enable cl-dvfs support
siddardha naraharisetti [Tue, 10 Sep 2013 02:37:06 +0000]
arm: tegra: loki: enable cl-dvfs support

Added platform data to enable cl-dvfs on loki

Bug 1363892

Change-Id: I5c1ab23bd7a72570fdc693747b0d1ed572464f51
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/272696
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra12: clock: Add host1x shared bus
Alex Frid [Mon, 9 Sep 2013 19:48:07 +0000]
ARM: tegra12: clock: Add host1x shared bus

Ported from Tegra14:
commit fc86a5f24dbb2ee59fa8a43975b8a7915fc69c6b
commit 0120b418704b6152c30b05de3689a415bad34d23
commit 8e7c3690ea540f4371ca0df8fdeb9852365ec499
commit 5003bde3cbec22f14d94af11dadf41af8de60307

Change-Id: I1e9e04496a0ba550bde2fe105583c1486c0d4837
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/272121
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarch: config: tegra enable pcie support
Anand Bhatia [Wed, 4 Sep 2013 18:38:54 +0000]
arch: config: tegra enable pcie support

Enabled config options TEGRA_PCI, PCIEPORTBUS, PCIAER,
PCIEASPM, PCI_MSI.

Change-Id: I8be6992aa5c825244910363392b489f6fa2c646d
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/270225
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kiran Kasamsetty <kkasamsetty@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

6 years agoARM: tegra12: dvfs: Update GPU tables
Prashant Malani [Fri, 30 Aug 2013 23:39:01 +0000]
ARM: tegra12: dvfs: Update GPU tables

Update GPU tables based on latest SiVal data,
as of 08/30/2013.

Bug 1352610

Change-Id: Iebadfa658df8eac24beec4f61cae0ba8a9db8ad5
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/271606
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

6 years agoARM: tegra12: clock: Add AHB/APB shared buses chain
Kaz Fukuoka [Sat, 31 Aug 2013 00:53:46 +0000]
ARM: tegra12: clock: Add AHB/APB shared buses chain

So far, only top most tegra system bus SBUS was exposed as shared bus
by tegra clock framework. All system, AHB, APB clock users requested
directly SBUS rate, and SCLK:HCLK:PCLK rate ratios were fixed at 1:1:2.

This commit added AHB/APB shared buses chain on Tegra12: AHB shared
bus is a shared user of SBUs, and APB shared bus is a shared user of
AHB, respectively.

USB shared users are moved from SBUS to AHB, and SBC shared users are
moved from SBUS to APB. All other SBUS shared users are still children
of the top most SBUS. All "leaves" users in the chain are protected
with cross-bus mutex to avoid races when different segments of the
chain are updated concurrently.

The bus clocks ratios are now dynamically changed based in the rates
requested by the users of each bus. There are, however, limitations on
scaling SCLK:HCLK:PCLK dividers:
(A) H/w limitation: if SCLK >= 60MHz, must have SCLK:PCLK >= 2
(B) S/w policy limitation, in addition to (A): if any APB bus shared
user request is enabled, set HCLK:PCLK >= 2
Limitation (B) is necessary, since otherwise we can not guarantee safe
transition from HCLK:PCLK = 1:1 below 60MHz to HCLK rate above 60MHz
without under-clocking APB user.

When SBUS is throttled by thermal or EDP manager, AHB and APB buses
will be throttled as well to satisfy limitations (A) and (B).

When SBUS rate is fixed via debugfs override user, bus dividers are
also fixed as SCLK:HCLK:PCLK = 1:1:2

(Note for Tegra12: The limitation descried above may have been relaxed
on Tegra12. This issue has to be visited again once the new limitation
is clarified.)

Ported from Tegra14 Change-Id: I8d2999aa8399f86c592ee9b5ee5c66aa0d036c93

Change-Id: Idab839cd227ff9f97db2471c9168f07b6383f653
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/268796
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarm:tegra:loki: enable dynamic VDD_CPU EDP management
siddardha naraharisetti [Tue, 10 Sep 2013 01:30:39 +0000]
arm:tegra:loki: enable dynamic VDD_CPU EDP management

Bug 1365048

Change-Id: I83e58e3386c5ac82e1c19ddfd212af6990957c5c
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/272263
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agotegra: hdmi: add hdmi_audio capability exposure via sysfs
Emma Yan [Wed, 10 Apr 2013 08:10:27 +0000]
tegra: hdmi: add hdmi_audio capability exposure via sysfs

Add checking of the CEA extension bit 6 of byte #3 and expose this
information for userspace to set audio path properly.

Bug 1261178

(cherry-picked from commit 7cb4be8a47081a1468faa29509475eed462fb671)
Reviewed-on: http://git-master/r/218151
Change-Id: Id2780f735da13c7292f269d7ddd9a87b3d09d0d6
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271954
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agovideo: fbmon: added HDMI_Video_Format condition checking
Emma Yan [Tue, 3 Sep 2013 11:38:59 +0000]
video: fbmon: added HDMI_Video_Format condition checking

Bug 1357380

Change-Id: I4b10c31b1c5124539b648764cfae8b17b5764f0a
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271339
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/271896
GVS: Gerrit_Virtual_Submit

6 years agousb: pmc: set utmip tracking data with snps
Krishna Yarlagadda [Thu, 5 Sep 2013 17:18:53 +0000]
usb: pmc: set utmip tracking data with snps

provide api to read tracking data from snps register space

Bug 1334159

Change-Id: Ieb46f178226678295ce5ec03701209b11422bf43
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270908
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoUSB: tegra: reinit hw fixes upon phy_on
Suresh Mangipudi [Thu, 5 Sep 2013 09:40:40 +0000]
USB: tegra: reinit hw fixes upon phy_on

H/W fixes have to be reinitialized after the tegra resumes from LP0.
TXFILL_TUNING needs to be programmed properly for resume from LP0 and
Non LP0 cases.

Bug 1347167

Change-Id: I91bd87bae31988ccf0c36f372ac5b1ca1f767557
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/270703
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoARM: tegra: Rename defconfig for vcm30_t124.
Ashwin Joshi [Tue, 10 Sep 2013 07:30:12 +0000]
ARM: tegra: Rename defconfig for vcm30_t124.

Renamed defconfig for vcm30_t124 from:

arch/arm/configs/tegra12_vcm30_t124_defconfig

to:

arch/arm/configs/tegra_vcm30-t124_gnu_linux_defconfig

Bug 1330469
Bug 1319925
Bug 1365252

Change-Id: I16a6b15ddf42ca80041b191f5fe7c7bb9d3105a4
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/272375
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agovideo: tegra: dsi: Make phy warning verbose
Animesh Kishore [Fri, 6 Sep 2013 09:00:17 +0000]
video: tegra: dsi: Make phy warning verbose

Increase verboseness of phy timing warnings.

Bug 1357180

Change-Id: I58577cf4cbab765f23a9edae793e031fbec38a55
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/271398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: tegra: ardbeg: Fix sharp 25x16 panel timings
Animesh Kishore [Fri, 6 Sep 2013 08:59:32 +0000]
arm: tegra: ardbeg: Fix sharp 25x16 panel timings

Bug 1357180

Change-Id: If21ef99eb89e34b76ad8d22bd6c1bfb0003bc5e4
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/271397
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: pinmux: Add drive pinmux for I2Cs in T12x
Chaitanya Bandi [Thu, 29 Aug 2013 10:24:05 +0000]
ARM: tegra: pinmux: Add drive pinmux for I2Cs in T12x

Added drive pinmux settings for all I2Cs in T12x

Bug 1347466

Change-Id: Iaeff4439f92ca2bbfb8b317758e11626da73ac5e
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/267905
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agovideo: tegra: host: Remove DEVICE_UNKNOWN
Arto Merilainen [Mon, 9 Sep 2013 11:23:14 +0000]
video: tegra: host: Remove DEVICE_UNKNOWN

nvhost scale profiles informed by DEVICE_UNKNOWN that the device
has not received idle/busy events since the last probe. This case
has never been used.

This patch replaces DEVICE_UNKNOWN by DEVICE_IDLE (on boot) and
keeps the current status untouched if nothing has changed.

Change-Id: I021d6ebf788ad9532cd25370ba30af32145aa148
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/272013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agovideo: tegra: host: Fix devfreq profiles
Arto Merilainen [Mon, 9 Sep 2013 11:12:58 +0000]
video: tegra: host: Fix devfreq profiles

Devfreq profiles did not inform the busyness correctly for the device
profiles. This patch adds the missing code to copy the information
correctly for the profile

Change-Id: I8603f12657be6e1723c309c5c3cf37555b377f2e
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/272012
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agovideo: tegra: nvmap: fix warnings from nvmap_free_sg_table
Krishna Reddy [Mon, 9 Sep 2013 22:15:25 +0000]
video: tegra: nvmap: fix warnings from nvmap_free_sg_table

remove checks for validity of ref and ref->handle as ref memory
may not exist during sgt free.

Change-Id: I07f075c25ec1702a3ea9dbead83ac20b54094b9c
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272162
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agovideo: tegra: gk20a: remove pmu debugfs node
Prashant Malani [Tue, 10 Sep 2013 01:06:12 +0000]
video: tegra: gk20a: remove pmu debugfs node

PMU debugfs node isn't required. The load value
is already exposed by gk20a nvhost sysfs node,
and the elpg_stats field is currently empty.

It's better to just remove the node and have all
relevant entries in one place.

Change-Id: Ia8acceff341ee8acd1e774fdf730e3700ca4ddd3
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/272252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agovide: tegra: host: fix nvmap handle leak
Krishna Reddy [Mon, 9 Sep 2013 23:28:16 +0000]
vide: tegra: host: fix nvmap handle leak

nvmap pinned handle in pinned during nvhost_nvmap_pin. But it
is not unpinned during nvhost_nvmap_unpin. This holds the handle
forever and leaks the memory.
Bug 1356091

Change-Id: Ie2d884720f21527c24ea79de6f128a9b29303fdd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272190
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra11: clock: Set wait count after EMC clock change
Alex Frid [Sat, 22 Jun 2013 07:29:23 +0000]
ARM: tegra11: clock: Set wait count after EMC clock change

Unconditionally update EMC_ZCAL_WAIT_CNT after EMC clock change.

Bug 1312928

Change-Id: I35a24757ed8f2cbca73393fb0d95533491524b3f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241212
(cherry picked from commit a0919e7dbba0a39fabbfd48f8270c72288b1240c)
Reviewed-on: http://git-master/r/257681
(cherry picked from commit e04f8cd6055c34a81fa65e415c25b0b8ef84fbe3)
Reviewed-on: http://git-master/r/271886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: clock: Add debugfs node for EMC DFS table info
Alex Frid [Sun, 16 Jun 2013 05:08:05 +0000]
ARM: tegra11: clock: Add debugfs node for EMC DFS table info

Bug 1308928

Change-Id: I9b4318a37902c78e61417e62ea1e51687bbf1ea5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239138
(cherry picked from commit 23f6e8484f9565f5f02c26a363b4b5177c9872b9)
Reviewed-on: http://git-master/r/245968
(cherry picked from commit a6a35548781184f998df2c70cc9c30b8f0b02382)
Reviewed-on: http://git-master/r/271885
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarm: tegra: ardbeg: added tshut info for AMS PMU
Diwakar Tundlam [Sat, 7 Sep 2013 01:58:55 +0000]
arm: tegra: ardbeg: added tshut info for AMS PMU

On ardgeb boards with AMS PMU, we need different tshut data to enable
therm-trip with soctherm. Added dynamic detection of PMU type and set
the tshut info.

Bug 1291108

Change-Id: I828cd43b98481f47cec0be8aa6dab4b6581e081f
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/271778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra12: clock: Rename "gpu" to "gpu_ref"
Kaz Fukuoka [Thu, 5 Sep 2013 23:25:24 +0000]
ARM: tegra12: clock: Rename "gpu" to "gpu_ref"

GPU PLL reference clock was mistakenly named as "gpu".

Change-Id: I5083cdfd98795002d46a68806e2c9d41282eb9a4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/271103
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agosecurity: tlk_driver: shared req/param reg SMC
Chris Johnson [Wed, 4 Sep 2013 00:48:59 +0000]
security: tlk_driver: shared req/param reg SMC

Add support for attempting to register the req/param buffers with
TLK. If it fails, we know we're on an older TLK and have to use
phys address to indicate where the buffers are.

If the SMC succeeds, we pass the virtual pointers to the buffers
knowing TLK will map them in and use them directly. This takes
care of the coherency and reduces our dependence on phys addrs.

Once both TLK and kernel changes have been synced up, we'll remove
the legacy support.

Bug 1353314

Change-Id: I1a73ddc66f002f966e80579ac49bbbd3e64a1f72
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/269802
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarch: config: enable nvhdcp for t12x.
Marvin Zhang [Fri, 30 Aug 2013 18:55:15 +0000]
arch: config: enable nvhdcp for t12x.

bug 1347934

Change-Id: I9b7e1ca19e2891515bbce7b4e4640ffa3c4c5423
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/268657
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

6 years agoARM: tegra: dvfs: Don't apply rail maximum limit
Alex Frid [Sat, 7 Sep 2013 00:20:54 +0000]
ARM: tegra: dvfs: Don't apply rail maximum limit

Removed clipping of target rail voltage to maximum limit. No clock
domain should ever request voltage above maximum. If happened it is
a bug, and now it would hit BUG() in regulator core (applying limit
before this change just masked the bug).

Change-Id: Ic482e546cf75aa968a548ba1eaf66ebf28abe861
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271819
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: dvfs: Re-name rail offset variable
Alex Frid [Sat, 7 Sep 2013 00:59:09 +0000]
ARM: tegra: dvfs: Re-name rail offset variable

Re-named rail offset variable from offset_millivolts to dbg_mv_offs,
since it is controlled by debugfs only.

Change-Id: I5b218769c01538b6f152d052ea2e0d409dd5e872
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271818
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: dvfs: Add tegra_dvfs_ prefix
Alex Frid [Sat, 7 Sep 2013 06:32:35 +0000]
ARM: tegra: dvfs: Add tegra_dvfs_ prefix

Added tegra_dvfs_ prefix to public dvfs functions.

Change-Id: I65995465fa79f4554504a4b37fa1e8f83f83ab1c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271817
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agovideo: tegra: dc: updated tegra_hdmi_audio_config table
Emma Yan [Thu, 21 Mar 2013 11:28:42 +0000]
video: tegra: dc: updated tegra_hdmi_audio_config table

Added 241500000 pclk entry for 1440p (2560x1440) HDMI support

Bug 1254995

(cherry picked from commit 87fa6a27e55983e3bb6f472fd05677ca80874dec)
Reviewed-on: http://git-master/r/211936
Change-Id: If68cee3eed532ef06d23e6a967836fde161c3e58
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271897
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

6 years agoARM: tegra: power: Disable CL-DVFS clock on LP1 entry
Alex Frid [Sun, 16 Jun 2013 02:11:15 +0000]
ARM: tegra: power: Disable CL-DVFS clock on LP1 entry

Disabled CL-DVFS logic clock on LP1 entry, and re-enabled it during
resume. If running DFLL is in open loop in LP1, and there is no need
to clock closed loop logic.

Change-Id: I097aa431d99cd24d1dd6a409ad37faecf8f579dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239134
(cherry picked from commit 8b56a79525817fab6e4bc7a6d905f6544d791116)
Reviewed-on: http://git-master/r/240863
(cherry picked from commit adbe3ecbb0d81a8a5eaf548dc209cabdd2f58a51)
Reviewed-on: http://git-master/r/271888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support
Alex Frid [Wed, 24 Jul 2013 02:58:41 +0000]
ARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support

- added dvfs tables for AP40X sku
- set DFLL mode Vmin with 0.9V if designated fuse is set

Bug 1326355

Change-Id: Id604580d02d820db5fcf40f77fd3afd8b9c79f35
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253188
Reviewed-on: http://git-master/r/237072
Reviewed-on: http://git-master/r/257730
(cherry picked from commit 97feb5338870afa3b0c499adc99a5554a488c78f)
Reviewed-on: http://git-master/r/271884
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: power: Add AP40X cpu EDP table
Alex Frid [Thu, 25 Jul 2013 03:46:56 +0000]
ARM: tegra11: power: Add AP40X cpu EDP table

Bug 1326355

Change-Id: I19b0a6dea4712b718477ca76f479fab0ff8b14b5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253187
(cherry picked from commit fdd98a8a7524cfe540a117cc183c9b817a935614)
Reviewed-on: http://git-master/r/257729
(cherry picked from commit eefc0988bdc336000adfe63e0477b928da0425a2)
Reviewed-on: http://git-master/r/271883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>