5 years agoarm: tegra: power: Updated EDP table to latest spec
Diwakar Tundlam [Mon, 9 Jan 2012 22:56:31 +0000]
arm: tegra: power: Updated EDP table to latest spec

(see bug for Excel with the new spec)
Bug 844268

Change-Id: I7a3bdd674b987c2edd540de7764e01338f66c0ac
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/74094
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/74893
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra86df1a80bf0b7e05efca69a736aba16ca55a3b4

5 years agoTegra: DTV: Added resources and device for DTV
Adam Jiang [Mon, 21 Nov 2011 06:48:41 +0000]
Tegra: DTV: Added resources and device for DTV

Added dtv interface device to Tegra3 platform.

Fixed Bug 904626
Fixed Bug 881303

Change-Id: Id2a4e6f015d3edf1ecd0e76f5586ae2ec00ed380
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/66627
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Reviewed-on: http://git-master/r/74890
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0e786c051fd2e2f183a40f86459e554019f26748

5 years agoARM: tegra: power: Fix Tegra3 LP2 stats
Alex Frid [Sun, 4 Dec 2011 05:56:29 +0000]
ARM: tegra: power: Fix Tegra3 LP2 stats

Fixed Tegra3 LP2 stats to account for total completed and interrupted
LP2 time (interrupted LP2 time was missed).

(cherry picked from commit 4207244f6fc25544315fe5aaf067ea7684731d9d)

Change-Id: I3b87819d56e3a700f7e0858fa124b0fdfabe8295
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73902
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/74557
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Rac5cfa164804ed340fed91bb7aef32858be4c8a6

5 years agoARM: tegra: clock: Split Tegra3 G/LP CPU backup rates
Alex Frid [Sun, 18 Dec 2011 06:54:55 +0000]
ARM: tegra: clock: Split Tegra3 G/LP CPU backup rates

Separated Tegra3 G and LP CPU backup rates used while main CPU PLL is
re-locking. These rates are selected low enough to be safe at minimum
voltage, but high enough to avoid voltage droop when CPU clock is
switched between backup and main clock sources.

Bug 868692

Change-Id: I6b07323a5d3a69d0834b743596aca1e5499781a4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71132
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-on: http://git-master/r/74551
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R1a6567272524070056cb68815af8bf3e9c05bd01

5 years agoarm: tegra: smmu: Move tegra_smmu.h under "include/mach"
Hiroshi DOYU [Mon, 9 Jan 2012 06:52:47 +0000]
arm: tegra: smmu: Move tegra_smmu.h under "include/mach"

This is the preparation the following patches so that  this header can
be referred from another directly than "arch/arm/mach-tegra".

Change-Id: I846970f306ff3daa8229e10e6f33b8e9fcf57cf9
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/73947
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R14812807899a11c6e7d7caf374025a4570552787

5 years agoarm: tegra: smmu: Set TEGRA_IOMMU_SMMU for platform_device
Hiroshi DOYU [Tue, 27 Dec 2011 08:02:07 +0000]
arm: tegra: smmu: Set TEGRA_IOMMU_SMMU for platform_device

This platform_device will be used for struct iommu_ops for SMMU in
addition to iovmm-smmu exclusively.

Change-Id: I8a15ba5ce40cd4bd5df255ecbe70a79a33fe8209
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/72216
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R147b54cf169a5ac4360cbdf2a112791eadfae16f

5 years agoARM: Tegra: fuse: Add A04 revision
Prashant Gaikwad [Mon, 2 Jan 2012 11:38:34 +0000]
ARM: Tegra: fuse: Add A04 revision

Change-Id: Ie1facdb47d9eae2438f1bb3928db174690dd2e4d
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/72862
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit da61c8810313729b8c8f451f6cf1586afff2bf12)
Reviewed-on: http://git-master/r/73959
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rf91402aa763f1e6ef5e78f2f19b4d7995309df45

5 years agoarm: tegra: power: Fix build errors if PM_SLEEP is not selected
Scott Williams [Thu, 5 Jan 2012 20:12:32 +0000]
arm: tegra: power: Fix build errors if PM_SLEEP is not selected

Change-Id: I2e7fa55c5d02ada3b203ec9627a4d91a5f17ca9b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/73539
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
(cherry picked from commit e3b0a2205133e5209a9e35c2300c03d384b1ae2a)
Reviewed-on: http://git-master/r/73954
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Re567ba3949cba82cec0739e984c0b835eb259468

5 years agoARM: tegra: Clean up tsensor includes
Dan Willemsen [Wed, 28 Dec 2011 23:16:02 +0000]
ARM: tegra: Clean up tsensor includes

mach-tegra/tegra3_tsensor.h is used for the parameterized initialization
of the tsensor device. mach-tegra/include/mach/tsensor.h is used for the
tsensor device driver.

Really, mach-tegra/tegra3_tsensor.c should go away - probably becoming a
device driver.

Change-Id: I16edae878f1e97d1654252cfee49cd9dd7f77db7
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/72481
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rd416691737c0fb9203ad1b7902e2e9459f312f43

5 years agoARM: tegra: power: L2 cache sync only for CPU0 LP2
Prashant Gaikwad [Tue, 3 Jan 2012 10:18:45 +0000]
ARM: tegra: power: L2 cache sync only for CPU0 LP2

Bug 922010

Change-Id: I19724ae5d8421b2fccfc604ecb0a867d20fddf75
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/72986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R4f9abdeb07699040a652edd8a1c7801ab1f8ee4e

5 years agoarm: tegra: delete the debugfs sys entry for suspend
Vandana Salve [Wed, 28 Dec 2011 15:47:54 +0000]
arm: tegra: delete the debugfs sys entry for suspend

Deleted the tegra debugfs /sys entry. Instead have a unified
/sys/power/suspend/mode sysfs entry to set the suspend state.

Bug 911096

Change-Id: I280eb0ed0f5c8b46c2147d84c27b1cf728078709
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/72419
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R3622a0a9ca159aef45155a45ff8ea0a12c308f33

5 years agoARM: tegra: pinmux: Support for setting pin io
Pradeep Goudagunta [Fri, 23 Dec 2011 08:53:02 +0000]
ARM: tegra: pinmux: Support for setting pin io

-Added support for setting a pin io state to INPUT/OUTPUT.
-Exported tegra_pinmux _get_pingroup/_set_io to make them
available to loadable kernel modules.

Bug 845065

Change-Id: I7d9500f590b804d1d222dfd7e42d1dbfc6686611
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/71975
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Re607ded0fdf5d2f70c2e2526b751b8f938574746

5 years agotegra3: clock: Support for divisor 15.1
Laxman Dewangan [Wed, 28 Dec 2011 08:51:16 +0000]
tegra3: clock: Support for divisor 15.1

Uart clock source has divisor of 16 bits where
LSB is 0.5.
Adding support for divisor 15.1 and configuring uart
for use the 15.1 type divisor.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

Change-Id: Ifdd77041e7abb43026bbfb273f6e12923d64d607
Reviewed-on: http://git-master/r/70324
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R51700ac0dad8ed1638cfd4944d84fe4b20b0f76a

5 years agoarm: tegra: power: io dpd APIs defined
Bitan Biswas [Fri, 30 Dec 2011 12:40:36 +0000]
arm: tegra: power: io dpd APIs defined

Defined IO deep power down(DPD) APIs for tegra drivers -
    tegra_io_dpd_get - returns dpd handle
    tegra_io_dpd_enable - enable driver dpd
    tegra_io_dpd_disable - disables driver dpd

bug 919993

Change-Id: I45976b41dca0e3e9266ace86393ef4db8b20c97b
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/72737
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R6b3beef3f41d164a7b00fa90af44d8729acba05b

5 years agoARM: tegra: power: Update Tegra3 auto-hotplug states
Alex Frid [Sat, 17 Dec 2011 03:57:04 +0000]
ARM: tegra: power: Update Tegra3 auto-hotplug states

Updated Tegra3 auto-hotplug state machine:

- no longer enter down state on LP CPU (there is no down path on LP)
- no longer enter idle state on G CPU (since load distribution between
G cores may change without CPU frequency change, continue polling)
- allow only disabled or idle state to be set via auto-hotplug sysfs
node, and synchronize with cpufreq governor in the latter case

Change-Id: Ibb93ddca852bbe1341fc5c52b0c83c16e9963e9d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Re92bbfefb418e94368a641fc2f0e2454c5dee1a2

5 years agoarm: tegra: Create nvmap dev based on config flag.
Krishna Reddy [Sat, 17 Dec 2011 02:35:28 +0000]
arm: tegra: Create nvmap dev based on config flag.

Create nvmap dev and related resources only when CONFIG_TEGRA_NVMAP
is defined.

Change-Id: Iee9e43de79767353a750f73cddd6550a74315cff
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/70699
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: Ra7946a135a435267da71653b6ff36dcc1c50ce77

5 years agoARM: tegra: disable cluster switch messages
Diwakar Tundlam [Wed, 14 Dec 2011 23:10:27 +0000]
ARM: tegra: disable cluster switch messages

Bug 915962

Change-Id: Icece8c31a7e31b3871dd836aa79b5f7cc28d0af1
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/70121
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R69e587fcbacb63f99e55a07c5d1b9eed1e1bde54

5 years agoARM: tegra2: power: Fix LP2/LP3 states accounting
Prashant Gaikwad [Wed, 14 Dec 2011 11:25:32 +0000]
ARM: tegra2: power: Fix LP2/LP3 states accounting

Made sure LP3 state is reported as last entered state to cpuidle
governor in case when LP3 is entered as a fall back from LP2 path.

bug 905813

Change-Id: I850dddef733d45587875eb796e609b01b1732ab9
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/70012
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: Re7e0970c07dd357568b347af3b90627cdad76a6a

5 years agoARM: tegra: power: Limit maximum online cpus number
Alex Frid [Sat, 17 Dec 2011 02:07:33 +0000]
ARM: tegra: power: Limit maximum online cpus number

Updated Tegra3 auto-hotplug mechanism to keep maximum number of
online cpus within the limit specified by the PM QoS parameter
PM_QOS_MAX_ONLINE_CPUS.

Added respective debugfs node /kernel/debug/tegra_hotplug/max_cpus.

Bug 894200

Change-Id: I278cbfd91a1760b282eab186aa21883918b13800
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7eac8fdeb97d6222f5dba307ca1de122c2064998

5 years agoARM: tegra: power: Fix clock event broadcast mode
Prashant Gaikwad [Tue, 13 Dec 2011 07:03:13 +0000]
ARM: tegra: power: Fix clock event broadcast mode

Do not switch to broadcast mode in common code since it
affects both Tegra3 and Tegra2. Tegra3 does not need
broadcast mode until final CPU is going in LP2.

Bug 905813

Change-Id: I7b888504e5a926c15f34b0bb2487e16f672d9294
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/69686
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R2141429f34c74ecd61cbd867825fdb12448ead3a

5 years agoarm: tegra: pm: do not turn off PLL-P & PLL-A for LP1 on Tegra3
Nikesh Oswal [Tue, 20 Dec 2011 10:26:24 +0000]
arm: tegra: pm: do not turn off PLL-P & PLL-A for LP1 on Tegra3

Bug: 917672

Change-Id: Ie3446f7fdaa05a6dab43375b842b37070cea33b7
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/71173
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: R8628592b81a75836e12711af32e57bb571d6a856

5 years agoarm: tegra: thermal: Low temp to therm algorithm
Joshua Primero [Sun, 18 Dec 2011 23:44:25 +0000]
arm: tegra: thermal: Low temp to therm algorithm

Instead of using 0C as default low temp in thermal
algorithm, query the thermal device driver for
lowest supported temperature.

Change-Id: Id1f70380ba476dec80e36ce79b42ab6f24a5d5ba
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/70935
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rdbf4ea3ed04b02216a4358864949a3a0c09e62aa

5 years agoarm: tegra: thermal: Added thermal debugfs nodes
Joshua Primero [Fri, 16 Dec 2011 19:11:02 +0000]
arm: tegra: thermal: Added thermal debugfs nodes

Added nodes which can set/get tc1, tc2, passive
delay, shutdown temp, and throttle temp.

Change-Id: I433bb09f9bf42cdbc7112fc98fa4ae88ca7e1de8
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/70930
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R9f568e677c0e36089bc58e90b1a844228f8b1240

5 years agoarm: tegra: thermal: Added name per therm device
Joshua Primero [Fri, 16 Dec 2011 19:09:50 +0000]
arm: tegra: thermal: Added name per therm device

Added name paramater per therm device so that is
easy to tell which therm device is being used
from sysfs

Change-Id: I58488b4c50ac6dc58dc00e270b613458f61a9fd6
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/70929
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rdcaae4d2d3695900d47c883c5a97bb45954acde5

5 years agoarm: tegra: pcie: minor fixes in pcie driver
Peer Chen [Thu, 6 Oct 2011 05:11:21 +0000]
arm: tegra: pcie: minor fixes in pcie driver

Fixed issues in entering suspend mode when
no pcie devices are connected

bug 873836
bug 876954
bug 884808

Reviewed-on: http://git-master/r/51506
(cherry picked from commit ae3b130e0458731a04b6d961f84831da7a2ce711)
(cherry picked from commit 05697d94499eb94bf3e1ccd87c1382a4b10dec7e)

Change-Id: I2a0fd104d2443c84edea2d62debc242b497fc38d
Signed-off-by: Peer Chen <pchen@nvidia.com>
Reviewed-on: http://git-master/r/70636
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mursalin Akon <makon@nvidia.com>
Tested-by: Mursalin Akon <makon@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: Re97ba1bbbaa98d22608eec09e2288254145aef93

5 years agoARM: tegra3: restate msi irq desc
Mursalin Akon [Fri, 16 Dec 2011 19:52:29 +0000]
ARM: tegra3: restate msi irq desc

Restate MSI irq desc in architecture specific
functions. This way, PCI device drivers can later
on hook those irqs.

Plus, a minor fix.

Change-Id: I3d9ba84c071309343b58c6200a9f53708e4043f4
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/70631
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: R58ce9348626514d65433cdcb7a1590b6a4308802

5 years agoARM: tegra: pcie: fix return value from MSI irq routine
Mursalin Akon [Thu, 22 Sep 2011 20:55:11 +0000]
ARM: tegra: pcie: fix return value from MSI irq routine

Fix the return value from MSI irq routine. Without this
change __report_bad_irq is invoked at MSI interrupt.

Bug 870667

(cherry picked from commit 30f82dda084d9260ed550585d16629872f703b0d)

Change-Id: I0f75d1a369c93f0f1e3203bdb1d875249a86337a
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/70630
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mike Thompson <mikthompson@nvidia.com>
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>

Rebase-Id: R639583b6c637ae1e5f4790bf74a61499ae8e5d24

5 years agoarm: tegra: power: add watchdog recovery function
Kamal Kannan Balagopalan [Mon, 12 Dec 2011 22:15:02 +0000]
arm: tegra: power: add watchdog recovery function

Add watchdog recovery mechanism to protect against hangs during
driver suspend/resume sequence

Bug 857748

Change-Id: I03d540b38318a5a953b1a697af123291b48991e9
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/65986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R6c8dc78398b06915c0cbd80be2cb4454bc4b0ff9

5 years agoARM: tegra3: dvfs: Added DVFS entries
Mohit Kataria [Mon, 14 Nov 2011 12:18:11 +0000]
ARM: tegra3: dvfs: Added DVFS entries

Added dvfs entries for automotive skus

Bug 883565, 882186

Change-Id: I6186b682fa82e24c3062bcbf5c2e5580fdf80562
Signed-off-by: Mohit Kataria<mkataria@nvidia.com>
Reviewed-on: http://git-master/r/70292
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rcef217763d8f30806c6c7dd47d51c12923407a72

5 years agoarm: tegra: Use generator macros for pinmux selectors
Scott Williams [Wed, 14 Dec 2011 21:41:20 +0000]
arm: tegra: Use generator macros for pinmux selectors

Replace the hand-crafted pinmux mux selector enumerators and
name table with generator macros to avoid mismatches between
them.

Change-Id: I2e56bf89a4b29f33af00d0e4d2617ee13c554997
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/70088
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: R7c0a7c9fb743a50cc0edf1a9671364d8c30a00ea

5 years agotegra: fix processing of regulator notifier event
Alexandre Courbot [Tue, 13 Dec 2011 10:13:49 +0000]
tegra: fix processing of regulator notifier event

Regulator notifier event chain may be called with several events OR'd
together, e.g. in drivers/regulator/core.c:

_notifier_call_chain(rdev, REGULATOR_EVENT_FORCE_DISABLE |
REGULATOR_EVENT_DISABLE,

Bug 913417

Change-Id: Ifba9860c1ee59c2fe2a4ee3c901e983912e07139
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-on: http://git-master/r/69725
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rb83003f89e371b359616e000f3cef249554bb999

5 years agoarm: tegra: thermal: Lower limit during throttle
Joshua Primero [Mon, 12 Dec 2011 23:17:07 +0000]
arm: tegra: thermal: Lower limit during throttle

Added a lower limit while in throttling to the thermal
layer.  Needed this for tsensor to work.

Change-Id: Ib4cc038b9a287a799ae19ca565798b06c26af02c
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/69562
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rba0d0ce41e4a8af1fad38a3570afec803f0ecf64

5 years agoarm: tegra: power: tsensor to therm framework
Joshua Primero [Thu, 3 Nov 2011 05:18:30 +0000]
arm: tegra: power: tsensor to therm framework

Hooked up tsensor to thermal framework.  Cleaned
up some unnessary tsensor code as well.

Bug 848755

Reviewed-on: http://git-master/r/62021
(cherry picked from commit 307f53a36bd1bdfaabddfdd80f9de5445d805786)

Change-Id: If4156c35f78575bc67b48d1d87fa82a4e32751c5
Reviewed-on: http://git-master/r/63344
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/67238
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rbb7f8c9fa4cca4030a8fe73808dbc74f83497566

5 years agoARM: tegra: common: Remove T30 A01 SMMU workaround
Hiro Sugawara [Tue, 13 Dec 2011 17:12:26 +0000]
ARM: tegra: common: Remove T30 A01 SMMU workaround

Remove CONFIG_TEGRA_SMMU_BASE_AT_E0000000 workaround as T30 A01 is no
longer supported.

Change-Id: I0ba6c838984e3c3ec401057925727c9596a8075f
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/95644
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Conflicts:

arch/arm/mach-tegra/common.c

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: Rfb33dd468704f551aa0b36f9da708a0a52292f8f

5 years agotegra: kfuse: add error handling in kfuse read
David Schalig [Tue, 13 Dec 2011 08:43:59 +0000]
tegra: kfuse: add error handling in kfuse read

Bug 914805

Change-Id: Ifb02c3193383b15f3f52964fcbad844fedd595c7
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/69704
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

Rebase-Id: Rb72361fae7dcd154a90c70870d2d1c2d831dcd3c

5 years agoarm: tegra: power: clear pmc wake status register on suspend
Sanjay Singh Rawat [Wed, 7 Dec 2011 14:04:51 +0000]
arm: tegra: power: clear pmc wake status register on suspend

PMC register hold the reason for wakeup from LP0. The keypad driver resume the
device from the perspective of the User if the Power Key event is sent in the
register. Reset the register before going to suspend so that the status won't
get carried to the next wake time as in this case of LP1.

Bug 909191
Bug 913110

Change-Id: Ib00b26cd65008327f53b120ca8d0a4dbd3628227
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/68686
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R9eba446ed2a177ddb2f2b35a760ff0146c22789a

5 years agoARM: tegra: dvfs: Add DVFS rails statistic
Alex Frid [Sun, 20 Nov 2011 01:28:31 +0000]
ARM: tegra: dvfs: Add DVFS rails statistic

On Tegra3: complete account of in- and out-of-bound rails control.
On Tegra2: out-of-bound vdd_cpu control in LP2 state is not accounted.

Change-Id: Ib68cbbfe3e4f965e758aca17a0ba30277d530347
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/67340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rf2aa9242f09fc393fa5114cd059894ebdbeedcee

5 years agoARM: tegra: power: Restore IRQ multiple CPU affinity
Alex Frid [Sat, 10 Dec 2011 03:21:36 +0000]
ARM: tegra: power: Restore IRQ multiple CPU affinity

Restore IRQ affinity to multiple CPUs after LP=>G CPU mode switch.

Change-Id: Id7c263f2a11535669d1e9988f4e15b240a7fde38
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/69329
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R669e1583e757f6dd6c23205b9798ca44a50b7257

5 years agoARM: gic: Use affinity hint to set multiple CPUs for IRQ
Alex Frid [Wed, 12 Oct 2011 05:59:38 +0000]
ARM: gic: Use affinity hint to set multiple CPUs for IRQ

GIC IRQ affinity is currently set to one CPU only - the 1st cpu in
the requested mask. This commit adds option to set IRQ affinity to
all cpus present in affinity_hint and requested masks. The option is
enabled by default on Tegra architecture starting with Tegra3.

(cherry picked from commit 09f7ef4f28a6e18188649c40848252bc18a6646c)

Change-Id: I0d655f1d39170382f3372294172ed6d02dc0ad49
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/69328
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rd7536367e9b41245c6360371972ed0a31af40072

5 years agoarm: tegra: enterprise: support A01 camera module
Jihoon Bang [Mon, 12 Dec 2011 19:00:14 +0000]
arm: tegra: enterprise: support A01 camera module

Change if statement to support E1513 A01 board in E1197.
Add tegra_get_camera_board_info to parse camera module id
that is passed in from bootloader.

Bug 914552

Change-Id: I20c3bcaf181e29446aa254ea189d917bc6905488
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/69504
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Re823d0ebe9e0e54a74dc9930ab9f45049c34d6ef

5 years agoSPI: Register SPI1 as slave device
Krishna Yarlagadda [Mon, 21 Nov 2011 11:31:44 +0000]
SPI: Register SPI1 as slave device

Registering SPI1 as slave device which will be used in
loopback tests on E1198

Bug 903874

Reviewed-on: http://git-master/r/66790
(cherry picked from commit 87d7bc65a43dbb3a745c1bcb03e53ba44f8e80e9)

Change-Id: I22aeca2457dcb38125de48275e00c268fbe8792b
Reviewed-on: http://git-master/r/69189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7254788d26bfa161ebd758f6df46a2dc7cef7147

5 years agoARM: tegra: clock: Use Tegra3 PLL lock indicators
Alex Frid [Thu, 8 Dec 2011 05:35:38 +0000]
ARM: tegra: clock: Use Tegra3 PLL lock indicators

Bug 873599

Change-Id: Ice84a63d90d39105e53505282fe126e56c4749db
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/68897
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R5cfe49b30fe7b5b706dd4d84c27872b594e6779f

5 years agoarm: tegra: cardhu: pcie support for cardhu bsp
Jay Agarwal [Mon, 5 Dec 2011 08:55:38 +0000]
arm: tegra: cardhu: pcie support for cardhu bsp

Enabling PCIE support in cardhu board.
Fixes bug: 637871

Reviewed-on: http://git-master/r/34474
(cherry picked from commit bde3e58d998b6e76934152219b8803327cea2fad)

Change-Id: I18c548b458ad3d17ec07d2ec5b16fd83897b44b1
Signed-off-by: Krishna Kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/62072
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R17a36809823a7736e26d46a6e47fef7a38810e32

5 years agoarm: tegra: pcie: enabling MSI support for pcie
Krishna Kishore [Tue, 30 Aug 2011 08:36:51 +0000]
arm: tegra: pcie: enabling MSI support for pcie

MSI style interrupt support is being added to
pcie driver

Fixes bug: 637871

Reviewed-on: http://git-master/r/47330
(cherry picked from commit de7fd8768b32da66eaf4eaf58473c65f7a76808d)

Change-Id: I105db7d08b545e75832f12433d8c2d233444294a
Signed-off-by: Krishna Kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/62066
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R16977aeb938079baee8e738bdac4c1340244ef29

5 years agoarm: tegra: pcie: Adding tegra3 support for pcie
Jay Agarwal [Mon, 5 Dec 2011 08:43:01 +0000]
arm: tegra: pcie: Adding tegra3 support for pcie

Added support for tegra3 to pcie driver

Fixes bug: 637871

Reviewed-on: http://git-master/r/44989
(cherry picked from commit 9bbfb4189474ede7f16a20b564ac7da2a93f6750)

Change-Id: Ic0bb5b8d3098030baee5d8db6ca043df71db5a8e
Signed-off-by: Krishna Kishore <kthota@nvidia.com>
Reviewed-on: http://git-master/r/62059
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R718d10dd284379f3bb929af595318484cac33565

5 years agoarm: tegra: Invalidate TLB/BTAC afer enabling coherency
Prashant Gaikwad [Thu, 1 Dec 2011 04:47:51 +0000]
arm: tegra: Invalidate TLB/BTAC afer enabling coherency

Change-Id: Idaf841e245f3bccaae77375bb839e8c00bbc7542
Reviewed-on: http://git-master/r/67592
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R80d1db7627a4a13310765229216e7a7e4d9c4ab7

5 years agoarm: tegra: Restore L2 Aux control reg after LP2 exit.
Krishna Reddy [Mon, 5 Dec 2011 20:57:07 +0000]
arm: tegra: Restore L2 Aux control reg after LP2 exit.

Bug 908229

Change-Id: I0ce5955e62a66d806ff8937342e8f80940725f39
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/68270
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R513e51602afccf1a6308749d35630a195e178926

5 years agoarm: tegra: irq: PMC WAKE2 level configuration
Bitan Biswas [Thu, 8 Dec 2011 07:03:15 +0000]
arm: tegra: irq: PMC WAKE2 level configuration

Wake level was not getting programmed for wake sources beyond WAKE31.
Previous expression was using 32-bit operation. Changing constant 1
to 1ull corrects the calculation.

bug 907980

Change-Id: Ie2e5f9a7dd4024db9d96859251169027570540f0
Reviewed-on: http://git-master/r/68907
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rb9c6d78f507b9b0c6c2522c4abf138ae398ab304

5 years agoarm: tegra: irq: any polarity lp0 wake change
Bitan Biswas [Wed, 7 Dec 2011 16:39:02 +0000]
arm: tegra: irq: any polarity lp0 wake change

False lp0 wakeup due to wake sources configured as any polarity was
traced to an earlier change. Reverting the change.

bug 906073
bug 909193

Change-Id: I1b2d8ecb265e9a57b5d2514f86853bd59481b58a
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/68700
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>

Rebase-Id: R8571f63c0439c211f09da76bb409682310e9dca5

5 years agoarm: tegra: pm: preserve r4 - r11 across a suspend
Varun Wadekar [Tue, 6 Dec 2011 12:00:03 +0000]
arm: tegra: pm: preserve r4 - r11 across a suspend

Make cpu_suspend()..return function preserve r4 to r11 across a suspend
cycle.  This is in preparation of relieving platform support code from
this task.

Original commit: 5fa94c812c0001ac7c3d8868e956ec514734a352

Bug 911002

Change-Id: If33c32ba7de449288eac8f83cb0898ba77a46333
Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R79c9865c168b8fde6a02b1ddce1bd98400e19161

5 years agoarm: tegra: pm: move return address (for cpu_resume) to top of stack
Varun Wadekar [Tue, 6 Dec 2011 11:47:07 +0000]
arm: tegra: pm: move return address (for cpu_resume) to top of stack

Move the return address for cpu_resume to the top of stack so that
cpu_resume looks more like a normal function.

Original commit: 2fefbcd58590cf33189c6178098e12b31b994b5f

Bug 911002

Change-Id: I275930306a3b4ecb551a32da5f9f26dba53459ec
Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Rebase-Id: R54ebcedde6a84a538f44bcec759af88fef0abe4c

5 years agoarm: tegra: Set G-CPU L2 cache latency based on chip sku
Diwakar Tundlam [Fri, 2 Dec 2011 23:49:42 +0000]
arm: tegra: Set G-CPU L2 cache latency based on chip sku

Bug 909628

Change-Id: I945c3fe7675cf481b770be7025d436b6bf4e9ee6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/68073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R2c8414cf787cbc757ce9740059edac6ba17adc64

5 years agoARM: tegra: power: Limit CPU rate on system EDP alarm
Alex Frid [Thu, 6 Oct 2011 04:20:21 +0000]
ARM: tegra: power: Limit CPU rate on system EDP alarm

System electrical design point (EDP) alarm is generated when system
power source (battery) over-current is detected.

Part of the system EDP management is CPU frequency capping added by
this commit. Maximum CPU clock frequency is pre-determined depending
on number of CPU cores on-line. It is combined with CPU regulator EDP
limit and applied to final CPU rate; CPU voltage is scaled down by
DVFS, respectively. The system EDP limit of CPU rate is removed after
alarm is canceled.

EDP event can be emulated via debugfs entry /d/cpu-tegra/edp_alarm.

(cherry picked from commit fa673d27766ff9513139e94a498e4c24827d7c57)

arm: tegra: power: Removed erroneous ';'

(cherry picked from commit b4b404381b2d1823b7c127858950f853428fe3b5)

Change-Id: I60ec0e87f9442b698a8824895aac0a1f955565b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/67823
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R6a004bea8dfc99cd965f94035481907007bd1e32

5 years agoarm: tegra: power: Added EDP table for Tegra3 xL
Diwakar Tundlam [Mon, 5 Dec 2011 23:17:01 +0000]
arm: tegra: power: Added EDP table for Tegra3 xL

Bug 844268

Change-Id: Iddffd445401318fb0e64d6739dbf833da7daede9
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/68313
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rc62624a34cb15039023c46f53c1c07119dbed007

5 years agoarm: tegra: Enabled TEGRA_THERMAL_SYSFS by default
Joshua Primero [Sat, 3 Dec 2011 00:02:04 +0000]
arm: tegra: Enabled TEGRA_THERMAL_SYSFS by default

Use the Linux thermal sysfs framework by default now
which provides hysteresis and clear distinction between
thermal and cooling devices.

bug 877359

Change-Id: I3ef3e9079a8bfb500efae0b2165afd4025e5b075
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/68032
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R3aac623e10d6484e7a0bfa64e2d81f6bdf4f480c

5 years agoarm: tegra: thermal: Thermal cleanup
Joshua Primero [Tue, 22 Nov 2011 22:37:06 +0000]
arm: tegra: thermal: Thermal cleanup

Added tc1, tc2, and passive delay to thermal framework
parameters.

Made thermal offsets more explicit and clean.

In throttling code, instead of using one 10 second 640000 entry,
split this into five 2 second entries.  This will give better
temperature stability.

bug 877359

Change-Id: Idc463ab18bdabb7a0472f4f6572195bf76067bd4
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/68029
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R68a2bb662fe81636defdaa88da75cffb11712cf7

5 years agoarm: tegra: power: Updated EDP table to 9/12/2011 spec
Peter Boonstoppel [Mon, 10 Oct 2011 18:48:14 +0000]
arm: tegra: power: Updated EDP table to 9/12/2011 spec

(see bug for Excel with the new spec)

Bug 844268

(cherry picked from commit 036969082d6571a26572cfe80f62144be87e732b)

Change-Id: Iacc9081ace5629588b7634d2927d9ea5a7c8c91b
Reviewed-on: http://git-master/r/57095
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/68257
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R1d5a65cedf5c222b5368c9e883543210ae161406

5 years agotegra: treewide: Remove unused gpio-names.h includes
Dan Willemsen [Thu, 1 Dec 2011 22:28:44 +0000]
tegra: treewide: Remove unused gpio-names.h includes

Most places shouldn't be using these macros, they should get the gpio
information from the board files. Either way, all of these instances
were unused.

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: Ifb76704dccb24e5e6eab4c06c79bc8e97802c6d3
Reviewed-on: http://git-master/r/68481
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R400744dd961661a38cea2ec1afde4a6db357e644

5 years agoARM: tegra: clock: Enforce Tegra3 cbus parent assignments
Alex Frid [Fri, 18 Nov 2011 21:03:46 +0000]
ARM: tegra: clock: Enforce Tegra3 cbus parent assignments

Tegra3 graphics bus (cbus) modules do not use PLLM as a clock source
after boot. Explicitly enforced this policy now by failing set parent
API if PLLM is selected as a target for any cbus clock.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>

(cherry picked from commit eb2662b7d90af77ee01202e57afa3ed46d4f9053)

Change-Id: Ia17972c8c711d3498541ad62aef3961656433665
Reviewed-on: http://git-master/r/67832
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R85790fb62aae8f3b7dfc5754a5c359a45a36556a

5 years agoarm: tegra: Set G-CPU L2 cache latency to 0x442/552.
Krishna Reddy [Thu, 1 Dec 2011 23:32:36 +0000]
arm: tegra: Set G-CPU L2 cache latency to 0x442/552.

also restore the L2 cache latency values after exit from LP2.
Bug 909628

Change-Id: Ia113d3511255f77ba5f5bfbfafebe43ba247818f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/67767
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R83fa076e3f91fbca3da82ee180a8b24dc60ec7a0

5 years agoarm: tegra: power: Tegra Thermal refactoring
Joshua Primero [Fri, 14 Oct 2011 00:49:20 +0000]
arm: tegra: power: Tegra Thermal refactoring

Refactored Thermal module so that thermal device
drivers themselves are agnostic of the thermal
framework.  Also separated throttle limit constraints
from EDP table.

Reviewed-on: http://git-master/r/57990
Reviewed-on: http://git-master/r/63338

Cherry-picked from 8d0610bdd03c3490b718f11bc2108f45cd868533.

Change-Id: I4f87889c9cdc88daac1e6173043bab1f2e7cebfd
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/66551
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R37100c974463886fa01da5daa768e35d24c125fd

5 years agoarm: tegra: power: Device agnostic thermal driver
Joshua Primero [Tue, 4 Oct 2011 05:23:53 +0000]
arm: tegra: power: Device agnostic thermal driver

Added a thermal driver which is agonistic to the device driver
which will make it easier to port thermal devices to android
tegra.

Reviewed-on: http://git-master/r/55883
Reviewed-on: http://git-master/r/59471
(cherry picked from commit b89dbb5a64bcb3124794f644e71658de83a4ab71)

Change-Id: Ib3c7100144ea0a98ac7c15e404d4d9e7737018e5
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/66548
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R44a3c17d5434d83357c55e776ff216ba0d97992e

5 years agoARM: tegra: Pad client list of TEGRA_POWERGATE_HEG
Terje Bergstrom [Thu, 3 Nov 2011 11:58:22 +0000]
ARM: tegra: Pad client list of TEGRA_POWERGATE_HEG

Client list for TEGRA_POWERGATE_HEG was not padded with MC_CLIENT_LAST,
which causes an infinite loop if HEG is power gated.

Bug 855755

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/62129
(cherry picked from commit b36a3ef9584ceb23bd0ed97ba662a12ec08ce957)
Change-Id: Id6ad765db682ee153c7a271e01e3c40e462db6c4
Reviewed-on: http://git-master/r/67126
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rcc760672dbf2cc139a5637bb12e4d02393533e4e

5 years agoARM: tegra: power: Fix-up return value
Shridhar Rasal [Wed, 23 Nov 2011 08:58:18 +0000]
ARM: tegra: power: Fix-up return value

Fixes the return value for tegra_powergate_set () when new status
to be set and current status are same.

Change-Id: Iffbc4fac239c4ea21f3026cbf33fe4fb7941aa2d
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/66404
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

Rebase-Id: Rbdab9a71478fde0902191c85ac6340b74907d70d

5 years agoARM: tegra: iommu: Clean up checkpatch and CodingStyle errors
Hiroshi DOYU [Fri, 11 Nov 2011 11:15:03 +0000]
ARM: tegra: iommu: Clean up checkpatch and CodingStyle errors

- Fixed checkpatch.pl --strict errors.
- Inserted one space around binary operators
    From Documentation/CodingStyle "3.1: Spaces".
- Removed a file path line in the head of file.
- Updated Copyright year
- Removed duplicated header inclusions

Change-Id: I750e31cf6e90a9f36e707a6278da6137e1a8ba05
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/66351
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rf17092562772408c52346481dbb32dec48fc3a9c

5 years agoARM: Tegra: power: Tegra3 T33 set EDP limits correctly
Diwakar Tundlam [Tue, 29 Nov 2011 01:04:23 +0000]
ARM: Tegra: power: Tegra3 T33 set EDP limits correctly

bugid 844268

Use correct regulator current value obtained from bootloader
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: I9059a5e83c88c6fc0e933acd3c4ab6e6b9c35078
Reviewed-on: http://git-master/r/67025
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>

Rebase-Id: Rce035e804a189df47a5b5c2a03f418d88cd9147a

5 years agoARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltage
Alex Frid [Sat, 19 Nov 2011 06:46:04 +0000]
ARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltage

Updated Tegra3 xL core speedo and nominal voltage settings.
Re-factored nominal voltage selection, since new data introduced
dependency of core voltage on both CPU and core speedo id.

Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675)
(cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301)

Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1
Reviewed-on: http://git-master/r/67014
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rd35cb9ac1fbcb424548e05d10d5622744394e796

5 years agoARM: tegra: dvfs: Make EMC voltage scaling board dependent
Alex Frid [Sat, 5 Nov 2011 04:06:52 +0000]
ARM: tegra: dvfs: Make EMC voltage scaling board dependent

Added minimum voltage field to Tegra3 EMC frequency scaling table.
Adjusted default (common) EMC DVFS mapping, respectively, when EMC
frequency table for the particular board/dram chip combination is
loaded.

Bug 895245

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 1fe4d12c4abdd08abd45eb755d3d50780cafb19c)
(cherry picked from commit 4020c6aacfd5ec3c7106cc05e720bc4c356ac58d)

Change-Id: Ia10183001996aee37259efdb533640ebf72d552a
Reviewed-on: http://git-master/r/67012
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rb1cb3a849c9c870b0c338a5a0a7e9cb9a7572674

5 years agoARM: tegra: clock: Update Tegra3 cbus operations
Alex Frid [Sun, 13 Nov 2011 03:16:50 +0000]
ARM: tegra: clock: Update Tegra3 cbus operations

- Doubled PLLC (cbus parent) rate to make sure that cbus clients always
  have only even dividers.

- Added new shared bus user mode - SHARED_AUTO for user (like Host1x)
  that just follow the bus, but by itself does not require bus rate
  above the minimum.

Bug 895245

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit e95329c67d4efc424d3408b363e092c02c066ef7)
(cherry picked from commit 773e089f2ab676e9ea8afd7aaa0458654a3772d9)

Change-Id: Ie1488f38e3cb948d69738c2eef4ae9cd7ae0b47d
Reviewed-on: http://git-master/r/67011
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rdd00a21fc2f58efdfeec5733c0307627da1fb430

5 years agotegra: NOR: Add NOR platform device
Manoj Chourasia [Wed, 19 Oct 2011 17:55:32 +0000]
tegra: NOR: Add NOR platform device

Added NOR platform device for Tegra.

Reviewed-on: http://git-master/r/56895
(cherry picked from commit 6b93835cef6321f286b8efcd032a1a1cc7a6ae9d)

Change-Id: Ie0219f1b7534f140a1da924f4f97a52f50d59ad2
Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/66705
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R8ca0f2697a54ee48996c57af936bcc69c942db46

5 years agoarm: tegra: timer: Fix compiler warning
Scott Williams [Wed, 23 Nov 2011 20:48:07 +0000]
arm: tegra: timer: Fix compiler warning

Fix compiler warning when PM_SLEEP and HOTPLUG_CPU are not configured.

Change-Id: I6e9e7aaf9c63752d0c33363b1cced75b4437d82d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/66508
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Gerrit_Virtual_Submit

Rebase-Id: R5687b9e034e004907ba01263948bf839544adb1b

5 years agoARM: tegra: clock: Update EMC clock change procedure
Alex Frid [Tue, 15 Nov 2011 03:25:18 +0000]
ARM: tegra: clock: Update EMC clock change procedure

Set MC arbiter limits before EMC clock change on Tegra3.

Bug 896654

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 16f545012457a04ba38f4f8bf80646b18a74cb2f)
(cherry picked from commit bd29cb18f1d26cc3a0fdc8933a08158d623fed58)

Change-Id: I080f21030007909bece5272ccdb93f8a85d4b13b
Reviewed-on: http://git-master/r/66515
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R0561570b37cdff800f0a7f71558eef16eb82cc59

5 years agoARM: tegra: clock: Support restricted PLLM usage
Alex Frid [Sat, 12 Nov 2011 02:19:16 +0000]
ARM: tegra: clock: Support restricted PLLM usage

Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.

Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)

Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Re70df2b753de37d6873609c121440337fc3ac626

5 years agoarm: tegra: edp: add config to use internal tsensor
Bitan Biswas [Fri, 2 Sep 2011 18:20:18 +0000]
arm: tegra: edp: add config to use internal tsensor

Introduced kernel config variable to enable internal tsensor
EDP and throttling support feature -
CONFIG_TEGRA_INTERNAL_TSENSOR_EDP_SUPPORT

bug 848755

Reviewed-on: http://git-master/r/53822
(cherry picked from commit bacc6c8c7fc150db8d678281fd9cd1536d18d2bb)

Reviewed-on: http://git-master/r/65451
(cherry picked from commit 2793d55e3d50bb8d76e1191f8a0f53f822fbd875)

Change-Id: Ia15d13e670192b6656f20f29b5348aa995d95749
Reviewed-on: http://git-master/r/66444
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R3ed1f0cbdd9bc1ba52b7d37930df4ab2d81e6598

5 years agoARM: Tegra: power: Tegra3 T33S updated EDP limits
Dan Willemsen [Mon, 2 Sep 2013 23:01:45 +0000]
ARM: Tegra: power: Tegra3 T33S updated EDP limits

bugid 844268

Reviewed-on: http://git-master/r/65547
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 72d41cc5200454175d8dc04c761c983405e4d901)

Change-Id: Ica5aaf0bedb02bff3485cdcb76e81da80896a309
Reviewed-on: http://git-master/r/66520
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R7ed6a74e13a6900490c83a15f5adc00c5163d663

5 years agoARM: tegra: power: Correct EMC_ADR_CFG mask
Daniel Solomon [Mon, 21 Nov 2011 22:12:38 +0000]
ARM: tegra: power: Correct EMC_ADR_CFG mask

The mask used to check bit EMEM_NUMDEV in register EMC_ADR_CFG is
wrong for T30. Correct it.

Change-Id: I3deb1229cb27081049de1a4f2fd69e21507fa853
Reviewed-on: http://git-master/r/65927
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R328e76d0f107d1b2fe1f27a81c1fab82dc4808d6

5 years agoarm: tegra: power: lp0 wake enable modified
Bitan Biswas [Tue, 15 Nov 2011 09:09:02 +0000]
arm: tegra: power: lp0 wake enable modified

GPIO based lp0 wakeup needed to support search for its irq
as well as GPIO bank irq in table. This is implemented
in this change.

lp0 wakeup irq enable using enable_irq_wake needs to be
called in specific drivers. Additionally, in some cases
wake irq needs to be updated in tegra wakeup table.

bug 890309
bug 902114

Change-Id: I983318172ffb020f565763cfe2bb29018223dcd0
Reviewed-on: http://git-master/r/64395
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rffcadeee341a73f2ea6d62e31d507e9a8dce5a0e

5 years agoARM: tegra: power: L2 cache sync only for CPU0 LP2
Prashant Gaikwad [Mon, 14 Nov 2011 12:25:55 +0000]
ARM: tegra: power: L2 cache sync only for CPU0 LP2

Bug 901430
Bug 905813

Change-Id: Id57f870262eebe6a2017b808d1a66624f903989d
Reviewed-on: http://git-master/r/64103
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc3cad5fafa9e62fa10099bc4dc1281954a04b8f5

5 years agoARM: tegra: power: omit L2 flush for LP2
Antti P Miettinen [Mon, 24 Oct 2011 08:20:33 +0000]
ARM: tegra: power: omit L2 flush for LP2

The L2 cache RAM is preserved over LP2 so omit the L2 cache flush
in tegra_idle_lp2_last().

Bug 880338

Change-Id: I6aa30c712b6e467bd48e9c1959da2a69453a8f43
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/59892
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6eee47d009d45d0e20254a97df919bf2fc34e6cd

5 years agoARM: tegra: dvfs: Fix dvfs over-voltage error handling
Alex Frid [Fri, 4 Nov 2011 03:06:10 +0000]
ARM: tegra: dvfs: Fix dvfs over-voltage error handling

Record dvfs client voltage rate request only after over-voltage error
is checked (otherwise, after over-voltage error rail goes above the
limit when another client requests voltage change).

(cherry picked from commit 9151f77b545dc5b898ad16ceb695cc57764f94e0)

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 40243988e73a13a5c94db410cb0335fa8a9b1e42)

Change-Id: I70769b2ffd7303db6e54bfc3e07b47ea3e67b7b8
Reviewed-on: http://git-master/r/64767
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Re82214f06084d58eed67edb35443f7a72ac4d112

5 years agoARM: tegra: clock: Add Tegra3 emergency throttling
Alex Frid [Fri, 14 Oct 2011 02:12:55 +0000]
ARM: tegra: clock: Add Tegra3 emergency throttling

Add Tegra3 emergency throttling API to directly control G-CPU super
clock skipper underneath clock framework, dvfs, and cpufreq driver
s/w layers. To be used by system power supply over-current ISR.

(cherry picked from commit fca2a12e90684526b2b7aeeb3af31de4254ad939)

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit b30bf0b313131037baffed7b6467eb1e0f021d19)

Change-Id: Ice064326d46f868a9d59d2e1f53930d644fdfc02
Reviewed-on: http://git-master/r/64766
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: Rf42ae930ba90de1c40843b5565251e4c1c92a642

5 years agoARM: tegra: dvfs: Update Tegra3 EMC DVFS
Alex Frid [Fri, 4 Nov 2011 04:07:03 +0000]
ARM: tegra: dvfs: Update Tegra3 EMC DVFS

- Moved validation of EMC maximum rate against nominal core voltage
from common dvfs initialization to board specific EMC scaling table
setup (a logical place to do it, since EMC DVFS is board dependent)

- Used current rate as rounded EMC rate if no EMC scaling table is
provided (instead of maximum EMC rate - no sense in attempt to set
maximum rate, or any rate, for that matter, if there is no table).

- Cleaned EMC initialization procedure

(cherry picked from commit 4f655077e09c0dc4abc50d190d82c91473e2e81c)

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit a213668b4f54b8ea7603a6d1e71f8b4ab1998bf7)

Change-Id: Id61f33e42556a6415e45b014bcadace600dd86d5
Reviewed-on: http://git-master/r/64765
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R697e04b6140eb0084bdb341febe3acdf91d93535

5 years agoARM: Tegra: power: Tegra3 AP33 SKU updated EDP table
Diwakar Tundlam [Tue, 1 Nov 2011 23:30:31 +0000]
ARM: Tegra: power: Tegra3 AP33 SKU updated EDP table

bugid 844268

Reviewed-on: http://git-master/r/64185
(cherry picked from commit a27e20a84ce1bab8a1d37f12f7f9260d9d32dbfe)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: I88b108fd44719828e11499606ab7ef754f76ebac
Reviewed-on: http://git-master/r/65290
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R557e282e415fd4bed871ea1ed8c056ae79731311

5 years agoARM: tegra: clock: Enable EMC scaling for AP25
Prashant Gaikwad [Tue, 15 Nov 2011 14:29:47 +0000]
ARM: tegra: clock: Enable EMC scaling for AP25

Workaround added to enable EMC scaling for AP25.
PLL switching support added for 300MHz EMC scaling step.

Bug 892505

Reviewed-on: http://git-master/r/#change,41718
Reviewed-on: http://git-master/r/#change,41720
Reviewed-on: http://git-master/r/#change,60861

Change-Id: I885b8dc4e3b6124ebed572c06cea773de6c83471
Reviewed-on: http://git-master/r/64465
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rb8e58cfa7fe1106978030c8aea292e95a7a5da2b

5 years agoarm: tegra: enterprise: add platform data for bt voice call
Nikesh Oswal [Wed, 9 Nov 2011 09:57:37 +0000]
arm: tegra: enterprise: add platform data for bt voice call

Bug: 862023

Change-Id: I826bf1b2de5681bd999b989ab74f86f26155f421
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/63248
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rec26d539061cdcd8895a539416f05111605b56b0

5 years agoarm: tegra: enterprise: add platform data for voice call
Nikesh Oswal [Sun, 6 Nov 2011 04:02:36 +0000]
arm: tegra: enterprise: add platform data for voice call

add platform data structures for codec i2s port connections
and baseband parameters

Bug: 862023

Change-Id: I52cc25e623474f6d5dd070cf4aedc1f108980595
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/62618
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rbe96cc2c99342de04590101d96c09616e72c6a41

5 years agoARM: Tegra: power: T33 SKU EDP table for 10A regulator
Diwakar Tundlam [Tue, 25 Oct 2011 01:20:08 +0000]
ARM: Tegra: power: T33 SKU EDP table for 10A regulator

bug 841336

Reviewed-on: http://git-master/r/62766
(cherry picked from commit c27e091be2ec3899fbb0bdbfe199784063f24be1)

Change-Id: I40277cea7f48cc15e074123ee73287b25389c0e6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/64211

Rebase-Id: Reef8906240656bfee07dbf9ba8f581677bad8e5f

5 years agoarm: tegra: Add HDA support
Sumit Bhattacharya [Fri, 21 Oct 2011 06:28:36 +0000]
arm: tegra: Add HDA support

Modify HDA device names to be inline with Intel HDA driver. Also
add entries for both HDA controller memory base address and HDA
controller PCI base address.
Also modify the dev_id and con_id of HDA related clocks so that
they can be used by HDA driver.

Bug 872652

Change-Id: Ifa05fe7d3d524e9ae310594a0e582c297dc52ef7
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/59506
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: R098f861d94a78a1401841b71b8c591b902b7b0bc

5 years agoARM: Tegra: dvfs: T33 SKU EDP table
Diwakar Tundlam [Fri, 12 Aug 2011 00:22:57 +0000]
ARM: Tegra: dvfs: T33 SKU EDP table

Bug 841336

Reviewed-on: http://git-master/r/60779
(cherry picked from commit 4d3f017e2715f50aaca6c7e8dc61e880947f7550)

Change-Id: Ib1eeb8729a91162d39fc952eeb7494d8863a03c7
Reviewed-on: http://git-master/r/64204
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rcfa5f6c11e831c4f08e956609ea8f9d98a6111f8

5 years agoarm: tegra: power: add TEGRA_THERMAL_SYSFS option
Joshua Primero [Tue, 4 Oct 2011 00:43:53 +0000]
arm: tegra: power: add TEGRA_THERMAL_SYSFS option

Added option to enable the use of the Linux Thermal
Sysfs infrastructure within the tegra thermal
framework.

Change-Id: I4306d173173a162dce18d864c46a9601523cdd09
Reviewed-on: http://git-master/r/59472
Reviewed-on: http://git-master/r/62574
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rbb6b3261fbdf2aa997f47eb254634fc6eff3ffb9

5 years agoARM: tegra: power: add combined power req processing
Joshua Cha [Mon, 14 Nov 2011 01:37:31 +0000]
ARM: tegra: power: add combined power req processing

For platforms where the core & CPU power requests are combined
as a single request to the PMU, we need separate processing to
enable its suspend/resume operation.

Bug 862504

Change-Id: If66282a7b069d35568147e2d64f14371e1692bfd
Reviewed-on: http://git-master/r/64011
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R21b966a438be03b11b80ce7deb70e3036b80dab2

5 years agoarm: tegra: power: Add throttle as a cooling dev
Joshua Primero [Tue, 4 Oct 2011 00:34:55 +0000]
arm: tegra: power: Add throttle as a cooling dev

Added cooling device hooks into the throttling module
to be used with the linux thermal sysfs infrastructure.

Reviewed-on: http://git-master/r/59470
(cherry picked from commit a7d0c2d23ae32cd074dc667f1ace6083273b1870)

Change-Id: I8ca4d94d838a00ea7c10423ab120329bf1b2343f
Reviewed-on: http://git-master/r/62573
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R1bb4b36226f8a7c13166162feabeced9a1d469ee

5 years agoArm: Tegra: Cardhu: Set slew rise/fall rates properly
Pavan Kunapuli [Wed, 14 Sep 2011 13:40:53 +0000]
Arm: Tegra: Cardhu: Set slew rise/fall rates properly

Setting the slewrise and slewfall rates properly.

Bug 811303

Reviewed-on: http://git-master/r/52367
(cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031)

Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836
Reviewed-on: http://git-master/r/62326
(cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9)
Reviewed-on: http://git-master/r/63813
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e

5 years agoARM: tegra: power: Update CPU rate after mode switch
Alex Frid [Sun, 30 Oct 2011 04:12:44 +0000]
ARM: tegra: power: Update CPU rate after mode switch

Update Tegra3 CPU clock rate after G=>LP mode switch is completed to
synchronize with cpufreq target rate.

(cherry picked from commit 870d21e5e23eff476cdd841b4ce2605393d638ef)
(cherry picked from commit 11b20d7d6206c557f00e3f7a40dec1d498345d79)

Change-Id: I62237b8d34be23a8d903937f2ebb2d395c5db1b9
Reviewed-on: http://git-master/r/63359
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rdd1548389896521fddb2e239d6236706eb102f73

5 years agoARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP mode
Alex Frid [Wed, 26 Oct 2011 06:36:26 +0000]
ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP mode

Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero,
which could happen only while CPU is in LP mode (and CPU regulator
output is turned off by side-band signal, anyway):

- Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero
- Allow VDD_CPU one step change to zero (i.e., to minimum voltage set
by constraints) after entry to LP mode
- Allow VDD_CPU one step change to the predicted G mode target before
exit from LP mode

(cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872)
(cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827)

Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1
Reviewed-on: http://git-master/r/63357
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94

5 years agoARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table
Alex Frid [Wed, 2 Nov 2011 02:39:15 +0000]
ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table

Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This
field will be supported starting with table revision to 3.2, and it
will allow to enable/disable DSR for each table entry independently.

Bug 853990

(cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac)
(cherry picked from commit c7ebe73da695206a992088a4ba5a6cd7643ea333)

Change-Id: I212d5992067baffaaf5b2e1de25b103c7b1fb56a
Reviewed-on: http://git-master/r/63356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7261d49b023634a783ab2bd55f494112d0bac2a1

5 years agoARM: tegra: gpio: Add range check for gpio enable/disable
Chaitanya Bandi [Thu, 3 Nov 2011 10:43:18 +0000]
ARM: tegra: gpio: Add range check for gpio enable/disable

Added the range check into tegra_gpio_enable and tegra_gpio_disable

Bug 897387

Reviewed-on: http://git-master/r/62641
(cherry picked from commit 091b3906b2dd64cd58221e7e61a24a57dabad16c)

Change-Id: I9be8129397a1dccbea4a04f6b6ed7d4529bf45c3
Reviewed-on: http://git-master/r/63174
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rfaf0efdbc60208a56e4e4f073e3661ad1511694c

5 years agoarm: tegra: power: set throttling temperature = 85C
Diwakar Tundlam [Fri, 2 Sep 2011 17:38:24 +0000]
arm: tegra: power: set throttling temperature = 85C

Earlier value of 75 had unnecessary double guardbanding.
Changed 90C row in EDP table down to 85C to get throttling alert.

Bug 862301

Reviewed-on: http://git-master/r/50544
(cherry picked from commit 9f2693a80274bcd9eb8e7424bca87f34cc190741)

Change-Id: If7204150013e7894fc310a2f7e8fd46baf11d869
Reviewed-on: http://git-master/r/62773
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6dacf9402de8edbb02bddb08b138808628b7eb15

5 years agoARM: tegra: uart: Restore FCR in uart resume
Pradeep Goudagunta [Fri, 4 Nov 2011 10:25:01 +0000]
ARM: tegra: uart: Restore FCR in uart resume

Restore FCR while resuming debug uart, to enable RX and TX FIFOs with
trigger levels configured during initialisation of debug uart port.

Bug 867063

Change-Id: I9665ff29a53c3e2e6c78a3037e20e7362a642f77
Reviewed-on: http://git-master/r/62411
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Ra3b9858456b952ab539a36019a55863077094054

5 years agoARM: tegra: power: Correct PL310 virt addr calculation
Puneet Saxena [Thu, 3 Nov 2011 10:01:23 +0000]
ARM: tegra: power: Correct PL310 virt addr calculation

PL310 virtual address was calculated using PPSB virtual/phy address.
It should be done using CPU virtual/phy address. This causes
TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's
Vmalloc region on whistler.

Bug 881831
Bug 867094

Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/62097
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f