5 years agoARM: tegra11: clock: Set wait count after EMC clock change
Alex Frid [Sat, 22 Jun 2013 07:29:23 +0000]
ARM: tegra11: clock: Set wait count after EMC clock change

Unconditionally update EMC_ZCAL_WAIT_CNT after EMC clock change.

Bug 1312928

Change-Id: I35a24757ed8f2cbca73393fb0d95533491524b3f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241212
(cherry picked from commit a0919e7dbba0a39fabbfd48f8270c72288b1240c)
Reviewed-on: http://git-master/r/257681
(cherry picked from commit e04f8cd6055c34a81fa65e415c25b0b8ef84fbe3)
Reviewed-on: http://git-master/r/271886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Add debugfs node for EMC DFS table info
Alex Frid [Sun, 16 Jun 2013 05:08:05 +0000]
ARM: tegra11: clock: Add debugfs node for EMC DFS table info

Bug 1308928

Change-Id: I9b4318a37902c78e61417e62ea1e51687bbf1ea5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239138
(cherry picked from commit 23f6e8484f9565f5f02c26a363b4b5177c9872b9)
Reviewed-on: http://git-master/r/245968
(cherry picked from commit a6a35548781184f998df2c70cc9c30b8f0b02382)
Reviewed-on: http://git-master/r/271885
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: ardbeg: added tshut info for AMS PMU
Diwakar Tundlam [Sat, 7 Sep 2013 01:58:55 +0000]
arm: tegra: ardbeg: added tshut info for AMS PMU

On ardgeb boards with AMS PMU, we need different tshut data to enable
therm-trip with soctherm. Added dynamic detection of PMU type and set
the tshut info.

Bug 1291108

Change-Id: I828cd43b98481f47cec0be8aa6dab4b6581e081f
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/271778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clock: Rename "gpu" to "gpu_ref"
Kaz Fukuoka [Thu, 5 Sep 2013 23:25:24 +0000]
ARM: tegra12: clock: Rename "gpu" to "gpu_ref"

GPU PLL reference clock was mistakenly named as "gpu".

Change-Id: I5083cdfd98795002d46a68806e2c9d41282eb9a4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/271103
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agosecurity: tlk_driver: shared req/param reg SMC
Chris Johnson [Wed, 4 Sep 2013 00:48:59 +0000]
security: tlk_driver: shared req/param reg SMC

Add support for attempting to register the req/param buffers with
TLK. If it fails, we know we're on an older TLK and have to use
phys address to indicate where the buffers are.

If the SMC succeeds, we pass the virtual pointers to the buffers
knowing TLK will map them in and use them directly. This takes
care of the coherency and reduces our dependence on phys addrs.

Once both TLK and kernel changes have been synced up, we'll remove
the legacy support.

Bug 1353314

Change-Id: I1a73ddc66f002f966e80579ac49bbbd3e64a1f72
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/269802
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarch: config: enable nvhdcp for t12x.
Marvin Zhang [Fri, 30 Aug 2013 18:55:15 +0000]
arch: config: enable nvhdcp for t12x.

bug 1347934

Change-Id: I9b7e1ca19e2891515bbce7b4e4640ffa3c4c5423
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/268657
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: dvfs: Don't apply rail maximum limit
Alex Frid [Sat, 7 Sep 2013 00:20:54 +0000]
ARM: tegra: dvfs: Don't apply rail maximum limit

Removed clipping of target rail voltage to maximum limit. No clock
domain should ever request voltage above maximum. If happened it is
a bug, and now it would hit BUG() in regulator core (applying limit
before this change just masked the bug).

Change-Id: Ic482e546cf75aa968a548ba1eaf66ebf28abe861
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271819
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Re-name rail offset variable
Alex Frid [Sat, 7 Sep 2013 00:59:09 +0000]
ARM: tegra: dvfs: Re-name rail offset variable

Re-named rail offset variable from offset_millivolts to dbg_mv_offs,
since it is controlled by debugfs only.

Change-Id: I5b218769c01538b6f152d052ea2e0d409dd5e872
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271818
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Add tegra_dvfs_ prefix
Alex Frid [Sat, 7 Sep 2013 06:32:35 +0000]
ARM: tegra: dvfs: Add tegra_dvfs_ prefix

Added tegra_dvfs_ prefix to public dvfs functions.

Change-Id: I65995465fa79f4554504a4b37fa1e8f83f83ab1c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271817
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dc: updated tegra_hdmi_audio_config table
Emma Yan [Thu, 21 Mar 2013 11:28:42 +0000]
video: tegra: dc: updated tegra_hdmi_audio_config table

Added 241500000 pclk entry for 1440p (2560x1440) HDMI support

Bug 1254995

(cherry picked from commit 87fa6a27e55983e3bb6f472fd05677ca80874dec)
Reviewed-on: http://git-master/r/211936
Change-Id: If68cee3eed532ef06d23e6a967836fde161c3e58
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271897
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: power: Disable CL-DVFS clock on LP1 entry
Alex Frid [Sun, 16 Jun 2013 02:11:15 +0000]
ARM: tegra: power: Disable CL-DVFS clock on LP1 entry

Disabled CL-DVFS logic clock on LP1 entry, and re-enabled it during
resume. If running DFLL is in open loop in LP1, and there is no need
to clock closed loop logic.

Change-Id: I097aa431d99cd24d1dd6a409ad37faecf8f579dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239134
(cherry picked from commit 8b56a79525817fab6e4bc7a6d905f6544d791116)
Reviewed-on: http://git-master/r/240863
(cherry picked from commit adbe3ecbb0d81a8a5eaf548dc209cabdd2f58a51)
Reviewed-on: http://git-master/r/271888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support
Alex Frid [Wed, 24 Jul 2013 02:58:41 +0000]
ARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support

- added dvfs tables for AP40X sku
- set DFLL mode Vmin with 0.9V if designated fuse is set

Bug 1326355

Change-Id: Id604580d02d820db5fcf40f77fd3afd8b9c79f35
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253188
Reviewed-on: http://git-master/r/237072
Reviewed-on: http://git-master/r/257730
(cherry picked from commit 97feb5338870afa3b0c499adc99a5554a488c78f)
Reviewed-on: http://git-master/r/271884
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: power: Add AP40X cpu EDP table
Alex Frid [Thu, 25 Jul 2013 03:46:56 +0000]
ARM: tegra11: power: Add AP40X cpu EDP table

Bug 1326355

Change-Id: I19b0a6dea4712b718477ca76f479fab0ff8b14b5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253187
(cherry picked from commit fdd98a8a7524cfe540a117cc183c9b817a935614)
Reviewed-on: http://git-master/r/257729
(cherry picked from commit eefc0988bdc336000adfe63e0477b928da0425a2)
Reviewed-on: http://git-master/r/271883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: power: Add AP40X core EDP tables
Alex Frid [Wed, 24 Jul 2013 20:51:38 +0000]
ARM: tegra11: power: Add AP40X core EDP tables

Bug 1326355

Change-Id: Ic6932da6da1aa83ce8582d68167ff50f8ea4663a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253186
(cherry picked from commit b0600e1d87f2eb30acd0ebf58baef42288a7222f)
Reviewed-on: http://git-master/r/257727
(cherry picked from commit ab2bf5b822d917b33b7e147fb4c44c6f55edee95)
Reviewed-on: http://git-master/r/271882
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Increase max AMX/ADX clock rate
Alex Frid [Sun, 16 Jun 2013 06:03:06 +0000]
ARM: tegra11: dvfs: Increase max AMX/ADX clock rate

Increased maximum AMX/ADX clock rate from 19.91MHz to 24.73MHz.

Bug 1161126

Change-Id: I637eb483a570a91511ae472053bac5287ac9f92f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239140
(cherry picked from commit d1861462d318d4c6483543f26a1f1bc6e2dc3043)
Reviewed-on: http://git-master/r/241233
(cherry picked from commit 0d4302e2f31caeea4dbce2d3c0379d5eedf57d5c)
Reviewed-on: http://git-master/r/271881
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: Use devfreq scaling for gk20a
Arto Merilainen [Mon, 29 Jul 2013 11:38:10 +0000]
ARM: tegra12: Use devfreq scaling for gk20a

This patch disables perfmon frequency scaling and enables devfreq
scaling on gk20a.

Bug 1330780

Change-Id: Ia4081128389f93f16ca7ed35aa5c4e2a956ddade
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/263239
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Use pod governor
Arto Merilainen [Mon, 9 Sep 2013 10:19:58 +0000]
video: tegra: host: gk20a: Use pod governor

This patch sets nvhost_pod to be the default devfreq governor for
gk20a.

Bug 1330780

Change-Id: I6b594b3e1c7ea0e76a36a68045fc0a94321e8d27
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/271995
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Don't duplicate freqs
Arto Merilainen [Mon, 9 Sep 2013 05:46:55 +0000]
video: tegra: host: gk20a: Don't duplicate freqs

gk20a clock frequencies used to be doubled in the clock structure.
This, however, has been changed and therefore the gk20a devfreq
profile has currently too small frequencies.

This patch modifies the scale profile to use clock structure
frequencies "as is".

Bug 1330780

Change-Id: I278c3ab5de23be6dc3c528122b7420aa188947c0
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/271933
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: PMC: tegra12: enable IO DPD function for T124
Terry Wang [Thu, 29 Aug 2013 06:36:08 +0000]
ARM: PMC: tegra12: enable IO DPD function for T124

Enable PMC IO DPD function for T124.

Bug 1352773

Change-Id: I18387f8054957745bf3f7de70e9e5fa4ce581cb7
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/267755
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hunk Lin <hulin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: palmas: provide enable_time through desc instead of callback
Laxman Dewangan [Sat, 7 Sep 2013 09:00:43 +0000]
regulator: palmas: provide enable_time through desc instead of callback

Change-Id: I48184f33f3e1bcc9fac1fe74d00601edd1364957
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271823
GVS: Gerrit_Virtual_Submit

5 years agoregulator: palmas: remove unused macros
Laxman Dewangan [Sat, 7 Sep 2013 08:53:12 +0000]
regulator: palmas: remove unused macros

Some macro defined on the driver file is no more used. Removing
such macros.

Change-Id: I3b2d837d595b012f9731f4e4f71d7de80cb66ce2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271822
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoRevert "media:video:tegra: add HDR for ar0261"
Mitch Luban [Sat, 7 Sep 2013 20:50:27 +0000]
Revert "media:video:tegra: add HDR for ar0261"

This reverts commit 9de14ad78781f63ed2306f7c6f7c1f328e41e132.

Change-Id: I263a614a5afe1eee17cda5e251510e0a205d7256
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/271842
Reviewed-by: Automatic_Commit_Validation_User

5 years agoiommu/tegra: smmu: smaller preempt latency for map_pages
Hiroshi Doyu [Fri, 6 Sep 2013 10:31:32 +0000]
iommu/tegra: smmu: smaller preempt latency for map_pages

Take smaller preemption latency for map_pages since there's not much
perf improvement on this larger lock range.

Bug 1290869

Change-Id: Ic7579fe9ffe89d01ad6e7fc3e18404b742b38b50
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/271447
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoRevert "iommu/tegra: smmu: fix perf regression with map_sg"
Hiroshi Doyu [Fri, 6 Sep 2013 10:26:09 +0000]
Revert "iommu/tegra: smmu: fix perf regression with map_sg"

This reverts commit da57b0c27246871c93f5e541ba8803de95c311bf.

No perf improvement but better to have smaller preemption latency.

Bug 1290869

Change-Id: I368381c82f42ef0baf9cdd573f97ea9e9724923a
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/271446
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Replace nvmap heap management
Vandana Salve [Mon, 2 Sep 2013 14:16:46 +0000]
video: tegra: nvmap: Replace nvmap heap management

Replace nvmap heap management functionality with DMA coherent APIs
Bug 898152

Change-Id: Ia632c23c3ee86bb6017d9cb1b4280d356c2b977b

Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Change-Id: I95c9bd013841f018cf9e706b3e82a804a4a0554a
Reviewed-on: http://git-master/r/269517
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoregulator: palmas: add DT support
Laxman Dewangan [Fri, 6 Sep 2013 11:24:41 +0000]
regulator: palmas: add DT support

Add DT support for palmas regulators.

Change-Id: Ia453390de433a0bc9ca75daf2afe55523b415726
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271501

5 years agoregulator: palmas: cleanup in the roof floor and ext control handling
Laxman Dewangan [Fri, 6 Sep 2013 11:15:14 +0000]
regulator: palmas: cleanup in the roof floor and ext control handling

Use sparte ops struture for the smps which is controlled externally
and get rid of the roof_floor storage.

Change-Id: I444fd7845766d48c5215ebaf09f954b30589dda8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271500
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: use ARRAY_SIZE() to check bounds
Diwakar Tundlam [Thu, 5 Sep 2013 22:21:14 +0000]
arm: tegra: use ARRAY_SIZE() to check bounds

Bug 1291108

Change-Id: I81c29b46481c90956acf3ff4f027cf6abdfb2338
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/271073
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoARM: tegra12: dvfs: Add GPU rail Vmin thermal floor
Alex Frid [Fri, 6 Sep 2013 03:49:59 +0000]
ARM: tegra12: dvfs: Add GPU rail Vmin thermal floor

Implemented Tegra12 GPU rail Vmin floor 0.9V when temperature is
below 20C.

Bug 1273253
Bug 1342499

Change-Id: I5e8fce0c798145d5682c9e60c219e7f603703324
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271329
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: dvfs: Use common rail thermal profile init
Alex Frid [Fri, 6 Sep 2013 00:13:46 +0000]
ARM: tegra: dvfs: Use common rail thermal profile init

Moved dvfs rail thermal profiles initialization to common tegra
dvfs code.

Change-Id: Iae26a9704135479bce90e108104af8569bb87848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271328
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: use general clock framework for GPU throttling
Hyungwoo Yang [Thu, 5 Sep 2013 23:51:41 +0000]
ARM: tegra: use general clock framework for GPU throttling

Bug 1363262

Change-Id: Ic455507d191a5b980d8d54580048c2dbb7b828df
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/271123
Reviewed-by: Philip Rakity <prakity@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: ardbeg : update thermal throttling table
Hyungwoo Yang [Fri, 23 Aug 2013 20:26:53 +0000]
arm: tegra: ardbeg : update thermal throttling table

Bug 1315460

Change-Id: I47c99888eef8c6e92e9a74c8fa8c2592ccabc2f0
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/265680
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra12: clock: Add "PERIPH_ON_APB" to HDA
Sang-Hun Lee [Fri, 6 Sep 2013 01:16:58 +0000]
ARM: tegra12: clock: Add "PERIPH_ON_APB" to HDA

Added "PERIPH_ON_APB" flag to HDA clocks.

Bug 1353286

Change-Id: Ia99fcaa18419fe8894b401d218e57727a867ec14
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/271279
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: tegra: loki: update smps123 for gpu
Ray Poudrier [Fri, 6 Sep 2013 17:50:45 +0000]
ARM: tegra: loki: update smps123 for gpu

Because GPU regulator was programmed out
of range, we were falling back to SW rendering

Bug 1362416

Change-Id: I27859ea2e1e32b121610abb3bad0b168847c2907
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/271564
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Siddardha Naraharisetti <siddardhan@nvidia.com>
Reviewed-by: Tao Xie <txie@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: nvmap: fix comment
Alex Waterman [Thu, 5 Sep 2013 21:40:28 +0000]
video: tegra: nvmap: fix comment

Fix up the punctuation and clarity of the comment for
__nvmap_validate_id_locked().

Change-Id: Ie8cf12093d5b83107c7802eb1266d87333f5b683
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/271049
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Fix virt mem checks
Alex Waterman [Thu, 5 Sep 2013 21:38:45 +0000]
video: tegra: nvmap: Fix virt mem checks

Make it so that __nvmap_free_sg_table() does no error checking
and that nvmap_free_sg_table does all the error checking.

Change-Id: I4e9a8953b278c9317c4baa7d3ec0daeff455e981
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/271047
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: gk20a: enable elpg.
Kevin Huang [Tue, 6 Aug 2013 17:59:32 +0000]
video: tegra: gk20a: enable elpg.

Bug 1317989

Change-Id: Ic309b934e26f064569d444e9e552f74fc1dbaddb
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/270397
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clock: Add read fence in delayed writes
Alex Frid [Thu, 5 Sep 2013 03:02:35 +0000]
ARM: tegra: clock: Add read fence in delayed writes

Added explicit read fence after clock register writes that include
propagation delay. This is necessary on Tegra11 and Tegra12 platforms
where udelay implementation is based on CPU arch timers (on platforms
that use tegra microsecond timer for udelay, timer count read serves
as a fence).

Change-Id: I56a9af1bfa5ae7a9f6f51d129708eaa5cbd8ee27
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270481
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: gk20a: add ZBC save and restore.
Kevin Huang [Tue, 6 Aug 2013 17:51:22 +0000]
video: tegra: gk20a: add ZBC save and restore.

Save all ZBC entries once after PMU initialization. Save valid
entries afterwards.

Bug 1317989

Change-Id: I2cfd264e33125894d495f19f0e22be0dd593c502
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/269680
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: change HDMI prod settings
Xue Dong [Fri, 6 Sep 2013 00:22:35 +0000]
arm: tegra: change HDMI prod settings

bug 1327251

Change-Id: Iaba928cd2a4d196a466a8ef77432260a8c99cc37
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/271140
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: nvmap: support to findout if client is kernel client
Krishna Reddy [Thu, 5 Sep 2013 18:44:04 +0000]
video: tegra: nvmap: support to findout if client is kernel client

add support to find out if client is kernel client.

Change-Id: Ibc6926583f9ffa24d81c8175141b2d4d758c054a
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/271082

5 years agovideo: tegra: nvmap: remove unused _nvmap_pin
Krishna Reddy [Fri, 6 Sep 2013 00:26:53 +0000]
video: tegra: nvmap: remove unused _nvmap_pin

remove unused _nvmap_pin function

Change-Id: I3ec0f4a32571a169ee2a370c59d31c456d494aa0
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/271141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agopower: bq2419x: do not enable charger of battery is not present
Laxman Dewangan [Fri, 6 Sep 2013 10:08:15 +0000]
power: bq2419x: do not enable charger of battery is not present

If ther is no battery connected then do not enable the charging
functionality.

Change-Id: I15a718082363574e7877823465ce71c36fa6b2c3
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271422

5 years agopinctrl: tegra: add T124 pinctrl driver support
Ashwini Ghuge [Thu, 5 Sep 2013 07:09:33 +0000]
pinctrl: tegra: add T124 pinctrl driver support

Bug 1314143

Change-Id: Icde4053dd719644edf008b94408010a491349e64
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/269423
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: loki: set pinmux for js reset pin
Jun Yan [Tue, 6 Aug 2013 02:39:09 +0000]
arm: tegra: loki: set pinmux for js reset pin

Set it to be HIGH by default as js reset
signal is active LOW.

Change-Id: Ie2904748d540ee70a7b5bf5882a5401fe343fe81
Signed-off-by: Jun Yan <juyan@nvidia.com>
Reviewed-on: http://git-master/r/269862
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: fuse: fix fuse_pgm_cycles error check
Shardar Shariff Md [Thu, 5 Sep 2013 10:50:02 +0000]
arm: tegra: fuse: fix fuse_pgm_cycles error check

fuse_gpm_cycles error check to be checked with 0
instead its checked with non zero value

Change-Id: I473f7185b7929b0aaa38bcb6b8c2210373bbc895
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/270769
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Chang <kenc@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: palmas: Correct vbus detect pin name
Pradeep Goudagunta [Fri, 6 Sep 2013 06:34:53 +0000]
ARM: tegra: palmas: Correct vbus detect pin name

Correct palmas vbus detect pin name in ardbeg and macallan.

Bug 1362846

Change-Id: Idedc599cd877ef657e6750317642ca948543c014
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/271349
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: tn8: Disable panel rst before suspend
Jiukai Ma [Tue, 3 Sep 2013 11:40:22 +0000]
arm: tegra: tn8: Disable panel rst before suspend

LCD_BL_EN is not used on TN8, disable dsi_panel_rst_gpio before suspend.

bug 1353663

Change-Id: Iefa6df02308be44761f12352acdbe3fe23de8187
Signed-off-by: Jiukai Ma <jiukaim@nvidia.com>
Reviewed-on: http://git-master/r/269497
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agopower: bq2419x-charger: add thermal zone name
Venkat Reddy Talla [Thu, 5 Sep 2013 11:45:24 +0000]
power: bq2419x-charger: add thermal zone name

add thermal zone name for BQ2419x charger chip

 Bug 1339831

Change-Id: Ib84189246db3d28059acb419884dd15d46cc1c0c
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/270808
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: palmas: split SMPS10 out to two regulators
Laxman Dewangan [Thu, 5 Sep 2013 13:17:34 +0000]
regulator: palmas: split SMPS10 out to two regulators

The SMPS10 has two outputs, smps10-out1 and smps10-out2.
SMPS10-OUT1 is connected to smps10-out2 through switch and
smps10-out2 is conncted to input through boost/bypass.

As there is physically two outputs, split the SMPS10 regulator
into two regulators, smps10-out1 and smps10-out2.

Change-Id: I1dea345dcffa0e9d167d949cc69172864d331f7b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270870

5 years agoxhci: tegra: fix host partition powergate sequence
JC Kuo [Wed, 14 Aug 2013 10:05:37 +0000]
xhci: tegra: fix host partition powergate sequence

System hang observed during elpg entry/exit stress test. Root cause
is that xhci-tegra doesn't follow host partition powergating sequence
illustrated by PG. "flushing MCCIF and partition clients" needs to be
done before assserting RESET and disabling partition clocks.

This change fixes the sequence by removing fews steps since those are
supposed to be done by tegra_powergate_partition().

bug 1348646

Change-Id: Iae82e5cba2b5ceb09b6b5e6af6641736dc9ba855
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/267292
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>

5 years agoarm: tegra12x: disable secure reg updates
Varun Wadekar [Fri, 30 Aug 2013 05:18:59 +0000]
arm: tegra12x: disable secure reg updates

Non-secure builds cannot write to secure registers and this needs to
be done by the kernel running in the secure world.

Change-Id: Id8bd6a1b58118208acea57c992529e8e75885a1f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/268310
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Long <scottl@nvidia.com>

5 years agosecurity: tlk_driver: rejig switch-to-cpu0 code
Varun Wadekar [Mon, 2 Sep 2013 11:50:05 +0000]
security: tlk_driver: rejig switch-to-cpu0 code

* Try to encompass the duplicate cpu affinity code in
a macro which can be used at multiple places without
code duplication.
* Avoid over-writing saved_regs, while re-entering the
secure world with a FS-complete smc call.
* Remove the fs_ready logic as it is buggy and is not
working as expected.

Change-Id: I916e5ae53d87285e3e3be14647446a22ae795c1c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/269118
Reviewed-by: James Zhao <jamesz@nvidia.com>

5 years agoRevert "Revert "video: tegra: nvmap: Enable dmabuf stashing""
Krishna Reddy [Thu, 5 Sep 2013 23:37:19 +0000]
Revert "Revert "video: tegra: nvmap: Enable dmabuf stashing""

This reverts commit 7d0f8b777619fd95b6d6a6899cb0d819252ac80a.

Change-Id: Ibab957b4045364a788b5e6c173702f3904fb347d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/271104
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: dvfs: Don't squash GPU rates
Alex Frid [Thu, 5 Sep 2013 05:16:18 +0000]
ARM: tegra12: dvfs: Don't squash GPU rates

Updated GPU dvfs table construction to keep all characterized rates
(no longer squashing rates that require the same voltage).

Bug 1273253

Change-Id: I7344010cef6d28e11a8f58b09b9a2cec1a831e68
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270562
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: nvmap: fix race conditions in dmabuf stashing
Krishna Reddy [Thu, 5 Sep 2013 05:58:47 +0000]
video: tegra: nvmap: fix race conditions in dmabuf stashing

fix race conditions in dmabuf stashing code by taking lock at
correct place.
fix error checking during kmem_cache_alloc.
fix incorrect evict of map under use during dir mismatch.
Bug 1356091
Bug 1290869

Change-Id: Iafd159646a551579f4518a7535d86cb1248432b9
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/270564

5 years agoxhci: tegra: fix DFE/CTLE control sequence
joyw [Wed, 28 Aug 2013 11:03:25 +0000]
xhci: tegra: fix DFE/CTLE control sequence

According to PG to adjust DEF and CTLE context save/restore
programming sequence.

Bug 1345950

Change-Id: I0925f635347c322b96db7a13c9121b707611b97d
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/267288
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clock: Add user interfaces for GPU clock
Alex Frid [Tue, 27 Aug 2013 06:02:59 +0000]
ARM: tegra12: clock: Add user interfaces for GPU clock

Added nodes to limit and read GPU clock rate:

sysfs (limit level and rate in Hz, state ref-counted):
/sys/kernel/tegra_gpu/gpu_cap_level
/sys/kernel/tegra_gpu/gpu_cap_state
/sys/kernel/tegra_gpu/gpu_floor_level
/sys/kernel/tegra_gpu/gpu_floor_state
/sys/kernel/tegra_gpu/gpu_rate
/sys/kernel/tegra_gpu/gpu_available_rates

PM QoS (freq in kHz):
/dev/gpu_freq_max
/dev/gpu_freq_min

Bug 1349108

Change-Id: Iead80fa9a3e208a6235caac46092bd4e5e7bfa1d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/267703
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoPM QoS: Add GPU frequency limits to PM QoS
Alex Frid [Tue, 23 Jul 2013 04:26:11 +0000]
PM QoS: Add GPU frequency limits to PM QoS

Added GPU frequency min/max as PM QoS classes.

Bug 1330780

Change-Id: I2428c62748521c17e23b2df9ca409deda8b36160
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/267702
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: clock: Register arch timer delay early
Alex Frid [Wed, 4 Sep 2013 22:54:27 +0000]
ARM: tegra: clock: Register arch timer delay early

Registered ARM arch timer as delay timer early, so that udelay() calls
provide proper delays for initial clock table settings.

Bug 1356220

Change-Id: I98021507d0bcf129179c97ce395cb7edf2c682e4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270411
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: clean up warnings and #if expression
Jon Mayo [Wed, 4 Sep 2013 19:16:51 +0000]
video: tegra: clean up warnings and #if expression

Clean up several warnings and fix a #if to use || instead of &&.

Change-Id: I23a63e2cb0125a3856d86c4da52d1b13d590118f
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/270240
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: mach_tegra: fix warnings soctherm
Philip Rakity [Wed, 4 Sep 2013 12:32:16 +0000]
arm: mach_tegra: fix warnings soctherm

use correct types
fix format warnings

Change-Id: I1a0a646ca56e810e4ce7d022f6bc148d99fd3841
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/270685
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: isomgr support for T124
Xue Dong [Wed, 21 Aug 2013 23:43:00 +0000]
arm: tegra: isomgr support for T124

bug 1162232

Change-Id: I342b8d9ede5d55fd16228d0ae08ce55ee2b26f42
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/264137
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: Add emc use case table
Xue Dong [Wed, 21 Aug 2013 01:17:41 +0000]
ARM: tegra12: Add emc use case table

bug 1162232

Change-Id: I2bf4cdec47b98da45852e3fd345dd1833bb020af
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/264134
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: nvmap: remove unused buddy_size var
Vandana Salve [Tue, 3 Sep 2013 09:52:52 +0000]
video: tegra: nvmap: remove unused buddy_size var

Remove the unused buddy_size variable from nvmap_heap_create()

bug 898152

Change-Id: I9a25af749825feca30ef72f11140454600d54bac
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/269467
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoarm: tegra: remove setting of buddy_size in nvmap_platform_data
Vandana Salve [Tue, 3 Sep 2013 10:41:57 +0000]
arm: tegra: remove setting of buddy_size in nvmap_platform_data

Remove the initialization of buddy_size variable in the
struct nvmap_platform_data to remove usage of
buddy heap allocation

bug 898152

Change-Id: I3f94690fa0254650a2c7ac79d201d87e1f61181b
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/269487
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoarm: tegra: soctherm: always do soctherm_init.
Diwakar Tundlam [Tue, 3 Sep 2013 20:19:24 +0000]
arm: tegra: soctherm: always do soctherm_init.

Let the checks in soctherm_init flag ATE revision error thus allowing
access to raw soctherm regs for debugging purposes.

Bug 1291108

Change-Id: I37afa77df0c9b8c5ecf282fc8e8b31ba7291a631
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/269670

5 years agoarm: tegra: restore correct tskin throttling threshold
Diwakar Tundlam [Tue, 3 Sep 2013 20:14:23 +0000]
arm: tegra: restore correct tskin throttling threshold

nct-driver detects skin-tdiode not-present and skips binding the
trip_point to handle board with missing flex connector.

Bug 1345131

Change-Id: I990e95c2cc9ee75c0bae3e57f97d21c26dd6872f
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/269669

5 years agomisc: nct1008: fix unified get_temp api use
Diwakar Tundlam [Tue, 3 Sep 2013 18:31:51 +0000]
misc: nct1008: fix unified get_temp api use

Removed duplicate get_temp api that was not taking offset table into
account which can cause confusion.

Check invalid temp readout on skin sensor before binding to
skin-balanced throttling cooling device.

Rearrange debug output to show similar items together.

Bug 1330895
Bug 1345131

Change-Id: I8c72f1c8d348e195e02baff3d5dfb7b8718d2c62
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/269668
Reviewed-by: Jinyoung Park <jinyoungp@nvidia.com>

5 years agoarm: tegra: enable therm_trip with soctherm
Diwakar Tundlam [Thu, 22 Aug 2013 18:29:34 +0000]
arm: tegra: enable therm_trip with soctherm

Bug 1291108

Change-Id: I0aaed6b574e64d3200438d831b2320d50da9ccd0
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/266926
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>

5 years agovideo: tegra: Improve hdmi worker
Jon Mayo [Thu, 5 Sep 2013 01:17:40 +0000]
video: tegra: Improve hdmi worker

original change by Mike J. Chen <mjchen@google.com>, but some changes
were made to bring it onto the newer kernel.
- fixed checkpatch warnings.
- used rt_mutex instead of spinlocks, as irq handler is threaded.

original commit message below:

It's now a full blown state machine.  Ported from similar work
we did for OMAP.  Handles TV's that occassionally drop HPD
briefly.

This also fixes a deadlock that could happen because the
old worker function grabbed the dc->lock, but then later
calls a function that grabs the fb lock.  FB_BLANK ioctl
grabs the same locks but in the oppossite order.  The
new worker thread does not grab the dc->lock.

Change-Id: Id5f54d934041e02859c92b9484ff08f4117c33b8
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/270245

5 years agoARM: tegra: sdhci: Pass boot vcore in plat data
Pavan Kunapuli [Fri, 16 Aug 2013 09:25:46 +0000]
ARM: tegra: sdhci: Pass boot vcore in plat data

Pass boot core voltage limit through platform data.
Enable nominal voltage tuning support for pluto.

Bug 1330567

Change-Id: Ia1c349bcf22cb80423d0dd782209fd94dc35b507
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/270146
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra12: config: enable max17048 config
Venkat Reddy Talla [Thu, 5 Sep 2013 11:52:36 +0000]
ARM: tegra12: config: enable max17048 config

Bug 1339831

Change-Id: I1f2b7b1646ec5f7f5eb4f4b2ee266657d820ff1f
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/270811
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agopower: max17048: initialize after thermal zone
Venkat Reddy Talla [Thu, 5 Sep 2013 11:50:47 +0000]
power: max17048: initialize after thermal zone

use fs_initcall_sync to initialize max17048_init
after thermal zone framework to avoid power supply
register fail for battery type.

Bug 1339831

Change-Id: I2db1e14951d47640ecc14cca95ad4144e8f5948c
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/270810
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: TN8: add INI data for max17048
Venkat Reddy Talla [Thu, 5 Sep 2013 11:47:15 +0000]
ARM: tegra: TN8: add INI data for max17048

Bug 1339831

Change-Id: Id31c75e4d092cdb57a07b8b5bf1286227b3c49cb
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Reviewed-on: http://git-master/r/270809
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: palmas: use regulator_regmap for ldo regulator ops
Laxman Dewangan [Thu, 5 Sep 2013 09:46:16 +0000]
regulator: palmas: use regulator_regmap for ldo regulator ops

Use generic regulator regmap api for the LDO regulator
operation to enable/disable/is_enable/set_voltage/get_voltage.
This removes the code from driver and make code simple.

Change-Id: I616b323c496c899ccad93ce6181619c28aa17658
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270706

5 years agoregulator: palmas: use regulator_regmap for external regulator ops
Laxman Dewangan [Wed, 4 Sep 2013 14:09:25 +0000]
regulator: palmas: use regulator_regmap for external regulator ops

Use generic regulator regmap api for the external regulator
operation to enable/disable/is_enable. This removes the code
from driver and make code simple.

Change-Id: Idfd70bea1fd1cafa3c6ccf95692b9a8490c6e7f1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270705

5 years agoregulator: palmas: use regulator_regmap for charge-pump regulator ops
Laxman Dewangan [Wed, 4 Sep 2013 13:45:13 +0000]
regulator: palmas: use regulator_regmap for charge-pump regulator ops

Use generic regulator regmap api for the charger pump regulator
operation to enable/disable/is_enable. This removes the code from
driver and make code simple.

Change-Id: I5efa3d6a7d531cb89283cd6d56264855e32a05b6
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270704

5 years agommc: tegra: Clear tuning overrides if not required
Pavan Kunapuli [Thu, 22 Aug 2013 15:22:06 +0000]
mmc: tegra: Clear tuning overrides if not required

If there is no need to maintain boot voltage, clear tuning
override voltages set.

Bug 1353926

Reviewed-on: http://git-master/r/264940
(cherry picked from commit f5b46bfe2d3d345d1c932558a6e81091bf0ed907)

Change-Id: Ie36fd98b6245839ea8ec4b6fd9a2afb4cd56ff3b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/270147
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agommc: tegra: Refactor frequency tuning code
Pavan Kunapuli [Fri, 16 Aug 2013 14:07:38 +0000]
mmc: tegra: Refactor frequency tuning code

Chip specific tuning frequency list.
Support low, high and max frequencies for each chip.
Generic tuning constraints update procedure for better scalability.

Synchronization between multiple devices for setting core voltage
constraints during tuning.
Check if tuning mutex is held before starting any data transfers. This
would avoid transfers when tuning changes the core voltage. This would
avoid data errors due to core voltage fluctuations as a result of tuning
vcore constraints. This check needs to be extended to any ongoing
transfers.

Fixed tuning status update as per the core voltage set status and tuning
window status.

If the verification of an already tuned best tap value fails, force
retuning.

Option to easily configure support for any two frequencies when DFS is
enabled. Simplified procedure to support higher tuning frequency count.

Modularize tuning code for better scalability, maintainability and
readability.

Bug 1330567

Reviewed-on: http://git-master/r/260568
(cherry picked from commit 8c226304c0e23a7609013846921fb2728dd95a96)

Change-Id: I98533a3ceb661b5b54c8903341181ad0009f4dfb
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/270145
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agommc: core: core.c fix compile warnings
Philip Rakity [Mon, 22 Jul 2013 10:00:04 +0000]
mmc: core: core.c fix compile warnings

Change-Id: I950fd9e7424fcbf072d36c191e4eb42bc28362d0
Signed-off-by: Philip Rakity <prakity@nvidia.com>
(cherry picked from commit 3da3329eeeb7eff6f125c363b535633270a3ad8e)
Reviewed-on: http://git-master/r/269597
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: Enable IRQs before attempting to read user space in __und_usr
Catalin Marinas [Tue, 20 Aug 2013 17:37:02 +0000]
arm: Enable IRQs before attempting to read user space in __und_usr

The Undef abort handler in the kernel reads the undefined instruction
from user space. If the page table was modified from another CPU, the
user access could fail and do_page_fault() will be executed with
interrupts disabled. This can potentially deadlock on ARM11MPCore or on
Cortex-A15 with erratum 798181 workaround enabled (both implying IPI for
TLB maintenance with page table lock held).

This patch enables the IRQs in __und_usr before attempting to read the
instruction from user space.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Change-Id: Ie5164d8ada9646d723b2b6ef65797e9307718292
Reviewed-on: http://git-master/r/264300
(cherry picked from commit 099ae886a528059cdda926ce1701caaaeaa9e0e8)
Reviewed-on: http://git-master/r/270036
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: host: Support physical addresses
Terje Bergstrom [Thu, 29 Aug 2013 09:17:28 +0000]
video: tegra: host: Support physical addresses

Support physical addresses in nvhost_memmgr interface. This is needed
to support carveout memories.

Change-Id: Iaa6c5a33fde20db9d3c4f2cf0778371cce07da2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/270080
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agommc: tegra: Add OCR mask for 3V3.
Ashwin Joshi [Wed, 4 Sep 2013 10:20:00 +0000]
mmc: tegra: Add OCR mask for 3V3.

Add a new OCR mask for 3.3 V. This is required for Automotive boards.

Bug 1319925

Change-Id: I4e933164abc13087c69b18d2ea9129e7f22fe18c
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/270051
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agostaging: iio: adc: palmas: Correct info_mask configuration
Jinyoung Park [Mon, 2 Sep 2013 14:42:51 +0000]
staging: iio: adc: palmas: Correct info_mask configuration

Correct info_mask configuration.
- Changed info_mask from 0 to IIO_CHAN_INFO_RAW_SEPARATE_BIT.
- Changed info_mask from IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT to
  IIO_CHAN_INFO_PROCESSED_SEPARATE_BIT.

Bug 1356128

Change-Id: I964f3d345a2ac7006610cd1cf06fefe397ae684e
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/270495
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomedia: nvavp: Keep BSEV/VDE clock enabled
Vandana Salve [Wed, 3 Jul 2013 14:11:13 +0000]
media: nvavp: Keep BSEV/VDE clock enabled

Keep clocks BSEV and VDE enabled for Video channel
This is needed for secure key programming which happens
on various video playback operations such as seek to 0 &
toggling full screen mode. Use stay on flag to handle
clock reference for vde/bsev clocks

bug 1307769

Change-Id: I8d0cbb91797ab17d0b671f8bdf6c3db79bd589ce
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/244770
(cherry picked from commit 4550dd38827a0a16a2bff94beacbd9ce6edfa560)
(cherry picked from commit 1d65f96438c31ae28b3921268eb20ba4f1dc46e3)
Reviewed-on: http://git-master/r/269979
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoASoC: codecs: Fix headset detection
Ravindra Lokhande [Wed, 28 Aug 2013 10:36:17 +0000]
ASoC: codecs: Fix headset detection

Ceres ERS and FFD has different headset jack. ERS has closed jack
whereas FFD has open jack. Max97236 fails to detect headset for both.
Added code to check board id and use respective jack detection.

Bug 1332257

Change-Id: I64fd45504a090c08e5465c84fec1826367e828c4
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/267264
(cherry picked from commit 21459e02e3c0ff2d0f5697c99bdad7ddf1295246)
Reviewed-on: http://git-master/r/269585
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoASoC: codec: tlv320aic325x: Remove run time error
Ravindra Lokhande [Thu, 25 Jul 2013 09:11:39 +0000]
ASoC: codec: tlv320aic325x: Remove run time error

remove run time wait bits timedout error

Bug 1305129

Change-Id: I214f32874311d31dd732a5aaa0fa1fe0ff4bd25e
Signed-off-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-on: http://git-master/r/253319
(cherry picked from commit 2cbb323bff442c5292c84117bac0521b63e68dbf)
Reviewed-on: http://git-master/r/269584
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agoARM: tegra12: dvfs: Add DVFS limits for NOR
Ashwin Joshi [Wed, 4 Sep 2013 10:18:38 +0000]
ARM: tegra12: dvfs: Add DVFS limits for NOR

Add DVFS limits for NOR

Bug 1319925

Change-Id: I80f1b8d0946f1fed0027476ae9de6b59bc2f4ba0
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/270050
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agoARM: tegra: Add NOR to T124 fixup table.
Ashwin Joshi [Wed, 4 Sep 2013 10:16:42 +0000]
ARM: tegra: Add NOR to T124 fixup table.

Add NOR entry to T124 fixup table. With this NOR works fine when IOMMU
is enabled. It gives MC errors otherwise.

Bug 1319925

Change-Id: I6e1a5127552c64402c60ab7a36b0f2dc57abedac
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/270049
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agovideo: tegra: dsi: Fix mipi base address
Vineel Kumar Reddy Kovvuri [Thu, 5 Sep 2013 03:52:06 +0000]
video: tegra: dsi: Fix mipi base address

 Fix mipi base address in register dump prints

Change-Id: I1f7763e728322e7f84261f4e41dea21e913bcf29
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/270496
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agovideo: tegra: dsi: Send commands on both links
Vineel Kumar Reddy Kovvuri [Wed, 4 Sep 2013 09:49:51 +0000]
video: tegra: dsi: Send commands on both links

When configured in ganged mode DSI sends panel
commands only on link 1. This patch will enable
commands to be sent on desired link

Bug 1359602

Change-Id: I474d64be041da98bacbf62fc7c0828af63ffa70c
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/270030
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra12: clock: Add interface to set G and LP CPU idle rate
Prashant Gaikwad [Tue, 27 Aug 2013 08:58:11 +0000]
ARM: tegra12: clock: Add interface to set G and LP CPU idle rate

Added interface to set fast and slow CPU idle rate by direct
(i.e., underneath cpufreq governor) clock source control.

This change is port of T114 implementation. T148 implements
these interfaces in different way.

Bug 1349795

Change-Id: Ie4fa646f08feee073e0a96a053667a47257c45f8
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/266692
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Remove extra smmu map/unmap
Terje Bergstrom [Wed, 4 Sep 2013 08:05:07 +0000]
video: tegra: host: Remove extra smmu map/unmap

nvhost_memmgr_smmu_map/unmap was replaced with nvhost_memmgr_pin. Only
one use of old function remains. Replace that with nvhost_memmgr_pin
and remove the old functions.

Change-Id: I28186ce4ee773f22ec8f7cc93851c5b43162cc29
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/269990
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Use IOVA for gk20a page tables
Terje Bergstrom [Wed, 12 Jun 2013 07:20:19 +0000]
video: tegra: host: Use IOVA for gk20a page tables

Use IOVA for gk20a PDEs and PTEs. Add flag for restoring usage of
physical addressing and make it default for simulation platform.

Bug 1306615

Change-Id: Id21a45eec34c3a1c4f7b28a757856c2d07c7dc4e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/269631
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Tested-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agogpio: palmas: fix compilation warning
Laxman Dewangan [Wed, 4 Sep 2013 10:20:51 +0000]
gpio: palmas: fix compilation warning

Fix following comiplation warning:
---
gpio/gpio-palmas.c: In function 'palmas_gpio_input':
gpio/gpio-palmas.c:128:3: warning: format '%d' expects a matching 'int' argument [-Wformat]
gpio/gpio-palmas.c: In function 'palmas_gpio_set_debounce':
gpio/gpio-palmas.c:159:3: warning: format '%d' expects a matching 'int' argument [-Wformat]
gpio/gpio-palmas.c: At top level:
gpio/gpio-palmas.c:140:12: warning: 'palmas_gpio_set_debounce' defined but not used [-Wunused-function]
---

Change-Id: Ieeec586a9ec084d01d6f62fa1fe01a04c5850d05
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/270072

5 years agovideo: tegra: host: Fix truncation of SMMU addrs
Terje Bergstrom [Tue, 3 Sep 2013 18:01:34 +0000]
video: tegra: host: Fix truncation of SMMU addrs

Fix truncation errors on SMMU addresses.

Bug 1306615

Change-Id: Ib9af63e19fac484a2227b696af86e58b4c0c1aa6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/269630
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host fix warning on return type
Philip Rakity [Wed, 4 Sep 2013 17:20:13 +0000]
video: tegra: host  fix warning on return type

nvhost_nvmap_pin returns the pointer or an error
return error if cannot allocate pointer

Change-Id: Ia119bdef8c0834e3ed2698300d7f2c18eab7b3c0
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/270176
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: gk20a: increase ext2priv timeout
Prashant Malani [Wed, 4 Sep 2013 00:40:13 +0000]
video: tegra: gk20a: increase ext2priv timeout

Bug 1351758

Change-Id: I78fbaa85aca20c816f19758980a3446d21abc99c
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/269795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agovideo: tegra: nvhdcp: make inlines as static
Jon Mayo [Wed, 4 Sep 2013 22:12:32 +0000]
video: tegra: nvhdcp: make inlines as static

Headers should use static inline and not inline.

Change-Id: Iad4fe6d848f2129be560b8cc9a500c984caee43a
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/270316