5 years agoARM: tegra: clock: Add Tegra3 emc high voltage bridge
Alex Frid [Wed, 29 Jun 2011 03:50:29 +0000]
ARM: tegra: clock: Add Tegra3 emc high voltage bridge

On Tegra3 platforms emc configurations for DDR3 rates below 300MHz
can not work at high core voltage; the intermediate step (bridge) is
mandatory when core voltage is crossing the 1.2V threshold (fixed for
Tegra3 arch). In addition emc must run above bridge rate if any other
than emc clock requires high voltage.

EMC bridge is implemented as a special emc shared user: its rate is set
once during emc dvfs table initialization; then, the bridge is enabled
or disabled when sbus and/or cbus voltage requirement is crossing the
threshold (sbus and cbus together include all clocks that may require
voltage above threshold - other peripherals can reach their maximum
rates below threshold).

Bug 846693

Change-Id: Ib17448877583453250cf11adf6c5c94dab0fadcf
Reviewed-on: http://git-master/r/39919
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re546be46958b6bf8e491553679b1637eaf3786ff

5 years agoarm: tegra: enterprise: init modem according to modem_id
Steve Lin [Mon, 11 Jul 2011 19:45:06 +0000]
arm: tegra: enterprise: init modem according to modem_id

Init baseband modems according to the modem_id passed from the bootloader.

Bug 842870

Original-Change-Id: Ib8cd37877eb50ac67a337ef20dd6c6f631169578
Reviewed-on: http://git-master/r/39273
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb3484d422dd0fbfbd80ac5ef62fe1aa7fa574c52

5 years agoarm: tegra: fuse: support to burn fuses on the field
Varun Wadekar [Thu, 16 Jun 2011 11:08:30 +0000]
arm: tegra: fuse: support to burn fuses on the field

- follow the new sequence shared by the hardware team
- merge Tegra2 and Tegra3.0 odm fuse burning into a single file

Bug 796825

Original-Change-Id: Ia06d589eba95254a410016dce244375f27e22be0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/38404
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R740d7bd47eaa6231954ae98686272a755a4bce14

5 years agoARM: tegra: clock: Use bus lock to protect shared bus update
Alex Frid [Mon, 27 Jun 2011 21:36:58 +0000]
ARM: tegra: clock: Use bus lock to protect shared bus update

Protected shared bus update with bus lock - common for all shared bus
users (update procedure was already covered by individual shared users
locks, but it did not prevent concurrent access to shared rates list).

Original-Change-Id: Ia0e6886265aff1f624802e0415fe8cecb887b507
Reviewed-on: http://git-master/r/39918
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0e0ee997ce9347470e207910f7b4f6c42143717f

5 years agoARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3
Karan Jhavar [Thu, 9 Jun 2011 21:50:35 +0000]
ARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3

By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions. Also
3D,3D1 and MPE are not powergated at startup.

Original-Change-Id: Ibc74868eb59af7c0e8b5a1ecd78e6f993dd5d3a6
Reviewed-on: http://git-master/r/35955
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra55d87d7d816d7cf0bea0d28e7865fa7760f869f

5 years agoARM: tegra: power: Restore Tegra3 EMC power setting after deep sleep
Alex Frid [Wed, 6 Jul 2011 07:23:49 +0000]
ARM: tegra: power: Restore Tegra3 EMC power setting after deep sleep

Bug 836334

Original-Change-Id: I19587e97af0addc62217466ee977c5afc33a6028
Reviewed-on: http://git-master/r/39854
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R2748dbb3f7308ae491e137062e2b0f940fb8185e

5 years agoarm: tegra: devices: Set emc rate for avp
Prashant Gaikwad [Fri, 8 Jul 2011 09:25:19 +0000]
arm: tegra: devices: Set emc rate for avp

Set emc clock rate for avp client as required by the platform.

Original-Change-Id: I10374e1967cda6a9f497ba0a95bd62c3b58ecc40
Reviewed-on: http://git-master/r/40167
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R54697789f03d9465339029b49cba336cb9592c88

5 years agoARM: tegra: la: Add support for latency allowance.
vdumpa [Tue, 14 Jun 2011 20:20:01 +0000]
ARM: tegra: la: Add support for latency allowance.

Original-Change-Id: Ia6593fd6720e38f9bb0635fabe236675764cee91
Reviewed-on: http://git-master/r/36570
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R338465e38b998b4c6a8bfa4efc89003eac90d8b9

5 years agotegra: clocks: Fix in clock settings
mchourasia [Mon, 27 Jun 2011 06:34:21 +0000]
tegra: clocks: Fix in clock settings

clk_disable_locked should not be called when
clk_enable_locked is failed.

Original-Change-Id: I2524ec0198f62de2487723676ca7657d15757eda
Reviewed-on: http://git-master/r/38273
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R1598bf84619449922c599d611a84dec791047837

5 years agoarm: tegra: cardhu: Fix the issue of boot screen corruption.
Kevin Huang [Wed, 6 Jul 2011 01:27:43 +0000]
arm: tegra: cardhu: Fix the issue of boot screen corruption.

- The issue is due to the corruption of bootloader fb during kernel
initialization. This change reserves the bootloader fb and then
frees it until bootloader fb is copied to fb for Cardhu, Ventana,
Whistler, Enterprise and Aruba.
- Change color depth of Cardhu and Harmony to 32-bit.

Bug 828271
Bug 832016

Original-Change-Id: I05ef5930ee68dcbd672a5cb59b4568a2c88a2e55
Reviewed-on: http://git-master/r/34966
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R92cd2153c44ac907fdf153a028429e7a5fa3fc23

5 years agoarm: tegra: tsensor: driver instantiation
Bitan Biswas [Fri, 10 Jun 2011 07:39:00 +0000]
arm: tegra: tsensor: driver instantiation

Tegra internal tsensor driver supported for fuse revision 0.8
and above.

Bug 661228

Original-Change-Id: I820f6b5f20c20bb2d1ba04266148f5969ab84444
Reviewed-on: http://git-master/r/36054
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R62574ff1667ad009dcf13f98e00b7af0ecca2016

5 years agoarm:tegra:tsensor: device definitions
Bitan Biswas [Tue, 22 Feb 2011 13:13:43 +0000]
arm:tegra:tsensor: device definitions

Tegra internal temperature sensor addresses defined

Bug 661228

Original-Change-Id: I061ac9e7da3115d1e832e645582353f93378d291
Reviewed-on: http://git-master/r/36119
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R62de8521a55164f582eb2b0f8ad5a83bbc02876c

5 years agovideo: tegra: nvmap: fix GART pin lockups
Kirill Artamonov [Wed, 15 Jun 2011 00:40:32 +0000]
video: tegra: nvmap: fix GART pin lockups

Fix GART lockups caused by fragmentation by evicting
mapped areas from iovm space after unsuccessful array
pinning attempt.

Fix double unpin error happening during interrupted

Fix possible sleep in atomic context in iovmm code
(semaphore inside spinlock) by replacing spinlock
with mutex.

Fix race between handle_unpin and pin_handle.

bug 838579
bug 838073
bug 818058

Original-Change-Id: I420447ffb4e02fb78a7987e22a537eefc16ff524
Reviewed-on: http://git-master/r/36129
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rd7c287d1a2ad3da50188788324ad908e19f34bb8

5 years agoARM: tegra: sysfs write permission for user only
Manoj Gangwal [Fri, 1 Jul 2011 10:09:43 +0000]
ARM: tegra: sysfs write permission for user only

Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
-clock: syncevents

Bug 828100

Original-Change-Id: I14affc209e954a58de055e291093e31dc1dbfe16
Reviewed-on: http://git-master/r/39364
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R97f4eadb711717e788be7c4e4e8993d048cf1428

5 years agoARM: tegra: power: Refactored kernel powergate code
Karan Jhavar [Tue, 17 May 2011 00:00:43 +0000]
ARM: tegra: power: Refactored kernel powergate code

This change provides a centralized location for powergating modules.
It would take care of switching on/off clocks while un-powergating/
powergating modules respectively.

Bug: 814267
Original-Change-Id: Ic80dc517f634c29085c8e089bdaa32c6fd742710
Reviewed-on: http://git-master/r/31776
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Re0c233ed4bacc27feb7b210cddc6ff3e487c528f

5 years agotegra: power: correct LP0 sequence
Jay Cheng [Tue, 16 Aug 2011 18:57:59 +0000]
tegra: power: correct LP0 sequence

Change-Id: I5f548f11059039cbd830be483ecfa0c6671002e7
Reviewed-on: http://git-master/r/47365
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd7ef967c8b40295a04a0447eb8bbc8e2d577a48e

5 years agoARM: tegra: power: setup TTB0 for cacheable memory
Jin Qian [Tue, 16 Aug 2011 02:32:23 +0000]
ARM: tegra: power: setup TTB0 for cacheable memory

Bug 862494

Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3
Reviewed-on: http://git-master/r/47246
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58

5 years agoARM: tegra2: power: fix LP2 statistics reporting
Jin Qian [Tue, 16 Aug 2011 01:07:40 +0000]
ARM: tegra2: power: fix LP2 statistics reporting

Bug 863108

Change-Id: I5cc4e3ba58daeaeb527871026c85bdca5f6362f2
Reviewed-on: http://git-master/r/47232
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R843a5cf74874bad3999bc55caa0eb8cad04cc555

5 years agoARM: tegra: Fix build error when CONFIG_SMP is not selected
Scott Williams [Wed, 17 Aug 2011 18:47:58 +0000]
ARM: tegra: Fix build error when CONFIG_SMP is not selected

Change-Id: I2420730290c7ecb407e6f30c8a6159ceadfabbbe
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47589
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb177b1e8ed9ce89c732319f49525588c5c0dd9d0

5 years agoARM: tegra: Delete obsolete tegra_audio_device declaration
Scott Williams [Wed, 17 Aug 2011 19:19:09 +0000]
ARM: tegra: Delete obsolete tegra_audio_device declaration

Change-Id: I119fdbbc2440f8a7e64e2f3b5cec2ae4b182ee36
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47592
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R891ed7225b634dc01aaf3f13dbe79fc1eae1c27c

5 years agoARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selected
Scott Williams [Wed, 17 Aug 2011 18:49:57 +0000]
ARM: tegra: Fix build error when CONFIG_PM_SLEEP is not selected

Change-Id: I65e18395eef3a36f6dd537d64d98ab970f166460
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47590
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R2643d7665780442e71444999f21d96a508c7a062

5 years agoARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'
Gaurav Sarode [Tue, 16 Aug 2011 09:42:41 +0000]
ARM: tegra: workqueue: Unify spelling of 'freeze'+'able' to 'freezable'

In K39 , 'freezeable' is changed to 'freezable'.
Reference Commit Id 58a69cb47ec6991bf006a3e5d202e8571b0327a4.

Change-Id: Ie3f95db453205c05da4cf4e655ba8b12a126255b
Reviewed-on: http://git-master/r/47487
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R530643b91e8c252eb606ce7e789cfe34101f6edd

5 years agoarm: tegra: Use new platform types
Yudong Tan [Fri, 1 Jul 2011 18:26:17 +0000]
arm: tegra: Use new platform types

This change is needed to support three different platforms, silicon,
 fpga and simulation.

Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce
Reviewed-on: http://git-master/r/36351
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19

5 years agoarm: tegra: Add platform types for Tegra
Yudong Tan [Mon, 13 Jun 2011 20:14:01 +0000]
arm: tegra: Add platform types for Tegra

Change-Id: Ib9ef42efcbc24d1424a1b43e7d4ad46b97255aaa
Reviewed-on: http://git-master/r/36350
Reviewed-by: Yudong Tan <ytan@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R99f25c1b92fe4a9322d83e00c9560fc7ada2b641

5 years agoARM: tegra: clock: Change default sampling period to 12ms
Tom Cherry [Tue, 5 Jul 2011 22:08:53 +0000]
ARM: tegra: clock: Change default sampling period to 12ms

Bug 845349

Original-Change-Id: I0ce1a5da9a80cea6a4e55bc92490e6ae8508e22f
Reviewed-on: http://git-master/r/39704
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rfc2bfc89082778e43d15406b0b5e53bdf845f08e

5 years agoARM: tegra: power: Restore cpufreq governor target
Alex Frid [Sat, 25 Jun 2011 04:06:22 +0000]
ARM: tegra: power: Restore cpufreq governor target

Restored cpufreq governor target frequency on exit from suspend.
Otherwise, CPU would stay at frequency set underneath the governor
by tegra driver on suspend entry.

Original-Change-Id: Iad96c7771bf89b78cdeb3e8f4e2c40b36e845b57
Reviewed-on: http://git-master/r/38390
Reviewed-by: Alex Courbot <acourbot@nvidia.com>
Tested-by: Alex Courbot <acourbot@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R12135cc7f8f940eac1653432786826bf2affec16

5 years agoARM: tegra: clock: Expand Tegra3 shared bus modes
Alex Frid [Fri, 24 Jun 2011 23:22:26 +0000]
ARM: tegra: clock: Expand Tegra3 shared bus modes

Implemented 3 different modes of combining rate requests from shared
bus users :
- SHARED_FLOOR: cumulative floor request is determined by maximum rate
among all users in this mode and minimum bus rate
- SHARED_BW: cumulative bandwidth request is determined by adding rates
of all users in this mode together
- SHRED_CEILING: cumulative ceiling request is determined by minimum
rate among all users in this mode and maximum bus rate

Final shared bus rate is determined as minimum rate between cumulative
ceiling request and maximum of floor or bandwidth cumulative requests.

Up to now shared bus clocks supported only SHARED_FLOOR mode, and this
mode is kept as default mode for all users. Hence, no change in actual
shared bus operations.

Bug 837005

Original-Change-Id: I29f8215ba7bab4998fdd23b74c4f96611f5848fe
Reviewed-on: http://git-master/r/39139
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re9f9f87d58419a6756b7985c59743356c6a634bc

5 years agoARM: tegra: dvfs: Update Tegra3 cpufreq table selection
Alex Frid [Sat, 18 Jun 2011 07:35:46 +0000]
ARM: tegra: dvfs: Update Tegra3 cpufreq table selection

- For selection of cpufreq scaling table used top-most rate in G CPU
dvfs table, instead of G CPU max rate. Commonly the above rates are
the same, however, in case when PMU limitations on core voltage
indirectly (VDD_CPU on VDD_CORE dependency) lower cpu max rate, the
top-most dvfs rate should be used for table selection, and the max
rate clipped to table entry.

- Replaced BUGs in table selection implementation with errors. Thus,
when no table is found cpufreq is not installed, but the system boots
with respective error messages.

- Step up suspend frequency index in cpufreq tables to reduce suspend
entry latency (the selected rate is still low enough to work under
Vmin voltage setting).

Original-Change-Id: I45db19dbf5b48cef80db35663db2df3b68473993
Reviewed-on: http://git-master/r/37415
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R59fb213db14d868bec0ca701e1c73dd9d1918e82

5 years agoARM: tegra: Fixed the wrong 'if' statement.
Jubeom Kim [Mon, 20 Jun 2011 11:39:30 +0000]
ARM: tegra: Fixed the wrong 'if' statement.

Removed the semicolon after 'if'.

(cherry picked from commit 9a118fd001bfbe23a7b825aa66cb19ebe7c12c7c)

Original-Change-Id: I058d58f6bad2ec08cf5a509361dbc3fc52801ce1
Reviewed-on: http://git-master/r/38228
Tested-by: Jubeom Kim <jubeomk@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R1221658aa101f439a88df3cdae8a2d8c9c659cfb

5 years agoarm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLK
Harry Hong [Mon, 20 Jun 2011 04:46:37 +0000]
arm: tegra3: pinmux: Adding SFIO3 mode for VI_MCLK

SFIO3 on VI_MCLK pin is needed to output vi_sensor clk.

bug 839517

Original-Change-Id: Ied7408a8711b0256b8fe98eea67c873a7b168bcb
Reviewed-on: http://git-master/r/37426
Tested-by: Harry Hong <hhong@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>

Rebase-Id: Ra0c9550efc2ff7af8075eaf7962be94f2d299c2b

5 years agoARM: tegra: clock: Add shared bus users rate printout
Alex Frid [Sun, 26 Jun 2011 02:15:28 +0000]
ARM: tegra: clock: Add shared bus users rate printout

Original-Change-Id: Icb1a5028d575155427f1fd7fa5b3ee2a145934f4
Reviewed-on: http://git-master/r/38421
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: Rf473061330e8b6d63948c9a0ed247e37e3534a52

5 years agoARM: tegra: power: trace C states and CPU mode switches
Peter De Schrijver [Wed, 18 May 2011 08:10:08 +0000]
ARM: tegra: power: trace C states and CPU mode switches

Original-Change-Id: I7915d356f18ac830c93b736463406b907d8c1cef
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31958
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R341f7619d11f81fd7dfbab2ceb1c6fdaab6ead78

5 years agoARM: tegra: power: Overlap Tegra3 cpu off delay
Alex Frid [Sat, 14 May 2011 07:11:31 +0000]
ARM: tegra: power: Overlap Tegra3 cpu off delay

Overlap cpu off delay during G-to-LP mode switch with LP mode

Original-Change-Id: I8e93a5af3983e7daad46ae026fc510ce6c2fef99
Reviewed-on: http://git-master/r/31641
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R9260cc70b0fd5cf5266c7331a7b37d045f87fbfd

5 years agoARM: tegra: power: Use CPU LP mode for Tegra3 deep sleep
Alex Frid [Fri, 13 May 2011 05:51:34 +0000]
ARM: tegra: power: Use CPU LP mode for Tegra3 deep sleep

Original-Change-Id: If23b48fb414332f5dd25307a098569a5474283c6
Reviewed-on: http://git-master/r/31471
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6ba9ce7c7b355da4148ce0ebc9bc357bf5fc0b13

5 years agoARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entry
Alex Frid [Fri, 13 May 2011 04:08:34 +0000]
ARM: tegra: power: Idle Tegra3 auto-hoplug on suspend entry

Original-Change-Id: I7f4fb6447c882a54d95ee3fb4c6149f4e0357d69
Reviewed-on: http://git-master/r/31457
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Gerrit_Virtual_Submit

Rebase-Id: Rbe2ac5f11065109d34a04793f93c873441e261be

5 years agoarm: tegra: pinmux: Handling unfitted RSVD pinmux option.
Jin Park [Fri, 17 Jun 2011 06:17:19 +0000]
arm: tegra: pinmux: Handling unfitted RSVD pinmux option.

When call tegra_pinmux_set_func with unfitted RSVD pinmux option,
to prevent unexpected potential problem, handle to finding more
preferred value.

Bug 839423

Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Original-Change-Id: Idf8a1ece4317d14e94a69df0d1c8d450d7762c14
Reviewed-on: http://git-master/r/37185
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>

Rebase-Id: Rfb625aa025048c88c44fd96da1e8b0a3db8d013d

5 years agoARM: tegra: clock: Add Tegra3 AVP activity monitor support
Alex Frid [Thu, 16 Jun 2011 02:03:22 +0000]
ARM: tegra: clock: Add Tegra3 AVP activity monitor support

Added AVP clock control using Tegra3 activity monitoring device.
The target AVP frequency floor is set based on average load and
short term boost. Average AVP load time (time when AVP is not
halted by flow controller) is determined by fixed frequency count
provided by monitoring h/w featuring 1st order IIR activity filter.
The boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled AVP activity has crossed upper/lower boost

The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:

/sys/kernel/debug/tegra_actmon/avp/boost_step - boost rate increase
step (% of max AVP frequency)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/avp/boost_rate_dec - boost rate
decrease factor (%)

/sys/kernel/debug/tegra_actmon/avp/boost_threshold_up - upper
activity watermark for boost increase (AVP active time in %)
/sys/kernel/debug/tegra_actmon/avp/boost_threshold_dn - lower
activity watermark for boost decrease (AVP active time in %)

Original-Change-Id: Ia82247176531f2fb67acfc277e63b9f16916a488
Reviewed-on: http://git-master/r/37175
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R995949fe30f188c16c3fa39e292a2ca56256f2a3

5 years agoARM: tegra: clock: Add Tegra3 EMC activity monitor support
Alex Frid [Sun, 12 Jun 2011 06:29:55 +0000]
ARM: tegra: clock: Add Tegra3 EMC activity monitor support

Added EMC clock control using Tegra3 activity monitoring device.
The target EMC frequency floor is set based on average activity
and short term boost. Average EMC activity is obtained directly
from monitoring h/w featuring 1st order IIR activity filter. The
boost frequency is calculated by s/w - exponentially increasing/
decreasing when sampled EMC activity has crossed upper/lower boost

The implementation is interrupt driven - periodic sampling is hidden
by h/w. The tune-able debugfs parameters are:

/sys/kernel/debug/tegra_actmon/emc/boost_step - boost rate increase
step (% of max EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_inc - boost rate
increase factor (%)
/sys/kernel/debug/tegra_actmon/emc/boost_rate_dec - boost rate
decrease factor (%)

/sys/kernel/debug/tegra_actmon/emc/boost_threshold_up - upper
activity watermark for boost increase (% of current EMC frequency)
/sys/kernel/debug/tegra_actmon/emc/boost_threshold_dn - lower
activity watermark for boost decrease (% of current EMC frequency)

Original-Change-Id: I385c6e0a75da42dada792db6b4018b68fea8f23b
Reviewed-on: http://git-master/r/36790
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R0ac50b162b8e86237986885e115996f755b1e00a

5 years agoARM: tegra: generate status events for all clocks
Peter De Schrijver [Mon, 2 May 2011 12:43:06 +0000]
ARM: tegra: generate status events for all clocks

Original-Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31530
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R25afcccf5ff8d7a88b705ce7f68ab83e818ae1e4

5 years agoARM: tegra: sysfs write permission for user only
Sachin Nikam [Thu, 16 Jun 2011 07:46:26 +0000]
ARM: tegra: sysfs write permission for user only

Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
- tegra_mc_stats: enable and quantum
- susend: mode
- clock: rate, parent, state

File System Permission CTS expects this to pass.

Bug 840409

Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36867
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb

5 years agoARM: tegra: clock: Add clock rate change notification
Alex Frid [Sun, 12 Jun 2011 06:23:50 +0000]
ARM: tegra: clock: Add clock rate change notification

Original-Change-Id: I97434334a4214180a365d9709a331405da135669
Reviewed-on: http://git-master/r/36202
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a

5 years agonvhost: Make 3D workaround Tegra3 A01 only
Terje Bergstrom [Thu, 19 May 2011 06:35:16 +0000]
nvhost: Make 3D workaround Tegra3 A01 only

3D hardware workaround is needed for Tegra3 A01 only. With this patch, we
read run-time whether it should be enabled or not.

Workaround should be removed once A01's have been phased out.

Bug 786316

Original-Change-Id: Icd1b85b30a53c74d2e5c7a6df65a805d1fe5147c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/32136
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Re8e1ee401118339067a622ed7ae32f7f344c94b7

5 years agoARM: tegra: clock: Synchronize Tegra3 clocks scaling
Alex Frid [Sat, 14 May 2011 06:58:33 +0000]
ARM: tegra: clock: Synchronize Tegra3 clocks scaling

On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are
sourced from PLLC through integer dividers. Low resolution of these
dividers does not allow to set scaling frequency levels matching
intermediate voltage steps within core voltage range. Only changing
the source frequency can achieve it. However, re-locking common PLL
while engines are running requires synchronization of engines clock
control, and complex operations including switching to backup sources
during PLL stabilization time.

This commit introduces a new virtual clock "cbus" to support clocks
synchronization and PLLC re-locking procedures. The dvfs table for
cbus clock is constructed from frequency steps close to maximum rates
for each characterized core voltage level. Engine clocks exposed to
the drivers are no longer physical module clocks, but shared cbus
users. Setting the rate for such clock specifies the clock floor.
The final cbus rate is determined as maximum floor setting for all
enabled engines, and rounded up along the cbus dvfs ladder. Actual
engine clock rate is set equal to the cbus clock rate. Hence, engines
will be running close to maximum frequency for minimum voltage that
satisfies all floor requests.

Special case: Host1x. This clock will be always configured at 1/2 of
cbus clock rate, and its shared user floor request is ignored by cbus
target frequency calculations.

Added cbus dvfs tables and updated VDE engine dvfs data.

Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6
Reviewed-on: http://git-master/r/36199
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915

5 years agoarm: tegra: power: fix lp0 resume failure
Luke Huang [Mon, 6 Jun 2011 20:05:44 +0000]
arm: tegra: power: fix lp0 resume failure

Do not check PLLX lock bit on PLLX sanity check, since it might not be in the
lock state yet.

Original-Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3
Reviewed-on: http://git-master/r/35261
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1ea05b0640b93de011109de3402d8810a64defcc

5 years agoARM: tegra: power: use buffered memory for suspend context
Jin Qian [Thu, 11 Aug 2011 22:57:43 +0000]
ARM: tegra: power: use buffered memory for suspend context

use buffered memory to bypass L2
add memory barrier after cpu suspend

Bug 862494

Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe
Reviewed-on: http://git-master/r/47172
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7

5 years agoARM: tegra2: power: Don't disable CPU1 GIC interface in LP2
Scott Williams [Mon, 15 Aug 2011 16:08:06 +0000]
ARM: tegra2: power: Don't disable CPU1 GIC interface in LP2

Leave the GIC processor interface enabled for CPU1 during LP2.
Disabling it prevents CPU1 from waking up on IPIs.

Change-Id: I32ae01066f21f8b4fba1fd0da392bc691c29bf49
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R16db6ca494653a5d8c61cc7ac2b5cb2c3fa9f46f

5 years agoARM: tegra: power: Perform L2 cache sync when flushing L1
Scott Williams [Fri, 12 Aug 2011 17:21:35 +0000]
ARM: tegra: power: Perform L2 cache sync when flushing L1

Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84

5 years agoARM: tegra2: power: Fix reset race condition between the CPUs
Scott Williams [Thu, 11 Aug 2011 20:57:49 +0000]
ARM: tegra2: power: Fix reset race condition between the CPUs

During LP2 for CPU idle on Tegra2, there could be a race condition
between the CPUs. CPU1 cannot autonomously shut itself down (put
itself into reset). CPU1 must be reset by CPU0 but only when it
has no outstanding memory or I/O transactions going on (i.e., it
is in the WFI state). CPU1 indicates its readiness to be reset
by setting status in a PMC scratch register. If CPU1 wakes up
and CPU0 sees CPU1's ready to be reset status before CPU1 can
clear it CPU1 could be reset at inappropriate times resulting
in loss of cache coherency and ultimately a kernel panic.

Eliminate the race condition by ensuring that:

- CPU1's reset ready status is cleared as early as possible
  before CPU1 rejoins the coherent world.
- Use writel when updating the IRAM LP2 status flags to ensure
  the IRAM and coherent memory views of the flags are consistent.
- If there is not enough time remaining for CPU1 to be in LP2 for
  the minimum residency time, clear CPU1's reset status flag
  before entering WFI so that CPU0 will not wait for CPU1 to be
  ready to reset (since it won't be if there is insufficient time).

Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848

5 years agoARM: tegra: timer: Save TWD counter instead of load register
Scott Williams [Wed, 10 Aug 2011 21:18:37 +0000]
ARM: tegra: timer: Save TWD counter instead of load register

In tegra_twd_suspend(), save the remaining count rather than the
initial count of the timer.

Also catch invalid TWD configurations during suspend/restore
(e.g., enabled with a zero count).

BUG 862605

Change-Id: I05bf9e37f922a2b0a48cff23f1aa94ec8e8e039e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6c7e5ae1220faee4564cd751fa6c94f7404ddc27

5 years agoARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2
Scott Williams [Wed, 10 Aug 2011 01:14:11 +0000]
ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2

Don't try to flush the L1 D-cache for an aborted LP2 on the
secondary CPU if the L2 cache is enabled. The L1 cache will have
already been flushed and disabled by the suspend-side code.

Change-Id: If6fc7bd0f7d630e6cdcda6824411503f346c5405
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc50e525a320986432d2b125f82f846f94f605cc3

5 years agoARM: tegra: power: Map the CPU context page to tegra_pgd
Scott Williams [Wed, 10 Aug 2011 01:10:12 +0000]
ARM: tegra: power: Map the CPU context page to tegra_pgd

Add a mapping of the page used to save the CPU context to the
private pgd used during MMU shutdown.

Change-Id: I10ef282ff15ff5ee8469fcaa3637bcb0fb39ba4d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R837a2eb005ad93ef206153b120e972ee65383b65

5 years agoARM: tegra: power: Consolidate PM_SLEEP conditionals
Scott Williams [Wed, 10 Aug 2011 01:05:11 +0000]
ARM: tegra: power: Consolidate PM_SLEEP conditionals

Change-Id: If8f8868d929ec5bebe7c0083e03af504c7a6af11
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rf382a5bf2c7587ad496f2a88deaff75cb609f91c

5 years agoARM: tegra: power: Conditionalize diagnostic register save/restore
Scott Williams [Wed, 10 Aug 2011 01:01:49 +0000]
ARM: tegra: power: Conditionalize diagnostic register save/restore

Change-Id: I540d7272d585331da0241e7878dbb35557f0bb99
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R59fe634cc803ba2c9bb7916046aff5f92120f5c3

5 years agoARM: tegra: power: Fix build errors when DVFS is enabled
Scott Williams [Mon, 8 Aug 2011 20:41:53 +0000]
ARM: tegra: power: Fix build errors when DVFS is enabled

Change-Id: Icc37a1ac4fe1af3d08e579faf35ccb4ab1db1b1c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R786d091cccb765acb8d89acd59017ae993b78733

5 years agoARM: tegra: Fix mutex in atomic context when updating TWD freq
Scott Williams [Sat, 6 Aug 2011 01:16:48 +0000]
ARM: tegra: Fix mutex in atomic context when updating TWD freq

The CPU frequency change notifer runs in an atomic context but
obtaining the current CPU frequency requires taking a mutex because
updating the CPU frequency involves the regulator. Instead of
directly parenting the TWD clock on the CPU clock, make the TWD
a "detached child" of the CPU clock whose rate is updated whenever
the CPU frequency changes.

Change-Id: I49e15f85f269fb3ed0bcaee36ff739b4f064d6b8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7aa10f2576752390464586bc629c972802beb989

5 years agoARM: tegra: power: Rename variables for consistency
Scott Williams [Fri, 5 Aug 2011 01:41:41 +0000]
ARM: tegra: power: Rename variables for consistency

Rename Tegra3 CPU idle handler variables to be the same as their
Tegra2 counterparts for consistency.

Change-Id: I49a03182ff5a15d34847b3837f681ca842dcf643
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc71d7d71bebb197c983180429f24de7708d8dfea

5 years agoARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation
Scott Williams [Fri, 5 Aug 2011 01:35:45 +0000]
ARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation

CPU 0 must wake up before CPU 1 therefore CPU 0 must be awake by
the minimum of its or CPU 1's absolute wakeup time. However, the
the CPU idle request time is a duration not an absolute time.
Change the LP2 sleep time calculation to use an absolute "must
be away by" time.

Change-Id: Ia73dcbe071f81d0bd9fc6c5d860837e606575a8c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R138e6d4ae652932607f7dd411be3aa89ee53e34c

5 years agoARM: tegra: power: Save CPU context to non-cacheable stack
Scott Williams [Thu, 4 Aug 2011 20:32:10 +0000]
ARM: tegra: power: Save CPU context to non-cacheable stack

The standard cpu_suspend does not work if there is an exernal
L2 cache in the system individual CPUs are suspending without
shutting down the whole CPU complex. As a workaround for this
problem, we must save the CPU context to a non-cacheable region
of memory.

Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930

5 years agoARM: tegra: power: Add stack frame debug checks
Scott Williams [Thu, 4 Aug 2011 05:18:31 +0000]
ARM: tegra: power: Add stack frame debug checks

Tag the stack frame created by the CPU register context push
macro with a magic number and validate that magic number in
the register context pop macro to ensure that the stack
remains balanced and uncorrupted.

Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60

5 years agoARM: tegra: power: Define push/pop context register macros
Scott Williams [Thu, 4 Aug 2011 04:44:21 +0000]
ARM: tegra: power: Define push/pop context register macros

Define macros to ensure that the behavior of push/pop of the
context regsiter set is consistent across all callers.

Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4

5 years agoARM: tegra: power: Use uniform save/restore register set
Scott Williams [Thu, 4 Aug 2011 04:38:01 +0000]
ARM: tegra: power: Use uniform save/restore register set

Modify the register usage of tegra_cpu_save so that the same set
of registers is saved to and restored from the stack.

Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59

5 years agoARM: tegra: power: Use standard definitions for SCTLR
Scott Williams [Thu, 4 Aug 2011 03:36:21 +0000]
ARM: tegra: power: Use standard definitions for SCTLR

Change-Id: Ie2f619df4e5bff06960dcaa910a39d4cff78b879
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra75a8dba9e8f0fa57081a3fed9b3ef743b3c8796

5 years agoARM: tegra: power: Consolidate CPU context save and SMP exit
Scott Williams [Thu, 4 Aug 2011 02:07:51 +0000]
ARM: tegra: power: Consolidate CPU context save and SMP exit

Every call to tegra_cpu_save is always followed by a call to
tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save
by folding the CPU context save functionality of cpu_suspend and
the coherency exit functionality into a single function called

Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8

5 years agoARM: tegra: power: Add SMP coherency exit macro
Scott Williams [Thu, 4 Aug 2011 00:33:37 +0000]
ARM: tegra: power: Add SMP coherency exit macro

Define the SMP coherency exit code as a macro to allow it to be
inlined in assembly code that needs to control its register usage.

Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a

5 years agoARM: tegra: power: Delete obsolete function
Scott Williams [Thu, 4 Aug 2011 00:08:54 +0000]
ARM: tegra: power: Delete obsolete function

Deleted tegra3_sleep_cpu which is never called by anything.

Change-Id: I59a737e92ed8bec222cec65252cc19592e171fd6
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1fabb1b9a728f1d4ff99643b4d31cfe7292c260d

5 years agoARM: tegra: Use common coherency exit function for Tegra2
Scott Williams [Wed, 3 Aug 2011 15:59:34 +0000]
ARM: tegra: Use common coherency exit function for Tegra2

Change-Id: Ibbc9c2a38fb654e24b1edb4ee7bbcaf285bf0f7d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R9ff092cf658b71d8f79ef3901bd5067d18548e69

5 years agoARM: tegra: power: Fix suspend pgd identity mapping
Scott Williams [Tue, 2 Aug 2011 20:33:01 +0000]
ARM: tegra: power: Fix suspend pgd identity mapping

The RAM identity mapping in the suspend pgd was based upon the
characteristics of the Tegra2 address map and would not work for
Tegra3. Change the mapping so that it's independent of the physical
address map characteristics.

Change-Id: Ib8f67c169f6b0988e88a4ef7616dfd48e66754ac
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R399b9624e8f25637538273642059e8d0719badf5

5 years agoARM: tegra: power: Allocate non-cacheable page for CPU context
Scott Williams [Tue, 2 Aug 2011 03:38:04 +0000]
ARM: tegra: power: Allocate non-cacheable page for CPU context

The standard cpu_suspend() mechanism doesn't work if there's an L2
cache controller like a PL310 in the system because there's no
effective way to flush the saved CPU context out to the L3 memory
system. Allocate a page of non-cacheable memory to hold the CPU
context. This save area will be utilized in a subsequent change.

Change-Id: I1e3bd60bd0bd19c1010905ef65ea0a8597ad6654
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R00d69f8cab6992ed729c1f6ef67fd38c999c3a5b

5 years agoARM: tegra: power: Put power functions under CONFIG_PM_SLEEP
Scott Williams [Tue, 2 Aug 2011 02:22:02 +0000]
ARM: tegra: power: Put power functions under CONFIG_PM_SLEEP

Place additional functions that are invoked only by code under
CONFIG_PM_SLEEP conditionals under CONFIG_PM_SLEEP conditionals

Change-Id: I224ae07b9031038474b922422422a4feafcd94f1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R65b81ec60f59ae981fd668ad8354b14b8b4c83b9

5 years agoARM: tegra: power: Reorganize CPU idle code
Scott Williams [Sat, 30 Jul 2011 00:45:21 +0000]
ARM: tegra: power: Reorganize CPU idle code

Change-Id: I57653997b7dc059f74e0722b9ea298f3d8a38095
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc8638db0a47faf6fe25976375542fb6eb6326c4c

5 years agoARM: tegra: power: Disable power management if pgd alloc fails
Scott Williams [Sat, 30 Jul 2011 00:38:11 +0000]
ARM: tegra: power: Disable power management if pgd alloc fails

Disable power management functions if we're unable to obtain memory
for our the suspend pgd.

Change-Id: If7900535ea05df9441c0b82ccb9152961ea9e12b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R4b616bb53552d2dd8b9da39ca9bc11ad10825f54

5 years agoARM: tegra: Limit ahb.c to Tegra2
Dan Willemsen [Thu, 4 Aug 2011 21:00:48 +0000]
ARM: tegra: Limit ahb.c to Tegra2

Change-Id: Ia9a67a2ce2c437b115efe7d1f5d69da481208d35
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R866af3fffbba37a2efac84ecfcbd8979d3c3b745

5 years agoARM: tegra: power: cluster control requires CONFIG_PM_SLEEP
Scott Williams [Fri, 29 Jul 2011 23:26:10 +0000]
ARM: tegra: power: cluster control requires CONFIG_PM_SLEEP

Change-Id: I6d395efbd8a83d867e6ac645e232ff95538b7f91
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R08fc23af26e1e1b9daf3de235fdd7df8419013de

5 years agoARM: tegra: power: Add debug checks for LP2 entry/exit
Scott Williams [Fri, 29 Jul 2011 01:31:21 +0000]
ARM: tegra: power: Add debug checks for LP2 entry/exit

Add debug traps for recursive attempts to enter or exit LP2 state.

Change-Id: I7da05774c90a4fd5b9f2369e801c5b447024698f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb74239b3fbabf80cf7548c6f5958b0c540ae6b62

5 years agoARM: tegra: power: Clean up stack pointer handling
Scott Williams [Thu, 28 Jul 2011 04:30:14 +0000]
ARM: tegra: power: Clean up stack pointer handling

Clean up some rather fragile manipulation of the stack pointer in
the CPU suspend code. It's all unnecssary except in one case where
Tegra2 can abort a suspend because of activity on the other CPU.

Change-Id: Ic872364c5abd58f704b2afeeae4d8722f127d3bb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5873dd120df2e98cc5bfcc74f86ebea6cc10f9b2

5 years agoARM: tegra: power: Fix Tegra2 LP2 mode
Scott Williams [Thu, 28 Jul 2011 04:02:36 +0000]
ARM: tegra: power: Fix Tegra2 LP2 mode

All CPUs are not created equal. CPU0 must be the one to perform
the CPU complex suspend actions. CPU complex power gating and rail
gating cannot be triggered from CPU1. The Linux 2.6.39 port for
Tegra2 violates this hardware restriction. While it may have
appeared that the system was entering LP2 state, when entered
on CPU1, essentially all that happened was a WFI with no CPU
complex power gating and no CPU rail gating.

Change-Id: Ie754520264fe8de1b95f523d6575914bf77e747f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R66e19457bc55bcd84124e3a4e23beae7b4ee707c

5 years agoARM: tegra: Handle uniprocessor all CPUs booted status
Scott Williams [Thu, 28 Jul 2011 03:57:45 +0000]
ARM: tegra: Handle uniprocessor all CPUs booted status

For CONFIG_SMP systems that report only a single CPU available,
platform_smp_prepare_cpus() will never get called. Make sure that
tegra_all_cpus_booted is properly set in this case.

Change-Id: I6bf30be02c0b692f0578eb9a19062bcb562c1892
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb800c15e27cff51a091e8e704610ed72572b4b6e

5 years agoARM: tegra: Fix uniprocessor reset handler initialization
Scott Williams [Thu, 28 Jul 2011 03:10:06 +0000]
ARM: tegra: Fix uniprocessor reset handler initialization

- For CONFIG_SMP kernels on systems that only report one CPU available,
  there is never a call to platform_smp_prepare_cpus() which means
  the reset handler would not get initialized. Invoke the reset handler
  initialization from smp_init_cpus() if there is only one CPU.
- For non-CONFIG_SMP kernels, the call to initialize the reset handler
  got accidentally dropped in the port to Linux 2.6.39. Invoke the
  reset handler initiazation from tegra_init_early() in this case.

Change-Id: I782faf84c89d4285aac26bfccb829f27878029de
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R9b35221571885a1620e0d7e19880b05a18c97233

5 years agoARM: tegra: power: CPU complex must be suspended on CPU0
Scott Williams [Tue, 26 Jul 2011 01:31:19 +0000]
ARM: tegra: power: CPU complex must be suspended on CPU0

All CPUs are not created equal. CPU0 must be the one to perform the
CPU complex rail gating action and as such must always be the last
CPU taken down.

Change-Id: I92d1c1c29305d2bf35a15baa43a6d299806482b7
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5ba8fbba2771a2458fcf27d9d49c964ffbe53c88

5 years agoARM: tegra: power: Add LP2 in idle support for secondary CPUs
Scott Williams [Mon, 25 Jul 2011 20:24:13 +0000]
ARM: tegra: power: Add LP2 in idle support for secondary CPUs

Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917

5 years agoARM: tegra: power: Split CPU context save and coherency exit
Scott Williams [Mon, 25 Jul 2011 21:55:25 +0000]
ARM: tegra: power: Split CPU context save and coherency exit

Separate the CPU context save and CPU coherency exit into separate

Change-Id: I7c5376677e293342b02b5bebdef6be2610522936
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d

5 years agoARM: tegra: power: Calculate address of IRAM LP2 mask once
Scott Williams [Mon, 25 Jul 2011 19:56:29 +0000]
ARM: tegra: power: Calculate address of IRAM LP2 mask once

Perform the calcuation of the address of the IRAM copy of the LP2
mask only once because run-time evaluation of it's IO_ADDRESS()
is a rather lengthly computation whose value never changes.

Change-Id: I8456fa3eb719dcf4f42c360196349177b8907fd9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R429d76f341410455883ad7d9e28ff66a44eddb98

5 years agoARM: tegra: timer: Save TWD registers on secondary CPU LP2
Scott Williams [Fri, 22 Jul 2011 22:00:22 +0000]
ARM: tegra: timer: Save TWD registers on secondary CPU LP2

Change-Id: I0ca5186fd833913b79abf2a7dbddc528d547acc6
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Simplify, remove unnecessary macros
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R686b57e37db12361f3c5054500c74337de6fd5a6

5 years agoARM: tegra: power: Save TWD registers on cluster transitions
Scott Williams [Fri, 22 Jul 2011 01:24:34 +0000]
ARM: tegra: power: Save TWD registers on cluster transitions

The ARM timer/watchdog (TWD) registers do not need saving on LP2
transitions resulting from real idle events. They do still need
saving/restoring on transitions resulting from cluster control

Change-Id: I459b25b98c256a52a2e9e68fb63dbf2681e90b07
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R3c7c0cae8b847af6355fa1fa0b8bf5bf1e1efef5

5 years agoARM: tegra: power: Add TWD context save/restore
Scott Williams [Thu, 21 Jul 2011 01:13:59 +0000]
ARM: tegra: power: Add TWD context save/restore

Change-Id: I629f77041ce444dfff32b563795573174afea3a1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R7a21e91127b44461d219a8bfd388f99ba7a72b53

5 years agoARM: tegra3: power: Add LP2 power mode support for CPU 0
Scott Williams [Thu, 21 Jul 2011 23:06:08 +0000]
ARM: tegra3: power: Add LP2 power mode support for CPU 0

Add support for forced Tegra3 LP2 low power mode on the boot processor
(CPU 0) via the cluster control interface when all others are offline.
Switching to the LP CPU mode is also enabled with this change.

LP2 in idle and LP2 mode on the secondary processors is not yet

Change-Id: Icb898729f093be5e006c413f701532dd45228687
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8

5 years agoARM: tegra: power: Clean up cluster control definitions
Scott Williams [Thu, 21 Jul 2011 22:46:01 +0000]
ARM: tegra: power: Clean up cluster control definitions

Reduce the complexity of the cluster control compile-time conditionals.
Also disable DEBUG_CLUSTER_SWITCH because it invokes clock code that
takes a mutex when taking of a mutex is disallowed.

Change-Id: I9b614d4b0189fbb01d0b7f8af7053c7586d9515b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R412820dc2fd9f0c9cc7b1e3ad7ead7e2e68a0ff3

5 years agoARM: tegra: power: Fix CPU complex suspend/resume
Scott Williams [Thu, 21 Jul 2011 21:29:58 +0000]
ARM: tegra: power: Fix CPU complex suspend/resume

- Invoke cpu_pm_enter()/cpu_pm_exit() to save/restore the GIC
  processor interface registers for the last processor standing from
  the cluster control interface.
- Disable the GIC processor interface on the last processor standing
  before shutting down the CPU complex so that wakeup interrupts get
  routed from the legacy interrupt controller to the flow controller.
- For Tegra3 enable GIC pass-through mode to prevent WFI failures.

Change-Id: Ia866b17bef47fc8e9e75d4e353394b2d1a09259c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R249fb53a2622218a7128646d68d8a3552268b4f1

5 years agoARM: tegra: power: Fix incorrect flow controller programming
Scott Williams [Thu, 21 Jul 2011 21:09:39 +0000]
ARM: tegra: power: Fix incorrect flow controller programming

Errors and invalid assumptions about how the flow controller should
be programmed were introduced in the port to Linux 2.6.39.

- Do not touch the flow controller HALT_EVENTS register for any of
  the secondary CPUs in suspend_cpu_complex(). Doing so can cause the
  flow controller state machine to prematurely abort resulting in fatal
  errors when power gating the CPU complex.
- Do not touch the flow controller CSR register for any of the
  secondary CPUs in restore_cpu_complex(). Doing so can cause the
  flow controller state machine to prematurely abort resulting in
  the secondary CPUs waking up before they're supposed to.
- suspend_cpu_complex() and restore_cpu_complex() can only be invoked
  from CPU 0. The hardware does not allow the CPU complex to be
  suspended from any other CPU.

Change-Id: I89546bf53f8f6f12c0e62ce49fc99a46244fa57f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rf61122cb730d852179d8e2d9e667ae7c65b09c58

5 years agoARM: tegra: power: Fix TEGRA_SUSPEND_NONE handling
Scott Williams [Thu, 21 Jul 2011 20:41:18 +0000]
ARM: tegra: power: Fix TEGRA_SUSPEND_NONE handling

- Do not assert in tegra_pm_set() if the platform suspend mode is
  set to TEGRA_SUSPEND_NONE. Just return.
- Do not override the platform suspend mode to a deeper power saving
  mode if the SDRAM refresh context save area cannot be obtained.

Change-Id: I1ebceef715f9175b8db25af3df28c48582ec0815
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rfe888ac904de11cb5a63475dc95ab736a39f5c4b

5 years agoARM: tegra: Add Tegra 3 CPU hotplug support
Scott Williams [Thu, 21 Jul 2011 20:20:20 +0000]
ARM: tegra: Add Tegra 3 CPU hotplug support

Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341

5 years agoARM: tegra: power: Consolidate power management flags
Scott Williams [Thu, 21 Jul 2011 19:24:05 +0000]
ARM: tegra: power: Consolidate power management flags

Consolidate all of the power management control flags in one
header and adjust the values of the software flags so that they
do not conflict with the values of the hardware flags.

Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4

5 years agoARM: tegra: Rename tegra<n>_sleep_reset
Scott Williams [Mon, 25 Jul 2011 22:50:36 +0000]
ARM: tegra: Rename tegra<n>_sleep_reset

Rename tegra<n>_sleep_reset to tegra<n>_hotplug_shutdown since that is
more descriptive of their actual function.

Change-Id: I411e2474bd35a799d5367a182809d17933238612
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R72bf50004ab3fcdde5485b84b7ba008247d1bf4c

5 years agoARM: tegra: power: Align MMU shutdown code to L1 cache line
Scott Williams [Thu, 21 Jul 2011 19:16:18 +0000]
ARM: tegra: power: Align MMU shutdown code to L1 cache line

The MMU shutdown code must be aligned to an L1 cache line boundary.

Change-Id: Ib6c976470983b7f69b45e720104fc65cae54e162
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R305325117ba1debc8d112b4c3596c158df98d75e

5 years agoARM: tegra: Remove obsolete files
Scott Williams [Mon, 25 Jul 2011 22:39:50 +0000]
ARM: tegra: Remove obsolete files

Change-Id: I92b35e1a9966023be98e532de8f89b6b0497a005
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Raf0dfd3a5ae967563885b05c2e8b03916439dfff

5 years agoARM: tegra: power: Disallow LP2 in idle if permanently disabled
Scott Williams [Tue, 19 Jul 2011 21:34:41 +0000]
ARM: tegra: power: Disallow LP2 in idle if permanently disabled

For a variety of reasons, it is possible that LP2 in idle can never
be allowed. If one of these conditions exists, do not allow LP2 in
idle to be re-enabled via the module_param interface.

Change-Id: I980f147844ad9374c218bfb2a25c0d91dad85281
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb897f6dc8245e525fd9ac90c9243e290307c4e58

5 years agoARM: tegra: power: Eliminate extraneous PMC register writes
Scott Williams [Thu, 14 Jul 2011 20:34:25 +0000]
ARM: tegra: power: Eliminate extraneous PMC register writes

Writes to PMC registers in the 32 KHz domain are extremely slow.
Write PMC SCRATCH0/SCRATCH1 regsiters only when entering LP0.

Change-Id: Ib85b436330a8a9a0dc7fbc56889a375a534b8d10
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R8267387cbe889727ca429c2c6dc44630a061c808

5 years agoARM: tegra2: Update LP2 timers
Dan Willemsen [Mon, 25 Jul 2011 21:34:22 +0000]
ARM: tegra2: Update LP2 timers

Clean up conditionals for LP2 timers
Register an interrupt handler for the LP2 timer

Change-Id: I6ee6b6971f45f33d5d9295a462778af1d1c9843b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R6cec04d1c66dc3af22cb9ab7afe0dffaba891cea

5 years agoARM: tegra: Move common timer code into timer.c
Scott Williams [Mon, 25 Jul 2011 20:21:37 +0000]
ARM: tegra: Move common timer code into timer.c

The system timer initialization code for Tegra2 and Tegra3 is
essentially the same except for the actual physical timer used and the
range of possible reference clock frequencies. This change removes the
needless duplication of code and restructures the system timer code into
common and SOC-specific parts.

Change-Id: Icb6e4c0e2b218c67667be9450e10326e1e42945b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rbd3fc10b2a6935dd1ca9272695fd0133e0ca4f15

5 years agoARM: tegra: Add Tegra GIC extensions
Scott Williams [Wed, 13 Jul 2011 01:05:12 +0000]
ARM: tegra: Add Tegra GIC extensions

Implement extensions to the standard ARM GIC API for Tegra3 power management.

Change-Id: If8b2ce2b366e48bb5ca82d3de2acab1fd0a81bb9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd7527cd57edf054c871f5d04d7e9185643f79843