5 years agoarm: tegra: enterprise: add platform data for bt voice call
Nikesh Oswal [Wed, 9 Nov 2011 09:57:37 +0000]
arm: tegra: enterprise: add platform data for bt voice call

Bug: 862023

Change-Id: I826bf1b2de5681bd999b989ab74f86f26155f421
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/63248
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rec26d539061cdcd8895a539416f05111605b56b0

5 years agoarm: tegra: enterprise: add platform data for voice call
Nikesh Oswal [Sun, 6 Nov 2011 04:02:36 +0000]
arm: tegra: enterprise: add platform data for voice call

add platform data structures for codec i2s port connections
and baseband parameters

Bug: 862023

Change-Id: I52cc25e623474f6d5dd070cf4aedc1f108980595
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/62618
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: Rbe96cc2c99342de04590101d96c09616e72c6a41

5 years agoARM: Tegra: power: T33 SKU EDP table for 10A regulator
Diwakar Tundlam [Tue, 25 Oct 2011 01:20:08 +0000]
ARM: Tegra: power: T33 SKU EDP table for 10A regulator

bug 841336

Reviewed-on: http://git-master/r/62766
(cherry picked from commit c27e091be2ec3899fbb0bdbfe199784063f24be1)

Change-Id: I40277cea7f48cc15e074123ee73287b25389c0e6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/64211

Rebase-Id: Reef8906240656bfee07dbf9ba8f581677bad8e5f

5 years agoarm: tegra: Add HDA support
Sumit Bhattacharya [Fri, 21 Oct 2011 06:28:36 +0000]
arm: tegra: Add HDA support

Modify HDA device names to be inline with Intel HDA driver. Also
add entries for both HDA controller memory base address and HDA
controller PCI base address.
Also modify the dev_id and con_id of HDA related clocks so that
they can be used by HDA driver.

Bug 872652

Change-Id: Ifa05fe7d3d524e9ae310594a0e582c297dc52ef7
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/59506
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: R098f861d94a78a1401841b71b8c591b902b7b0bc

5 years agoARM: Tegra: dvfs: T33 SKU EDP table
Diwakar Tundlam [Fri, 12 Aug 2011 00:22:57 +0000]
ARM: Tegra: dvfs: T33 SKU EDP table

Bug 841336

Reviewed-on: http://git-master/r/60779
(cherry picked from commit 4d3f017e2715f50aaca6c7e8dc61e880947f7550)

Change-Id: Ib1eeb8729a91162d39fc952eeb7494d8863a03c7
Reviewed-on: http://git-master/r/64204
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rcfa5f6c11e831c4f08e956609ea8f9d98a6111f8

5 years agoarm: tegra: power: add TEGRA_THERMAL_SYSFS option
Joshua Primero [Tue, 4 Oct 2011 00:43:53 +0000]
arm: tegra: power: add TEGRA_THERMAL_SYSFS option

Added option to enable the use of the Linux Thermal
Sysfs infrastructure within the tegra thermal
framework.

Change-Id: I4306d173173a162dce18d864c46a9601523cdd09
Reviewed-on: http://git-master/r/59472
Reviewed-on: http://git-master/r/62574
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rbb6b3261fbdf2aa997f47eb254634fc6eff3ffb9

5 years agoARM: tegra: power: add combined power req processing
Joshua Cha [Mon, 14 Nov 2011 01:37:31 +0000]
ARM: tegra: power: add combined power req processing

For platforms where the core & CPU power requests are combined
as a single request to the PMU, we need separate processing to
enable its suspend/resume operation.

Bug 862504

Change-Id: If66282a7b069d35568147e2d64f14371e1692bfd
Reviewed-on: http://git-master/r/64011
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R21b966a438be03b11b80ce7deb70e3036b80dab2

5 years agoarm: tegra: power: Add throttle as a cooling dev
Joshua Primero [Tue, 4 Oct 2011 00:34:55 +0000]
arm: tegra: power: Add throttle as a cooling dev

Added cooling device hooks into the throttling module
to be used with the linux thermal sysfs infrastructure.

Reviewed-on: http://git-master/r/59470
(cherry picked from commit a7d0c2d23ae32cd074dc667f1ace6083273b1870)

Change-Id: I8ca4d94d838a00ea7c10423ab120329bf1b2343f
Reviewed-on: http://git-master/r/62573
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: R1bb4b36226f8a7c13166162feabeced9a1d469ee

5 years agoArm: Tegra: Cardhu: Set slew rise/fall rates properly
Pavan Kunapuli [Wed, 14 Sep 2011 13:40:53 +0000]
Arm: Tegra: Cardhu: Set slew rise/fall rates properly

Setting the slewrise and slewfall rates properly.

Bug 811303

Reviewed-on: http://git-master/r/52367
(cherry picked from commit 337b90b5a359c4f320f58f5026fa511dca5d8031)

Change-Id: I518b4dcdad8ac338cf03d4fb6c634b0747a82836
Reviewed-on: http://git-master/r/62326
(cherry picked from commit 7a04424fb0b8c1f36f28c99f73a313cd192360e9)
Reviewed-on: http://git-master/r/63813
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Racfd777be42f83018a9e295e1c7048ebb02f7f9e

5 years agoARM: tegra: power: Update CPU rate after mode switch
Alex Frid [Sun, 30 Oct 2011 04:12:44 +0000]
ARM: tegra: power: Update CPU rate after mode switch

Update Tegra3 CPU clock rate after G=>LP mode switch is completed to
synchronize with cpufreq target rate.

(cherry picked from commit 870d21e5e23eff476cdd841b4ce2605393d638ef)
(cherry picked from commit 11b20d7d6206c557f00e3f7a40dec1d498345d79)

Change-Id: I62237b8d34be23a8d903937f2ebb2d395c5db1b9
Reviewed-on: http://git-master/r/63359
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rdd1548389896521fddb2e239d6236706eb102f73

5 years agoARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP mode
Alex Frid [Wed, 26 Oct 2011 06:36:26 +0000]
ARM: tegra: dvfs: Optimize Tegra3 VDD_CPU control in LP mode

Optimized Tegra3 VDD_CPU control when VDD_CPU target is set to zero,
which could happen only while CPU is in LP mode (and CPU regulator
output is turned off by side-band signal, anyway):

- Ignore VDD_CPU dependency on VDD_CORE while VDD_CPU target is zero
- Allow VDD_CPU one step change to zero (i.e., to minimum voltage set
by constraints) after entry to LP mode
- Allow VDD_CPU one step change to the predicted G mode target before
exit from LP mode

(cherry picked from commit 5826f3e28867207b5dad1c50795de8275d1af872)
(cherry picked from commit 79c531421dfc65e27af657fd12b64c4187c67827)

Change-Id: I3c469132034a431d2e9b8727d11d604c306122f1
Reviewed-on: http://git-master/r/63357
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4c4f6e79decddb778f58cb5eef853a4c9d52ca94

5 years agoARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table
Alex Frid [Wed, 2 Nov 2011 02:39:15 +0000]
ARM: tegra: clock: Add DSR field to Tegra3 EMC DFS table

Added dynamic self-refresh (DSR) field to Tegra3 EMC DFS table. This
field will be supported starting with table revision to 3.2, and it
will allow to enable/disable DSR for each table entry independently.

Bug 853990

(cherry picked from commit 6e225af7334d789ffac72542602913a0028d5eac)
(cherry picked from commit c7ebe73da695206a992088a4ba5a6cd7643ea333)

Change-Id: I212d5992067baffaaf5b2e1de25b103c7b1fb56a
Reviewed-on: http://git-master/r/63356
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7261d49b023634a783ab2bd55f494112d0bac2a1

5 years agoARM: tegra: gpio: Add range check for gpio enable/disable
Chaitanya Bandi [Thu, 3 Nov 2011 10:43:18 +0000]
ARM: tegra: gpio: Add range check for gpio enable/disable

Added the range check into tegra_gpio_enable and tegra_gpio_disable

Bug 897387

Reviewed-on: http://git-master/r/62641
(cherry picked from commit 091b3906b2dd64cd58221e7e61a24a57dabad16c)

Change-Id: I9be8129397a1dccbea4a04f6b6ed7d4529bf45c3
Reviewed-on: http://git-master/r/63174
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rfaf0efdbc60208a56e4e4f073e3661ad1511694c

5 years agoarm: tegra: power: set throttling temperature = 85C
Diwakar Tundlam [Fri, 2 Sep 2011 17:38:24 +0000]
arm: tegra: power: set throttling temperature = 85C

Earlier value of 75 had unnecessary double guardbanding.
Changed 90C row in EDP table down to 85C to get throttling alert.

Bug 862301

Reviewed-on: http://git-master/r/50544
(cherry picked from commit 9f2693a80274bcd9eb8e7424bca87f34cc190741)

Change-Id: If7204150013e7894fc310a2f7e8fd46baf11d869
Reviewed-on: http://git-master/r/62773
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R6dacf9402de8edbb02bddb08b138808628b7eb15

5 years agoARM: tegra: uart: Restore FCR in uart resume
Pradeep Goudagunta [Fri, 4 Nov 2011 10:25:01 +0000]
ARM: tegra: uart: Restore FCR in uart resume

Restore FCR while resuming debug uart, to enable RX and TX FIFOs with
trigger levels configured during initialisation of debug uart port.

Bug 867063

Change-Id: I9665ff29a53c3e2e6c78a3037e20e7362a642f77
Reviewed-on: http://git-master/r/62411
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Ra3b9858456b952ab539a36019a55863077094054

5 years agoARM: tegra: power: Correct PL310 virt addr calculation
Puneet Saxena [Thu, 3 Nov 2011 10:01:23 +0000]
ARM: tegra: power: Correct PL310 virt addr calculation

PL310 virtual address was calculated using PPSB virtual/phy address.
It should be done using CPU virtual/phy address. This causes
TEGRA_PL310_VIRT value to get overlapped with virtual kerenl memory map's
Vmalloc region on whistler.

Bug 881831
Bug 867094

Change-Id: Ifaeeb9291553af59453f0041ad7cb1fe9d27979b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/62097
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Ra5a6165c8a02f0ac130bbaac4a477b901ceea62f

5 years agoARM: tegra: temp sensor: fix error handler
Colin Patrick McCabe [Wed, 26 Oct 2011 23:08:40 +0000]
ARM: tegra: temp sensor: fix error handler

Change-Id: Ie730ad7ec74927ef63722f4038db00e5f5d31154
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Reviewed-on: http://git-master/r/60558
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rad06124e61bdf95cb0307dd2204f2bf4bb92e718

5 years agoarm: tegra: Rename tegra2/3-throttle to tegra2/3_throttle.
Tom Cherry [Fri, 30 Sep 2011 23:11:48 +0000]
arm: tegra: Rename tegra2/3-throttle to tegra2/3_throttle.

This is to keep consistency with tegra* files all of which use
underscores instead of dashes

Reviewed-on: http://git-master/r/55582
(cherry picked from commit 401f0018a27a18aafb9eac7d0bed6990c99c73cc)

Change-Id: I1a7066e6ac86f5876126ae54cee84f64fbc509f1
Reviewed-on: http://git-master/r/62251
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rd08530c8b72d63d3ed1c8557f1c47f481ed49044

5 years agoARM: tegra: dvfs: Enable EMC bridge if rail is disabled
Alex Frid [Sat, 22 Oct 2011 05:02:53 +0000]
ARM: tegra: dvfs: Enable EMC bridge if rail is disabled

When core rail is disabled it is set to nominal voltage underneath
clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe
at high voltage that exceeds EMC bridge minimum level. Enable EMC
bridge explicitly in this case to set safe floor for EMC. Similarly
need to enable EMC bridge when CPU rail is disabled and pushing core
voltage (cpu-to-core voltage dependency) over bridge minimum level.

(cherry picked from commit bff814b2e46e67defde178b72bd379003b5429c2)
(cherry picked from commit e5567cb8dafcbd30797237e7bb91d77ce57de66a)

Change-Id: Ibb8dad5132f69e3325d793658b3dcc8b887974bf
Reviewed-on: http://git-master/r/62031
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R56f360c3b1ee25bf2dae4b886399b83e357f0225

5 years agoARM: tegra: power: Enable Tegra3 EMC bridge in suspend
Alex Frid [Sun, 23 Oct 2011 02:06:33 +0000]
ARM: tegra: power: Enable Tegra3 EMC bridge in suspend

When dvfs is suspended core rail is set to nominal voltage underneath
clock framework. On Tegra3 DDR3 platforms low EMC rates are not safe
at high voltage that exceeds EMC bridge minimum level. Enabling EMC
bridge during suspend for Tegra3 DDR3 platforms guarantees safe EMC
operations at high voltage.

(cherry picked from commit 677c01d3d9edaf7e91f09de5025e7864b6a288d8)
(cherry picked from commit 75710c173caa46f2e3cd24e48cc82f030cdb52d9)

Change-Id: I1e300c18867295b1394184da39eeffcab43de4c7
Reviewed-on: http://git-master/r/62030
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R2a3a91b370d2517e89e1d30f27f9fd41a9a81267

5 years agoARM: tegra: clock: Update Tegra3 EMC clock configuration
Alex Frid [Sat, 22 Oct 2011 04:47:36 +0000]
ARM: tegra: clock: Update Tegra3 EMC clock configuration

- Moved initialization of Tegra3 dram configuration variables from
EMC DVFS setup to EMC clock initialization, so that these variables
can be used independently of DVFS.

- Added graceful exit from EMC DVFS setup in case of empty DVFS table

- Applied EMC minimum rate to direct EMC clock round rate operations
(currently applied only to shared EMC bus update).

(cherry picked from commit c6b3f6e0eb0b6e3485d02fc5306a1c09cbacf914)
(cherry picked from commit cbf09d55bb9fa9c9ade7bb472859b4808f47b615)

Change-Id: I84bbdc05ff7a0670ec9d088b98a9df25683db4df
Reviewed-on: http://git-master/r/62029
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R0fb03ff9903aa51aa922b4a49eed96aad0e97a06

5 years agoARM: tegra: gpio: Set a gpio to tristate or normal
Chaitanya Bandi [Mon, 19 Sep 2011 11:15:28 +0000]
ARM: tegra: gpio: Set a gpio to tristate or normal

Create mapping from gpio to pingroup and set gpio to
normal or tristate

Bug 866633

Reviewed-on: http://git-master/r/56557
(cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115)

Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21
Reviewed-on: http://git-master/r/61120
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e

5 years agovideo: tegra: dsi: Adjust two CSI registers in DSI module.
Kevin Huang [Tue, 6 Sep 2011 18:04:55 +0000]
video: tegra: dsi: Adjust two CSI registers in DSI module.

Bug 829327

Reviewed-on: http://git-master/r/50871
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit 8d9aa14595348a2daa408710927471169447e73c)

Change-Id: Ib3e335dab5329ef29842354dc9934f8213ae3d58
Reviewed-on: http://git-master/r/61603
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R01a1fe72b19f49e3845459d4da8949b1a97089c9

5 years agoARM: tegra: Add interface to read/write vi/csi module.
Kevin Huang [Fri, 2 Sep 2011 20:30:37 +0000]
ARM: tegra: Add interface to read/write vi/csi module.

Bug 829327

Reviewed-on: http://git-master/r/50351
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 43d66ead107fc584068e8b894ef0ccf067b78f35)

Change-Id: I466f8300ae8c8ade5f7ab2783baabe5e744da18a
Reviewed-on: http://git-master/r/61601
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4aa7bd08edad8ad1cb81e5b04961d873e9d01b1a

5 years agoARM: tegra: power: Restore Tegra3 MC registers after LP0
Alex Frid [Thu, 15 Sep 2011 05:27:07 +0000]
ARM: tegra: power: Restore Tegra3 MC registers after LP0

On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers
that are not saved in PMC scratch file for boot-rom restoration. Since
SDRAM after LP0 is running at boot rate, MC registers are saved only
once during initialization.

Bug 874351

(ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d)

Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678
Reviewed-on: http://git-master/r/61045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301

5 years agoARM: tegra: power Limit CPU complex speed through sysfs
Alex Frid [Fri, 7 Oct 2011 06:38:21 +0000]
ARM: tegra: power Limit CPU complex speed through sysfs

Added sysfs node /sys/module/cpu_tegra/parameters/cpu_user_cap to set
maximum CPU rate from user space. Unlike per-cpu frequency governor
limit (scaling_max_freq), this cap is applied directly to common CPU
complex frequency underneath per-cpu governors.

(cherry picked from commit 5fbd5b19ddb43a03391957000f23b729f394b05b)
(cherry picked from commit bf81c8efc2c98e5008527ce019669dc57718f44b)

Change-Id: Ic2f152e1fd58f2f0062489309c0cffd32a2462ae
Reviewed-on: http://git-master/r/61711
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R800c2a4d5e097bdd29fa1b0b901264a2723abff0

5 years agoARM: tegra: clock: Order memory and cpu clock updates
Alex Frid [Tue, 27 Sep 2011 05:47:02 +0000]
ARM: tegra: clock: Order memory and cpu clock updates

When voting on memory frequency based on cpu frequency, update memory
frequency before cpu frequency if cpu rate is increasing, and after cpu
frequency if cpu rate is decreasing (current code updates memory first
always).

(cherry picked from commit 9284039a4d86c22ee72e11d6c173b24a5b4f720e)
(cherry picked from commit 3cd676121913b1cd9eddff06d6966817dcd9de94)

Change-Id: I91b81f1eab91d575959a2fd9af3a8798f7ca6cf6
Reviewed-on: http://git-master/r/61707
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R64d5597f8360ca151ba5e017cb94915c63699aca

5 years agoarm: tegra: Add dummy platform driver for BT and BB
Sumit Bhattacharya [Tue, 1 Nov 2011 13:32:15 +0000]
arm: tegra: Add dummy platform driver for BT and BB

Use dummy spdif-dit platform driver for bluetooth and baseband
platform driver.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>

Change-Id: I111e1f16d545d19b37c2a49c212160a210eea9f4
Reviewed-on: http://git-master/r/61503
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R058f68adf8951ba33dccdcaf6760875650de761e

5 years agoarm: tegra: Correct DAS base address
Sumit Bhattacharya [Mon, 31 Oct 2011 16:33:35 +0000]
arm: tegra: Correct DAS base address

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>

Change-Id: I27911d144c5636ce8be26c6c3830dea09b4a2cde
Reviewed-on: http://git-master/r/61234
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rb361a4da4573ba22c418a5c12fb820c9135292bb

5 years agoarm: tegra: add dam to devices.h
Nikesh Oswal [Thu, 13 Oct 2011 15:09:47 +0000]
arm: tegra: add dam to devices.h

Bug: 862023
Change-Id: I135529efcb8bf4518802d950a07e6923690419b0
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/57881
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R6c2419452e13142b07963e65a256e9da1e181ab2

5 years agoarm: tegra: Add support for vpr heap.
Krishna Reddy [Wed, 5 Oct 2011 19:23:37 +0000]
arm: tegra: Add support for vpr heap.

Bug 875847

Change-Id: Ieb237b3415f0861dfa13371fdbb7b3dbdac197b1
Reviewed-on: http://git-master/r/61246
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rbed707e8bcba433aaed18fe9119c10902d4e618b

5 years agoARM: tegra: power: Add Tegra3 balanced throttling
Alex Frid [Fri, 12 Aug 2011 03:54:33 +0000]
ARM: tegra: power: Add Tegra3 balanced throttling

Balanced CPU and core domains thermal throttling on Tegra3. When
throttling is enabled the new algorithm caps core bus frequencies
(EMC, cbus and sbus) along with CPU rate. The throttling steps, and
time spent on each step are pre-defined based on characterization
results.

(cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e)
(cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f)

Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f
Reviewed-on: http://git-master/r/61024
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190

5 years agoARM: tegra: power: Lock force_policy_max update
Alex Frid [Fri, 7 Oct 2011 04:19:40 +0000]
ARM: tegra: power: Lock force_policy_max update

(cherry picked from commit dc2f416df4664f5ddeba6f14f41cd6bcd717abab)
(cherry picked from commit caa79c7d6219231d02260ae91876eff4f411dee8)

Change-Id: I29eb42c73a7e3cd3f401e8b5d44bcf3f06478c2c
Reviewed-on: http://git-master/r/61021
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Ref5015bb8336d8106c80fa390911ff0371b3ec57

5 years agoARM: tegra: power: Enforce cpufreq policy maximum
Alex Frid [Sun, 11 Sep 2011 01:33:28 +0000]
ARM: tegra: power: Enforce cpufreq policy maximum

Tegra cpu complex frequency is set by cpufreq driver to the maximum
of per-cpu target frequencies specified by the respective governors
running on each cpu core. It guarantees that final frequency is above
all per-cpu policy low limits, but policy high limit set on one core,
may be exceeded if the other core has higher target.

This commit implements complementary mode in cpufreq driver that set
final cpu frequency below all per-cpu maximum policy limits. The new
mode is disabled by default, and can be activated via

/sys/module/cpu_tegra/parameters/force_policy_max

(cherry picked from commit d52a93527778b13efd2e4b783ce0707513f53f26)
(cherry picked from commit bc1450eedb97fd2f37544e07dae15946d209866c)

Change-Id: I2b51738a50312e0b3ba747747e6fa68efddc6038
Reviewed-on: http://git-master/r/61020
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R2fa76e42f800220db708c8720a3fe6b1792e5c59

5 years agoARM: tegra: power: Fix LP2/LP3 states accounting on Tegra3
Alex Frid [Thu, 29 Sep 2011 03:41:30 +0000]
ARM: tegra: power: Fix LP2/LP3 states accounting on Tegra3

- Made sure LP3 state is reported as last entered state to cpuidle
governor in case when LP3 is entered as a fall back from LP2 path.

- Accumulate idle time designated to LP2 state by cpuidle governor
and time actually spent in LP2 by each CPU separately. Update LP2
statistic output.

Change-Id: I55b461e94925ba7a41112756ed958f81fc0bc882
Reviewed-on: http://git-master/r/60381
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R240873bd1de225696d392ac5ba2c3d517c59d86e

5 years agoARM tegra: gpio: Correct gpio interrupt init sequence
Daehyoung Ko [Sat, 1 Oct 2011 00:42:49 +0000]
ARM tegra: gpio: Correct gpio interrupt init sequence

It is possible for GPIO interrupt to occur when registering handler
since set_irq_chained_handler enables GPIO interrupt. Thus
all relevant variables are required to be initialized
before calling set_irq_chained_handler.

Also add initialization of interrupt status register.

Bug 884569

Reviewed-on: http://git-master/r/58218
(cherry picked from commit e03fe4cc1bf06fa6c32c0520e2ba31f009f9301d)

Change-Id: Ic76f95215b61d6e091ae1cfa11522f8af9c3eecd
Reviewed-on: http://git-master/r/60475
Reviewed-by: Daehyoung Ko <dko@nvidia.com>
Tested-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R5340918dccc1a8b1d95c5b629cc985f44d45fb67

5 years agoarm: tegra: baseband: add USB modem power management support
Steve Lin [Tue, 25 Oct 2011 21:49:11 +0000]
arm: tegra: baseband: add USB modem power management support

This platform driver enables the generic USB modem power management support
for out-of_band remote wakeup, selective suspend and system suspend/resume.

Bug 854339

Reviewed-on: http://git-master/r/44911
(cherry picked from commit f737bc30ee9509a79e499c975b61c5f58bb19bb3)

Change-Id: Ibf38afb593fd8097e6152197c816e95e8f457659
Reviewed-on: http://git-master/r/60313
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>

Rebase-Id: R2bc754d319b388ce477ab7f987352d7f307d11c3

5 years agovideo: tegra: support display board PM313
Hyungwoo Yang [Mon, 24 Oct 2011 22:06:17 +0000]
video: tegra: support display board PM313

This change supports PM313 with 19X12 panel.
The change uses PM313 in "Single input to Dual output" mode

Bug ID : 822980
Reviewed-on: http://git-master/r/50215
(cherry picked from commit b83e795747fa860b5b7fb66b2067ebe4f15bcfd0)

Change-Id: Iabf707ded2976e9877481c215d0b1f1940781f14
Reviewed-on: http://git-master/r/60085
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rfd752366b937526a13b755a13edaa5986c681665

5 years agoarm: tegra: use non-blocking api to cancel work from mc error isr
Nitin Kumbhar [Fri, 21 Oct 2011 12:50:13 +0000]
arm: tegra: use non-blocking api to cancel work from mc error isr

An api (del_timer_sync), which can sleep, should not be used in
hardirq context. This gives warnings for potential deadlock. Use
non-sleeping api to cancel the work instead. In this case, if the
work is already running, it would unthrottle mc error prints.

BUG 889717

Change-Id: I4c0205766d82a45a04d1c0125bb8ed5927757456
Reviewed-on: http://git-master/r/59604
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>

Rebase-Id: R713c536217d0169f395ffb199ec2a97b274b9914

5 years agoarm: tegra: Handler for parsing kernel command max_cpu_curr
Laxman Dewangan [Sat, 15 Oct 2011 10:14:04 +0000]
arm: tegra: Handler for parsing kernel command max_cpu_curr

Adding handler for parsing the kernel command max_cpu_curr and api
for retruning the max_cpu_current.

bug 888679

Reviewed-on: http://git-master/r/58626
(cherry picked from commit 4d2da03c37a1a1401b4ef87b888f487a99b175b7)

Change-Id: Ic5a53fe4e41317f48b986867081f3e7d96103f0d
Reviewed-on: http://git-master/r/59290
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Ra426e2b10268bc7eadbe394c107528378f043e15

5 years agoARM: tegra: power: Force FW bit when SMP is enabled.
Alex Frid [Tue, 11 Oct 2011 03:32:49 +0000]
ARM: tegra: power: Force FW bit when SMP is enabled.

Set FW bit in CP15 auxiliary control register after LP=>G CPU mode
switch if SMP bit in the same register is set. On Tegra3 in LP mode
FW bit is always zero, even though SMP bit is retained. Hence, this
change recovers FW bit on return from LP to G-mode.

Change-Id: I9f0021ab90866cb8686d73eb6ad5bbedbb2ceb90
Reviewed-on: http://git-master/r/57203
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R37dbe2079eafcfb47babaf41b53818a9130d2bbe

5 years agoARM: tegra: power: Do not switch Tegra3 to PLLP
Alex Frid [Sat, 1 Oct 2011 01:38:59 +0000]
ARM: tegra: power: Do not switch Tegra3 to PLLP

Do not switch Tegra3 to PLLP on sleep entry: no need - unlike Tegra2
PLLX on Tegra3 is not disabled when CPU is rail gated; also G/LP mode
switch clock configuration is set by mode switch prolog and should not
be overwritten at the last moment.

Change-Id: I9aa8463c6b1c04c0a70e70c1e2cd4113a679e100
Reviewed-on: http://git-master/r/57202
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R9a8d78a363c261d45e48832fcbed7fa2854f7da8

5 years agoarm: tegra: cardhu: Initialize gpio pins mode
Laxman Dewangan [Tue, 4 Oct 2011 12:58:57 +0000]
arm: tegra: cardhu: Initialize gpio pins mode

Initializing the pins which is used in gpio to their inital state.

bug 876305

Reviewed-on: http://git-master/r/57516
(cherry picked from commit 3f33cb777295669e71e291bb05651d3c6c4b37d5)

Change-Id: Ie05862e5184bb95c85cf7aa96ce2eca497c01c93
Reviewed-on: http://git-master/r/57817
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3886fa24fc77365529b86eef67f10a428764aee4

5 years agoarm: tegra: Avoid negative number parsing for debug port
Laxman Dewangan [Wed, 28 Sep 2011 09:12:49 +0000]
arm: tegra: Avoid negative number parsing for debug port

Avoiding negative number parsing for debug port id.

bug 854995

Reviewed-on: http://git-master/r/57328
(cherry picked from commit 81ce6594db0a2b9131e3a1317ef1f10e8310aad5)
Change-Id: I38e9e545c06a61b79d292c86dcbf8c595d2eddca
Reviewed-on: http://git-master/r/57787
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R2fe0b743db9f2b87f0a0715aeda12e7c00b041a7

5 years agoarm: tegra: Support for kernel command audio_codec
Laxman Dewangan [Sun, 18 Sep 2011 11:19:10 +0000]
arm: tegra: Support for kernel command audio_codec

Adding the handler to parse the kernel command "audio_codec".

bug 876544

Reviewed-on: http://git-master/r/56623
(cherry picked from commit b82c518354864c7dba03beea3c576edfab428efd)

Change-Id: Icb42164ea1276f4f5af941b8ba2f80076759af8b
Reviewed-on: http://git-master/r/57779
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: Rf3a0eed42103ef830c9697da42eb685fde6f6fe9

5 years agoarm: tegra: pm: issue a pl310 cache sync for tegra2
Mayuresh Kulkarni [Thu, 15 Sep 2011 09:26:10 +0000]
arm: tegra: pm: issue a pl310 cache sync for tegra2

this needs to be done when the lp2 is aborted before the
stipulated programmed time to wake-up

for bug 867094

Change-Id: I02102ed8afa69d782de5950118352e80edc79df4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/52581
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R5938771982b7cceb9ea23ee73852ca8b9b3490ae

5 years agoarm: tegra: gpio: API to configure pins as gpio with init value
Laxman Dewangan [Fri, 30 Sep 2011 10:44:27 +0000]
arm: tegra: gpio: API to configure pins as gpio with init value

Adding api to configure pins in gpio mode with init value before
gpio library is up. This will provide to configure the pins in
initial state and avoid any glitch in pins.

bug 876305

Reviewed-on: http://git-master/r/56630
(cherry picked from commit 9e357b69d25f96c13acb660860bcdf8e0ab0a1ef)

Change-Id: Ia14721c0bf96e1a45561139fdbbf2d995b9a4963
Reviewed-on: http://git-master/r/57265
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rc775d23898a6275d633e4474e6cf9b10395697e2

5 years agoarm: tegra: Add handle for kernel option power_supply
Laxman Dewangan [Sun, 4 Sep 2011 11:40:13 +0000]
arm: tegra: Add handle for kernel option power_supply

Adding the handler function for the kernel command line
option "power_supply".

Reviewed-on: http://git-master/r/50674
(cherry picked from commit 8d9e6bbe59ab68f44a4713f5d1bcc7877baf8180)

Change-Id: I07796b6ee5893d73ac7557e81aac5d26b299c491
Reviewed-on: http://git-master/r/57262
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rd64bf314bcdfe3f7bdbcdee946ed261bfce5938f

5 years agoarm: tegra: Remove T30 SPDIF DMA resource info
Sumit Bhattacharya [Tue, 4 Oct 2011 12:02:36 +0000]
arm: tegra: Remove T30 SPDIF DMA resource info

Bug 872652

Change-Id: Iaea76918169f3270f865122f824f60678c419b50
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/55970
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R70b9408e1c66c97a63a9408dda43aacd369c3178

5 years agoarm: tegra: whistler: add headphone debouncetime and irq
Nikesh Oswal [Mon, 10 Oct 2011 12:06:28 +0000]
arm: tegra: whistler: add headphone debouncetime and irq

add entries for headphone detection irq and debouncetime in
whistler specific board files

Bug: 862023

Change-Id: Ia72ec10f51a1bde0f81eb488b36a8b1439cedf1d
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/57034
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R7fe99f98b6d8c11562af00da3bef9ba5bfd56d1c

5 years agoarch: arm: Enable SPDIF driver for Tegra30
Sumit Bhattacharya [Wed, 28 Sep 2011 12:29:22 +0000]
arch: arm: Enable SPDIF driver for Tegra30

Bug 872652

Change-Id: Ic170dc2fc86f74d9e67d3b73a6f83368597dafcb
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/54975
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Ra59bdfb6b9109169935b3d5c9275053290d741ad

5 years agoarm: tegra: parse kernel command line for debug port id
Laxman Dewangan [Thu, 8 Sep 2011 14:06:17 +0000]
arm: tegra: parse kernel command line for debug port id

Parsing the linux command line for the debug port id.

bug 795847

Reviewed-on: http://git-master/r/51370
(cherry picked from commit f988c97564f9ecf4b78f4e935e2cfc4ca1b6db0e)

Change-Id: Ib1bbdd9f671ab4c22cffdf379d3b9fd79a5a8736
Reviewed-on: http://git-master/r/57042
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R8b31dafaa124fb7e99d219bb464703b5696da0ff

5 years agoarm: tegra: fix "malformed early option" warning
Deepesh Gujarathi [Fri, 7 Oct 2011 09:48:30 +0000]
arm: tegra: fix "malformed early option" warning

early_param expects return value 0 for success as
opposed to 1 in case of set_param handler.

Bug 875134

Change-Id: I3eaf540a44fef4d211add399cedc258314266ed0
Reviewed-on: http://git-master/r/56638
Tested-by: Deepesh Gujarathi <dgujarathi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

Rebase-Id: Rbcbd37982e85a4cbad71319945efbc0ab6052d90

5 years agoARM: tegra: fuse: Fix tegra_chip_uid
Dan Willemsen [Wed, 5 Oct 2011 22:26:57 +0000]
ARM: tegra: fuse: Fix tegra_chip_uid

This now matches what the bootloader thinks the chip ID is (and the lot
code is no longer all zeros).

Change-Id: I46dc677b983dd28f7f77e49919860fef66da8f51
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/56316
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfb7b961acd57447df95600d4f1678d84242ed1b9

5 years agoARM: tegra: power: Add Tegra3 cpu idle parameters
Alex Frid [Sat, 1 Oct 2011 04:27:37 +0000]
ARM: tegra: power: Add Tegra3 cpu idle parameters

Add Tegra3 cpu idle parameters: lp2_0_in_idle and lp_n_in_idle
to independently control LP2 mode for boot and secondary cpus.

Change-Id: I7e526b9bd78a9d5c3235307bbc89f5fb507bec2b
Reviewed-on: http://git-master/r/55630
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rc6a468b2e9e065c344b2386366d5a47d77ddf037

5 years agoARM: tegra: power: Update Tegra3 LP2 time prediction
Alex Frid [Thu, 29 Sep 2011 05:42:06 +0000]
ARM: tegra: power: Update Tegra3 LP2 time prediction

Use local timer count to predict time to be spent by secondary CPU
in LP2 state instead of scheduler timing. This is more accurate, as
local timer wakes CPU after counts down to zero.

Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35
Reviewed-on: http://git-master/r/55629
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>

Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631

5 years agoarm: tegra: move core_edp parsing to early_init
Deepesh Gujarathi [Thu, 15 Sep 2011 08:27:02 +0000]
arm: tegra: move core_edp parsing to early_init

since the dvfs init was being called before the kernel commandline was
parsed, it resulted in an incorrect core_edp voltage being set further
leading to an incorrect emc clock.

move parsing of core_edp voltage value to early_param handler.

fixes bug 875134
partial fix for bug 877315

Change-Id: Iab90e35ecb9145f028dd9c7bae7c7c4b49186b55
Originally Reviewed-on: http://git-master/r/52570
Reviewed-on: http://git-master/r/56181
Tested-by: Deepesh Gujarathi <dgujarathi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Sridhar Lavu <slavu@nvidia.com>
Tested-by: Sridhar Lavu <slavu@nvidia.com>

Rebase-Id: Rda263df02e386b4b2f455196c3f6ade7526c45ed

5 years agoARM: tegra: clock: Re-factor shared bus locking
Alex Frid [Sat, 1 Oct 2011 23:00:51 +0000]
ARM: tegra: clock: Re-factor shared bus locking

Current code:
- on tegra2 unnecessary covers with bus lock shared user state update
- on tegra3 does not cover shared bus rate update at all
Modified to cover with bus lock shared bus rate update only on both
tegra2 and tegra3.

Change-Id: Iaa2597136a521adf4285c61eb579c917c2c7965c
Reviewed-on: http://git-master/r/55640
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1b28f32ae37d47c56855023b18c943bf8fd93c74

5 years agoARM: tegra: power: Clean Tegra3 LP2 entry procedure
Alex Frid [Wed, 28 Sep 2011 05:33:50 +0000]
ARM: tegra: power: Clean Tegra3 LP2 entry procedure

- Do not save/restore local timer configuration across secondary CPU
LP2 state. It is always preserved, since local timer is neither power
gated nor reset when secondary CPU is in LP2.

- Do not configure external timer for secondary CPU wake up, since we
can use local timer instead. Moreover, in current code external timer
interrupt is registered too late on secondary CPU after it is brought
on-line, so the timer may not always be able to wake CPU up from LP2.

Change-Id: I864e9910fe7112bbce3ea4dbaef12be4b42fb5dc
Reviewed-on: http://git-master/r/55070
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R3407f05d200d81e29994daf278170d3619714bef

5 years agoARM: tegra: power: Initialize and update LP2 exit latency
Alex Frid [Wed, 28 Sep 2011 03:14:55 +0000]
ARM: tegra: power: Initialize and update LP2 exit latency

Change-Id: Id6bacc252774758d9ea03b7f2cc91897b5817e10
Reviewed-on: http://git-master/r/55069
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Ra8e8dfed500041886700a8fd44b0b917367225b3

5 years agoARM: tegra: timer: Update twd suspend/resume
Alex Frid [Wed, 21 Sep 2011 06:37:36 +0000]
ARM: tegra: timer: Update twd suspend/resume

- Preserve twd periodic load register across suspend and LP2 on main
CPU. Keep timer disabled on resume, since it will be re-configured
later when timekeeping switches from global system timer.

- Generate "load equal zero" warning in twd suspend/resume code only
when timer is in periodic mode.

Change-Id: If7df8be08c0ef4e355f315e3f0b7e3cf1b358f0f
Reviewed-on: http://git-master/r/55068
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R75f3950a915e0953a098620dea9ea32a7d5e9482

5 years agoARM: tegra: dvfs: Disable all rails if one failed to connect
Alex Frid [Fri, 30 Sep 2011 03:50:12 +0000]
ARM: tegra: dvfs: Disable all rails if one failed to connect

Change-Id: I0aa4debdb0bed160c6ff9d6e5863bfa06a693017
Reviewed-on: http://git-master/r/55370
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rfb9dea2f471f257a15d9da163226573f5330ce32

5 years agoARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.
vdumpa [Wed, 4 May 2011 18:48:38 +0000]
ARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.

Bug 804805

(cherry picked from commit 068e6789bd335640ad2b444fae1e74fd9ca974c5)

Change-Id: If79b491133e6080b8b9c90c5adb0f59239ea275f
Reviewed-on: http://git-master/r/54842
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R16eabb01ed2c8197632d6063b5c9f35bed5714dd

5 years agoarm: tegra: smmu: Remove IORESOURCE use from SMMU IOVA range
Hiro Sugawara [Wed, 14 Sep 2011 00:20:35 +0000]
arm: tegra: smmu: Remove IORESOURCE use from SMMU IOVA range

SMMU simply needs to know its assigned IOVA range, but does not need
address space resources.
Bug 874438

Change-Id: I0b9943d06c49363cfc0355586866f3bd6b217274
Reviewed-on: http://git-master/r/54534
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R3f4045ef2858960cd987a7477ec6869168ccec7d

5 years agoARM: tegra: Disable AUTO_HOTPLUG for Tegra2.
Gaurav Sarode [Wed, 28 Sep 2011 08:38:39 +0000]
ARM: tegra: Disable AUTO_HOTPLUG for Tegra2.

AUTO_HOTPLUG is not supported on Tegra2 platform.

Change-Id: Id6332b8a5e784bfada42c58803075ee2c70ec019
Reviewed-on: http://git-master/r/54915
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R02328774cd3588a6091446937229983e9131f87c

5 years agoARM: tegra: nvavp: registering new nvavp driver
Bharat Nihalani [Mon, 26 Sep 2011 13:51:08 +0000]
ARM: tegra: nvavp: registering new nvavp driver

Also re-arranged tegra_nvavp code so that it is common accross boards

Bug 880623

Change-Id: I7d634a718e07e07e945fb512466b3a0672aea7e2
Reviewed-on: http://git-master/r/54487
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R188282334f9e0d18985b87c6241f96f663b8f540

5 years agoarm: tegra: correcting wfi sequence
venu byravarasu [Tue, 27 Sep 2011 06:56:46 +0000]
arm: tegra: correcting wfi sequence

As per hardware documentation, dsb should precede wfi.
Hence fixing it.

Change-Id: I1c98581dfe3891d425ab36c1a2bb313e19ad046d
Reviewed-on: http://git-master/r/54626
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3d7e46306d7d97c2cdfa0ec7ce658a1658724a76

5 years agoarch: arm: tegra: Add SPDIF driver support
Sumit Bhattacharya [Sun, 18 Sep 2011 18:48:34 +0000]
arch: arm: tegra: Add SPDIF driver support

Bug 872652

Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>

Change-Id: I7b948b820434721511c008f644b69d93c23865e1
Reviewed-on: http://git-master/r/53094
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R769f97e31513f4479b20d7dff995e06cc72e19bd

5 years agoarm: tegra: Disable LP2 mode by default.
Krishna Reddy [Thu, 22 Sep 2011 02:27:30 +0000]
arm: tegra: Disable LP2 mode by default.

LP2 should be enabled through board specific init rc file.

Change-Id: I2772ad0ccd04fd3933a2286c6335304d2bef60cd
Reviewed-on: http://git-master/r/53920
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra46b97752305db9e3ac2400162872c5e5863034e

5 years agoARM: tegra: power: Flush cache just before cpu shutdown
Alex Frid [Wed, 21 Sep 2011 01:45:53 +0000]
ARM: tegra: power: Flush cache just before cpu shutdown

Re-arranged cpu die procedure to flush L1 cache just before shutdown.
This is necessary as code executed after L1 flush included spin-lock
protected sections, and the unlock operation was not properly detected
by SCU. As a result CPUs that stayed on-line hanged trying to acquire
the same spin-lock.

Bug 864256

Change-Id: I415160d60686094059e62d91cdcf4b264a4fb69f
Reviewed-on: http://git-master/r/53637
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0663eac9b5c3c84d8b7380873bde6af6b2a74a9f

5 years agoARM: tegra: timer: Fix mismatch in twd suspend/resume code
Alex Frid [Tue, 20 Sep 2011 02:27:19 +0000]
ARM: tegra: timer: Fix mismatch in twd suspend/resume code

Change-Id: Ied49d7517574b62ebc54ba8a5ef04d26408f0145
Reviewed-on: http://git-master/r/53347
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

Rebase-Id: Rd540ebbeb48903eea556508be45580c5d260941e

5 years agoARM: tegra: reduce LP0 resume CPU power on time
Jin Qian [Wed, 14 Sep 2011 18:53:35 +0000]
ARM: tegra: reduce LP0 resume CPU power on time

cherry-picked from adf08ef4030598a6bf9036f45584be8acc008fea

Bug 862504

Change-Id: I79460aa4abdccc4f2ca17867197bb12668d59dea
Reviewed-on: http://git-master/r/52420
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Rffc2d7314a61f04274e0db116c5a1cb7004dc77d

5 years agoarm:tegra: Add EXPORT_SYMBOL and ioctls for test framework
Rahul Mittal [Wed, 14 Sep 2011 09:34:32 +0000]
arm:tegra: Add EXPORT_SYMBOL and ioctls for test framework

Added EXPORT_SYMBOL to functions to be used by loadable kernel module
for audio test framework. Also added ioctl declarations for the same.

Change-Id: Id8a023c1d76fd031c042c7c663bb0e1df2d33b5c
Reviewed-on: http://git-master/r/52333
Tested-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

Rebase-Id: R88ac0ceb719d9fae5d68d5f9a1894a3562e82b25

5 years agoARM: tegra: power: fix build error on tegra_pm_enter routines
Jin Qian [Mon, 12 Sep 2011 19:33:15 +0000]
ARM: tegra: power: fix build error on tegra_pm_enter routines

Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c
Reviewed-on: http://git-master/r/51852
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861

5 years agoARM: tegra: Add enterprise audio support
Sumit Bhattacharya [Wed, 7 Sep 2011 09:42:51 +0000]
ARM: tegra: Add enterprise audio support

Bug 862023

Change-Id: I0ba560f471088302d6197c564f02606a25f2a5db
Reviewed-on: http://git-master/r/51072
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Raafdfa1c8ada5731492222e59228da084c0905d9

5 years agoARM: tegra: power: do not check time after kernel time suspend
Jin Qian [Fri, 2 Sep 2011 23:24:01 +0000]
ARM: tegra: power: do not check time after kernel time suspend

cluster switch for LP0 is called after linux timekeeping suspend,
which turns off timer.

Bug 862504

Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe
Reviewed-on: http://git-master/r/50611
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a

5 years agoARM: tegra: power: save cluster switch status before entering LP0
Jin Qian [Fri, 2 Sep 2011 23:22:18 +0000]
ARM: tegra: power: save cluster switch status before entering LP0

warm boot reads SCRATCH4 to choose wake-up from LP or G

Bug 862504

Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94

5 years agoARM: tegra: power: move cluster switch to syscore for LP0
Jin Qian [Thu, 1 Sep 2011 02:47:26 +0000]
ARM: tegra: power: move cluster switch to syscore for LP0

move printk as well since they rely on uart resume in syscore

Bug 862504

Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e
Reviewed-on: http://git-master/r/50240
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b

5 years agoARM: tegra: power: fix lp0 suspend
Jin Qian [Thu, 1 Sep 2011 02:39:57 +0000]
ARM: tegra: power: fix lp0 suspend

enable pllm and skip io_dpd for lp0

Bug 862504

Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7
Reviewed-on: http://git-master/r/50239
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0

5 years agoARM: tegra: power: move cluster switch prolog/epilog from suspend
Jin Qian [Wed, 31 Aug 2011 00:23:55 +0000]
ARM: tegra: power: move cluster switch prolog/epilog from suspend

They're called only when doing cluster switch so move them to
cluster control function.

Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c
Reviewed-on: http://git-master/r/49952
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363

5 years agoARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache
Jin Qian [Wed, 24 Aug 2011 20:51:43 +0000]
ARM: tegra: power: clear TLBs & BTAC after re-enabling L1 cache

Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f

5 years agoARM: defconfig: tegra3: use REPORT_PRESENT_CPUS
Jon Mayo [Thu, 28 Jul 2011 00:01:57 +0000]
ARM: defconfig: tegra3: use REPORT_PRESENT_CPUS

enable reporting of present cpus in /proc/cpuinfo and /proc/stat

Bug 849167

Original-Change-Id: I8651079ff63c7399942d937cb0af126aa67a2fd7
Reviewed-on: http://git-master/r/43632
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: R24122a5d7e8b2517e99518a698f89ac3946a76ec

5 years agoARM: tegra: power: restore reset handler after lp0
Jin Qian [Wed, 24 Aug 2011 01:15:32 +0000]
ARM: tegra: power: restore reset handler after lp0

Bug 862504

Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7
Reviewed-on: http://git-master/r/50241
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400

5 years agoARM: tegra: Update copyrights
Scott Williams [Wed, 7 Sep 2011 19:21:06 +0000]
ARM: tegra: Update copyrights

Change-Id: I156af0bdd8b37cb23aec214c3e158027252e27e1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/51157

Rebase-Id: R5aa782b116daefeb126b3bf58af90a7fd78f648d

5 years agoARM: tegra: whistler: Add sound support
Sumit Bhattacharya [Tue, 30 Aug 2011 16:34:55 +0000]
ARM: tegra: whistler: Add sound support

Bug 862023

Change-Id: I32d8406a7c1d88b09156b94dda2a2b47e89e515f
Reviewed-on: http://git-master/r/49874
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R1114efe2768c40b0615a8e22639b01372688a5be

5 years agoARM: tegra: Clean up the chip revision decoder
Scott Williams [Wed, 7 Sep 2011 00:19:18 +0000]
ARM: tegra: Clean up the chip revision decoder

Replace the chip revision decoder with something that is more
extensible and maintainable.

Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50931
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>

Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136

5 years agoARM: Tegra: Pinmux: Fix drive strength configuration
Pavan Kunapuli [Fri, 2 Sep 2011 10:02:00 +0000]
ARM: Tegra: Pinmux: Fix drive strength configuration

In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.

Bug 870369

Original-Change-Id: Ib1872417542236c95c3b41a1ad860ef8418f5704
Reviewed-on: http://git-master/r/49872
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R4889bbb8bc0e5fef57d98bc68cd0116a9be3fdbd

5 years agoARM: tegra: power: Tune Tegra3 hotplug algorithm
Alex Frid [Wed, 24 Aug 2011 05:52:42 +0000]
ARM: tegra: power: Tune Tegra3 hotplug algorithm

- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.

- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%

Added tunables:

/sys/module/cpu_tegra3/parameters/mp_overhead
/sys/module/cpu_tegra3/parameters/balance_level

Bug 865176
Bug 867186

Original-Change-Id: I6f2e175e0b5ed14c4b85794949c1e65d0e7f4a36
Reviewed-on: http://git-master/r/49772
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

Rebase-Id: Rcfefb570c30bf78f6eae155c3f3f7547ac64f128

5 years agoARM: tegra: pinmux: Prevent access to uninitialized pin groups
Scott Williams [Wed, 31 Aug 2011 15:37:27 +0000]
ARM: tegra: pinmux: Prevent access to uninitialized pin groups

There is no guarantee that every element in the pin group array
will be used (i.e., initialized) for a particular SOC. Prevent
access to pin group array elements that are not initialized.

Original-Change-Id: I90ea3616f8508b12ffe4a7daf9ff4b2bac057075
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50059
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

Rebase-Id: Rd6c206b805d180fb3c52be52edfeebed701ca73d

5 years agoARM: tegra: speed up framebuffer copy
Jon Mayo [Tue, 30 Aug 2011 01:09:16 +0000]
ARM: tegra: speed up framebuffer copy

Use a memcpy with less overhead in tegra_move_framebuffer, this makes
this function about 30 times faster.

Bug 843089

Original-Change-Id: I4ae9127db6d5ff5d9680e3ff2c3d28463395e39b
Reviewed-on: http://git-master/r/49735
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Kevin Huang <kevinh@nvidia.com>

Rebase-Id: R0906917433643ac4ce9ac97284007527ef2d67df

5 years agoarm: tegra: iovmm: Fixed configurablability advertised in Makefile
Hiro Sugawara [Thu, 25 Aug 2011 21:14:02 +0000]
arm: tegra: iovmm: Fixed configurablability advertised in Makefile

CONFIG_TEGRA_IOVMM_SMMU now can be independently disabled and
the kernel still builds.

Original-Change-Id: I009319352f4b125941a58132d2be8d5f36411aab
Reviewed-on: http://git-master/r/49278
Tested-by: Hiro Sugawara <hsugawara@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb663949db3e3fcfa6418f71cdc74662dded08fc6

5 years agoARM: tegra: Use SATA and PCIE SOC architecture conditionals
Scott Williams [Thu, 1 Sep 2011 23:20:47 +0000]
ARM: tegra: Use SATA and PCIE SOC architecture conditionals

Use the SOC architecture conditionals for determining the
presense of PCIE and SATA.

Change-Id: I312d0d1b45fc08e4938260b978d083b113ed9d66
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50379
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Ra949d477a8e96ccc7760c4974ae93909ea054bbb

5 years agoARM: tegra: Only enable fuse programming on silicon platforms
Scott Williams [Tue, 30 Aug 2011 00:31:46 +0000]
ARM: tegra: Only enable fuse programming on silicon platforms

Fuse programming is possible only on silicon platforms.
Do not enable it for simulation or FPGA platforms.

Change-Id: If1bec072eeaae1ee95720a37e37fcb7c8e8ee464
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49724
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R71d2073c18353d32a2b5373819f2e27e1e8bb680

5 years agoARM: tegra: Clean up makefile conditionals
Scott Williams [Thu, 1 Sep 2011 22:07:44 +0000]
ARM: tegra: Clean up makefile conditionals

Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50358
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2

5 years agoARM: tegra: Clean up power gating code
Scott Williams [Thu, 1 Sep 2011 22:03:48 +0000]
ARM: tegra: Clean up power gating code

Clean up conditionals.
Use the generic name of CELP for the LP partition.

Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a

5 years agoARM: tegra: Remove unnecessary SOC conditionals
Scott Williams [Thu, 1 Sep 2011 21:59:01 +0000]
ARM: tegra: Remove unnecessary SOC conditionals

Change-Id: I4ad09ea97db373dbed0764214fc5d98be2e29f7a
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50356
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5c2b9b638a4e150eb1fa6e1d4f587bb71622efea

5 years agoARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets
Scott Williams [Thu, 1 Sep 2011 21:55:13 +0000]
ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets

Determine the number of GPU register sets based upon the setting
of ARCH_TEGRA_DUAL_3D.

Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50355
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96

5 years agoARM: tegra: Only Tegra3 has TSENSOR
Scott Williams [Thu, 1 Sep 2011 21:47:32 +0000]
ARM: tegra: Only Tegra3 has TSENSOR

Change-Id: I232d3ae5e037d491d1d8d185e75c1c9a7035cd4c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50354
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R899f3aaf97ca7f21785749a8675ba1bc461f81f9

5 years agoARM: tegra: Use forward looking architecture conditionals
Scott Williams [Thu, 1 Sep 2011 02:24:56 +0000]
ARM: tegra: Use forward looking architecture conditionals

Change-Id: I31f2717327a627ad83e4cc2f083b71fd68fb1465
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50221
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcaef7248cf06aa01c40b8e5eae13e3a20ed097d3

5 years agoARM: tegra: Add SOC architectural capabilities
Scott Williams [Thu, 1 Sep 2011 15:56:31 +0000]
ARM: tegra: Add SOC architectural capabilities

Add architectural capabilities the at are selected by the top-level
architecture type rather than deriving this knowledge directly from
the top-level type in the code.

Change-Id: I1c1e5d986a65301cf2e474d866f01e4f8c2a5505
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50298
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R118b523b4c6cac8f4f530f01a1d14ed961d5a085