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nv-tegra.nvidia Code Review - linux-3.10.git/log
Robert Morell [Sun, 7 Jul 2013 04:18:50 +0000 (21:18 -0700)]
arm: tegra12_defconfig: Enable VT, disable SMMU
VT is necessary for X11. SMMU causes exceptions.
Change-Id: I88ac8670c623ea08ba7cd544cc940747ecac3615
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/245888
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Eric Brower <ebrower@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Mitch Luban [Mon, 8 Jul 2013 20:22:54 +0000 (13:22 -0700)]
arm: tegra: ardbeg: increase carveout to 1GB
Change-Id: I8dff848ba9c68738ecfbb6c6360ea39240dd2ff6
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/246245
Krishna Sitaraman [Sat, 6 Jul 2013 19:24:24 +0000 (12:24 -0700)]
ARM: Tegra12: Clocks: Increase max frequency of isp clock
Increase max frequency of isp clock to 800Mhz
Change-Id: Ie497f8a3eafea358f1f8149006186d6c6e539552
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/245850
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Krishna Sitaraman [Thu, 4 Jul 2013 00:03:38 +0000 (17:03 -0700)]
ARM: tegra12: dvfs: Update cpu cvb tables
Updated cpu cvb tables remove dvfs table restriction for higher cpu
rate cpu will be able to reach 1.9 GHz in DFLL mode and 1.6GHz in pll
mode with cpu voltage scaling up to 1.1V (for platforms with fixed 1.0V
cpu regulator cpu max rate in PLL mode is 1.2GHz).
Change-Id: I2a19fbcb2b4c98dfdc211a50a011313d02984246
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/245198
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Johnny Qiu [Sat, 6 Jul 2013 07:02:20 +0000 (00:02 -0700)]
asoc: tegra: rt5639/rt5645: add hp_det polarity
Change-Id: Ieac78ab76320c7d0161f351375e577afe063a95c
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/245782
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Johnny Qiu [Sat, 6 Jul 2013 07:03:08 +0000 (00:03 -0700)]
arm: tegra: laguna: set hp_det to active-high
Change-Id: I0a4a543ea6f1d10ac29a093e58e2cb438f7dac38
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/245783
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Pradeep Goudagunta [Mon, 1 Jul 2013 11:52:01 +0000 (17:22 +0530)]
ARM: tegra: tn8: Populate E1736 power rails
Bug
1284675
Change-Id: Iea212a2d6b5049528736dd43d6e6616eeb7c29f8
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/243889
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Sat, 29 Jun 2013 10:30:25 +0000 (16:00 +0530)]
ARM: tegra: ardbeg: Update power rails
-Add E1735 fixed regulators.
-Fill missing sensors and pcie regulators.
-Enable full constraints for E1735.
Bug
1306376
Bug
1313825
Bug
1320279
Bug
1300619
Change-Id: Ic2705fac07b2128ab4396c3d4db836f0bdbdb62b
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/243675
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Mallikarjun Kasoju [Mon, 8 Jul 2013 12:19:02 +0000 (17:49 +0530)]
ARM: tegra: adberg: add extcon platform data
- Add extcon platform data
- configure gpio0 to usb ID detection
Bug
1307888
Change-Id: I0dc6e0302b89b2ad4aff7c4fa2a0962d91310510
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/246119
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Mallikarjun Kasoju [Mon, 8 Jul 2013 12:18:00 +0000 (17:48 +0530)]
ARM: configs: tegra12: Enable palmas extcon
Bug
1307888
Change-Id: I67f9ee5906d438a08dce162dad4e1741b95e5b68
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/246118
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Mon, 8 Jul 2013 10:44:29 +0000 (16:14 +0530)]
ARM: tegra: ardbeg: Set init voltage for vdd_gpu
Bug
1321163
Change-Id: If65cc4420edb9fe41364a748a9699eb08d3b803c
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/246072
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Sun, 7 Jul 2013 04:01:25 +0000 (09:31 +0530)]
ARM: tegra: ardbeg: Enable TI913 32KCLKs
-Enable Audio/GPS 3K2CLK from TI913_GPIO5.
-Enable MDM_32KCLK from TI913_CLK32KG.
Bug
1321104
Change-Id: If697a697019a01ed96960b4ad58c5b818d36c8d9
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/245885
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Sun, 7 Jul 2013 04:22:35 +0000 (09:52 +0530)]
ARM: configs: tegra12: Enable palmas pinctrl
Bug
1321104
Change-Id: I6347dbaba30c13dc2a4b6225ee5141a8af7d48b4
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/245890
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Sun, 7 Jul 2013 04:21:38 +0000 (09:51 +0530)]
ARM: tegra: Kconfig: tegra12: Select pinctrl
Bug
1321104
Change-Id: I634304221f2a706cb4b453e177728c08fc426588
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/245889
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Mon, 8 Jul 2013 10:21:57 +0000 (15:51 +0530)]
regulator: core: Mechanism to set initial voltage
Bug
1321163
Change-Id: I4cf279d27a6ad5b64f77f7f504f080e76cf8cf66
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/246071
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Manoj Gangwal [Tue, 2 Jul 2013 13:48:38 +0000 (19:18 +0530)]
arm: tegra: Add addresses for AFC
Add addressess for Audio Flow controllers
Change-Id: Ieebfdf69396b73072c888a8db51e36d12c97ddd5
Signed-off-by: Manoj Gangwal <mgangwal@nvidia.com>
Reviewed-on: http://git-master/r/244380
GVS: Gerrit_Virtual_Submit
Tested-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Nikesh Oswal <noswal@nvidia.com>
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Jay Agarwal [Fri, 28 Jun 2013 05:32:06 +0000 (11:02 +0530)]
ARM: tegra: pcie: Correct shared PADS programming
1. Remove unnecessary pad programming for both T30
and T124.
2. Move common pad programming needed by different
clients in common function to avoid any conflict
between them.
3. Remove PCIe from powergate Skip list
4. Fixed some warnings
Bug
1259551
Bug
1305915
Bug
1304277
Change-Id: Ief020c1727dc75b2f84ef5e6524d8deee74133bb
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/244324
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Alex Frid [Sun, 7 Jul 2013 06:01:06 +0000 (23:01 -0700)]
ARM: tegra: power: Parse pmu board info early
Converted pmu board info kernel command line parameter to early
parameter, since this information is needed by dvfs in early init.
Change-Id: I2beb366307abf6849932ccd38a4e952a8e83fe1f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245903
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Kirill Artamonov [Sun, 7 Jul 2013 23:46:55 +0000 (16:46 -0700)]
video: tegra: host: fix gk20a graphics recovery
Simple reset sequence using mc_enable_r doesn't work, schedule
can't switch channels afterwards.
Change fifo recovery sequence to match the one described in
specs.
Do full gk20a graphics initialization to insure successful
recovery.
bug
1320435
bug
1321178
Change-Id: I6561f80bcba8fdb48b116eb82323bde561a72f5c
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/245953
Reviewed-by: Ken Adams <kadams@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Alex Frid [Thu, 27 Jun 2013 22:18:37 +0000 (15:18 -0700)]
ARM: tegra: dvfs: Add CL-DVFS PWM mode support
Added initial support for CL-DVFS PWM interface to regulator (so far,
only I2C interface was supported). Major differences addressed in this
commit:
- PWM output control may use external buffer with dedicated GPIO
(rather than direct control from CL-DVFS h/w).
- PWM output values translation does not include LUT table; output
values are the same as register values in CL-DVFS driver output map
(for I2C output values are indexes into output map array)
- PWM interface to regulator is a single master interface, there is no
arbitration between CL-DVFS and "other" master; PWM transaction cannot
be pending, the last output value is always delivered to regulator
within one PWM period.
- PWM can be disabled at any time with no need to flush last
transaction
Also added force_out_mv dbugfs node to override CL-DVFS control of PWM
interface.
Bug
1310396
Change-Id: Icfe4f2b113753ca5bf8db87e06145200594d4ab1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245554
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Alex Frid [Sun, 7 Jul 2013 05:13:00 +0000 (22:13 -0700)]
ARM: tegra12: dvfs: Re-arrange DFLL clock initialization
Re-assigned DFLL clock init operation to late init function inside
init operation itslef (instead of external assignment during global
tegra12x clocks initialization) Added call to Cl-DVFS debug init.
Change-Id: If08175cc07329a6f828c24fdb080a3aa4f302234
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Alex Frid [Sun, 7 Jul 2013 00:39:09 +0000 (17:39 -0700)]
ARM: tegra12: dvfs: Replace crossover error with warning
Replaced error generated if PLL and DFLL V/F curves do not have
crossover point, with warning. Still use DFLL above Vmin in this
case.
Change-Id: I7c97c6aea70266a36ae88796a8f7225bed6122c1
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245876
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Alex Frid [Sun, 7 Jul 2013 00:36:07 +0000 (17:36 -0700)]
ARM: tegra12: dvfs: Round cpu voltage limits
Round minimum/maximum cpu voltage limits to cvb voltage resolution.
Change-Id: Id2e08884c31d229a62b8b6309ba8a7a55b9e32da
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245875
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Alex Frid [Sun, 7 Jul 2013 00:20:12 +0000 (17:20 -0700)]
ARM: tegra12: dvfs: Allow DFLL Vmin below dvfs table
DFLL Fmax@Vmin rate used to be determined as frequency at the point of
intersection between cpu V/F curve and DFLL Vmin. As such at least one
dvfs entry below and one dvfs entry above Vmin was required. Relaxed
this requirement to dvfs table: if all table entries are above Vmin,
just use minimum tabulated rate as DFLL Fmax@Vmin rate.
Ported from Tegra14 commit
149794e1c66ae146805a46104bdbfc2e31f1fc48
Change-Id: I4900690ba67bb4e5260e70eb032e868429c53a55
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245874
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Kaz Fukuoka [Sun, 30 Jun 2013 01:18:42 +0000 (18:18 -0700)]
video: tegra: Fix GK20a PL divider values
Add a table to map PL divider index to the actual divider value.
bug
1313612
Change-Id: I2e94d82c681fbdfa18323c9db57de48a271db8ed
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/243709
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Tested-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Lauri Peltonen [Sun, 7 Jul 2013 02:02:49 +0000 (19:02 -0700)]
ARM: tegra12: Recognize tegra12 chip family
Change-Id: If8be0f9f31033bf0adacba334304198fb1f6efb8
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/245878
Reviewed-by: Antoine Chauveau <achauveau@nvidia.com>
Tested-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Lauri Peltonen [Sat, 6 Jul 2013 12:16:07 +0000 (05:16 -0700)]
video: tegra: host: gk20a: Fix pte flushes
Page table entries were not correctly flushed from the CPU
cache because the scatterlist length was not set up properly.
Also remove a spurious cache flush whose size was incorrect (would
always flush 4k while the page directory size is actually 128k).
Bug
1320110
Change-Id: Ic71cd632c506637267e310dfd7e5b76597defbb4
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: http://git-master/r/245841
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ken Adams <kadams@nvidia.com>
Tested-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Johnny Qiu [Sat, 6 Jul 2013 22:45:00 +0000 (15:45 -0700)]
arm: tegra: laguna: fix polarity of avdd_hdmi_en
Change-Id: Ib5cff9ca42da2def2fec17663dba9dc53ddd5d44
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/245862
Reviewed-by: Automatic_Commit_Validation_User
Xue Dong [Sat, 6 Jul 2013 01:21:22 +0000 (18:21 -0700)]
arm: tegra: change HDMI parent clk
Change HDMI parent clk due to HW change in T124
Change-Id: Ie8174f6a4bfa3d05e5ee07bd50003cd66768b895
Signed-off-by: Xue Dong <xdong@nvidia.com>
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/245685
Xue Dong [Sat, 6 Jul 2013 01:15:09 +0000 (18:15 -0700)]
hdmi: clk force use pll_d2 instead of pll_d2_out
Change-Id: I9f24da18427a4c7f84e0409223ea936535b94b19
Signed-off-by: Xue Dong <xdong@nvidia.com>
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/245681
Xue Dong [Sat, 6 Jul 2013 00:59:32 +0000 (17:59 -0700)]
tegra: video: HDMI fuse set register
Change-Id: I40472b466f552c9809dfbabefef3998d6b546d9e
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/245678
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Nagarjuna Kristam [Sun, 7 Jul 2013 03:36:53 +0000 (20:36 -0700)]
ARM: tegra: adberg: Configure 32K clock for AS3722
Configure GPIO5 of AS3722 to genetate 32KHz clock
Bug
1321104
Change-Id: I1667630bf7bfd197132be52935b21102d1bbe953
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/245884
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Nikesh Oswal [Sun, 7 Jul 2013 01:06:52 +0000 (18:06 -0700)]
arm: tegra: modify device names for audio reg
Change-Id: I5abc525c092c345615e1dceb5f2c4ee2b7207dcc
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/245872
Diwakar Tundlam [Sat, 6 Jul 2013 22:36:27 +0000 (15:36 -0700)]
arm: tegra: Enable NCT72 regulator rail for Laguna board
Bug
1315460
Change-Id: I2486e743e653181f645f5f4d02aa0849b331bbc2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/245861
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Alex Frid [Sat, 6 Jul 2013 07:19:43 +0000 (00:19 -0700)]
ARM: tegra: adberg: Increase E1735 vdd cpu power good time
Bug
1310396
Change-Id: I71ff700c371fb31d236298a2dfe6b5007dd8be90
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Alex Frid [Wed, 26 Jun 2013 05:14:24 +0000 (22:14 -0700)]
ARM: tegra: adberg: Add E1735 fixed CPU regulator
Bug
1310396
Change-Id: I219239918a35f7259f4e91038ceceedc19517f5d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245552
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Alex Frid [Sat, 6 Jul 2013 05:30:06 +0000 (22:30 -0700)]
ARM: tegra12: clock: Update cpu clock mux sources
Updated cpu clock mux cclk_g sources to make sure that only low
jitter path is used for PLLX and DFLL.
Change-Id: I114963b5fd2a11ded9884ec399a26b0da0927028
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245758
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Alex Frid [Wed, 26 Jun 2013 06:26:47 +0000 (23:26 -0700)]
ARM: tegra: dvfs: Connect dvfs rail to fixed regulator
Added an option to connect dvfs rail to fixed regulator. Fixed core
rail voltage must be equal to nominal voltage. Fixed cpu rail voltage
in pll mode can be below nominal for "hybrid" configuration: fixed
regulator from s/w prospective, but scalable by CL-DVFS h/w, provided
dfll clock source is available. In this configuration maximum cpu rate
in pll mode is limited to the level matching fixed voltage, but dfll
mode supports full range of cpu rates.
Bug
1310396
Change-Id: If84fd5d02cd554a66ffdb135c62293bc117d0e1d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/245553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Kaz Fukuoka [Sat, 29 Jun 2013 21:16:35 +0000 (14:16 -0700)]
video: tegra: Add gk20a debugfs
This is a crude debugfs implementation for power demo.
- /sys/kernel/debug/gk20a/rate set/get rate [MHz]
- /sys/kernel/debug/gk20a/cap set/get rate max [MHz]
- /sys/kernel/debug/gk20a/init call gk20a_init_clk_support()
/sys/kernel/debug/gk20a/init is just for testing GK20a clock on asim.
bug
1314552
Change-Id: Ic02ce7f5f8b3259b8ac05d919bbe46b0b65151de
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/243697
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Kirill Artamonov [Sat, 6 Jul 2013 07:03:43 +0000 (00:03 -0700)]
video: tegra: host: fix gk20a register reads
Change-Id: I7f9b0f04e42fa6a94b4e4ec6c416aeecbffc9a42
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/245787
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Nikesh Oswal [Fri, 5 Jul 2013 18:22:36 +0000 (11:22 -0700)]
arm: tegra: modify audio regulators
1. modify device names for audio regulator
2. turn off the speaker rail, it was kept
as always ON, it will be dynamically turned
ON and OFF from audio driver as per the routing
Change-Id: Iada1e8ab744ab3398a6d6ccd71342491ce6e7ac1
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/245565
Nikesh Oswal [Fri, 5 Jul 2013 18:23:14 +0000 (11:23 -0700)]
asoc: tegra: remove mic regulator
For Rt5639 micvdd power is derived internally
by codec using avdd, so there is no need of
turning ON the mic regulator
Change-Id: Ie4c38042d650cbf4c54e97167407a72c78f91101
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/245566
Reviewed-by: Automatic_Commit_Validation_User
Mitch Luban [Sat, 6 Jul 2013 01:08:55 +0000 (18:08 -0700)]
configs: t124: disable cpu freq scaling
Change-Id: I1b801c3ae7d23c22323952d20884b95a4d88b223
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/245669
Johnny Qiu [Thu, 4 Jul 2013 22:11:47 +0000 (15:11 -0700)]
arm: tegra: ardbeg: use correct dev name for hdmi power rails
Change-Id: Idb4806e2989e7b516b9002fd23df1867109c562b
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/245200
Ajay Gupta [Thu, 4 Jul 2013 17:19:45 +0000 (10:19 -0700)]
ARM: tegra: update port mapping for ERS-S board
Used runtime check for board id of 0x1781 and programmed
SS port map correctly.
Change-Id: Idb7b40ed7ac4ad9cb82abbb6afb26b459a41c9fe
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/245657
Reviewed-by: Chao Xu <cxu@nvidia.com>
Ajay Gupta [Wed, 3 Jul 2013 20:12:08 +0000 (13:12 -0700)]
usb: xhci: tegra: check for USB2_P2 wake event also
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Change-Id: I41e8655495230f0817fce7e71065871892ba684f
Reviewed-on: http://git-master/r/245652
Reviewed-by: Chao Xu <cxu@nvidia.com>
Ajay Gupta [Mon, 1 Jul 2013 22:33:46 +0000 (15:33 -0700)]
usb: xhci: tegra: refine shutdown path
Ignore calling xhci_shutdown when in ELPG as we are on shutdown. Just
make sure PMC wake detect is disabled.
Issue
9629922 @https://login.corp.google.com/
Change-Id: If0912f78b671dcb191df288b11a857614369e638
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/245651
Reviewed-by: Chao Xu <cxu@nvidia.com>
Ajay Gupta [Mon, 1 Jul 2013 17:12:06 +0000 (10:12 -0700)]
usb: xhci: tegra: Refine T124+ changes
Bug
1301052
Change-Id: Iee48d3981d6ad58032894ec61735f549bec1c759
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/245650
Reviewed-by: Chao Xu <cxu@nvidia.com>
Ajay Gupta [Thu, 13 Jun 2013 16:51:55 +0000 (09:51 -0700)]
usb: xhci: tegra: fix DFE training results
Bug
1281372
Change-Id: Ia40ef4092d817bd56055cdfb971d279a10758853
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/242546
Reviewed-on: http://git-master/r/245649
Reviewed-by: Chao Xu <cxu@nvidia.com>
joyw [Fri, 7 Jun 2013 05:54:12 +0000 (13:54 +0800)]
usb: xhci: clear add_flag when no need issue bw cmd
This patch fix issue when driver tried to switch between two alt setting
with no eps and return with uncleared add_flag. This will cause later
unplug usb device, driver will clear context entries of slot context dword0
in function xhci_drop_endpoint.
Bug
1267240
Change-Id: I09afe5f640ca61663725c03619a1eb310262279e
Signed-off-by: joyw <joyw@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/236580
Reviewed-on: http://git-master/r/245648
Reviewed-by: Chao Xu <cxu@nvidia.com>
JC Kuo [Thu, 20 Jun 2013 11:31:31 +0000 (19:31 +0800)]
xhci: tegra: add firmware logging capability
This commit
1) enables firmware logging
2) reads and saves firmware log in driver buffer
3) exports firmware log via debugfs (/sys/kernel/debug/tegra_xhci/firmware_log)
bug
1301420
Change-Id: Ib59dac9ae746308451257872ec968cea4a30f4c0
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/240618
Reviewed-on: http://git-master/r/245647
Reviewed-by: Chao Xu <cxu@nvidia.com>
Kaz Fukuoka [Wed, 3 Jul 2013 23:51:23 +0000 (16:51 -0700)]
ARM: tegra12: clock: Fix XUSB ID name to tegra-xhci
XUSB platform device and other clock sources are mapped
with device name as "tegra-xhci".
Ported from http://git-master/r/190491 (change for Tegra11)
Change-Id: I44edfc3139fd1225eadcd0c2f3c7e51641bcbfa8
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/244905
Reviewed-on: http://git-master/r/245646
Reviewed-by: Chao Xu <cxu@nvidia.com>
Xue Dong [Tue, 2 Jul 2013 11:33:20 +0000 (04:33 -0700)]
arm: tegra: enable nct72 device for temp sensing and shutdown
Enable discovery of NCT72 connected to TDiode to sense Tdiode and
board temperatures. Setup interrupts via GPIO_PI6. Set shutdown
threshold temperature to 85C safe value.
Bug
1315460
Change-Id: I8b0debbf46064b8adc2aa9af0ab0fe259532c199
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/244320
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Steve Lin [Tue, 2 Jul 2013 23:36:07 +0000 (16:36 -0700)]
arm: config: tegra: Add i500 data modem support
Enable tegra_usb_modem_power driver.
Bug
1318940
Change-Id: I11cfdb726ce3c6a732c5bda51651e8cd0a7de8a7
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/244550
Reviewed-by: Chao Xu <cxu@nvidia.com>
Steve Lin [Wed, 3 Jul 2013 00:05:10 +0000 (17:05 -0700)]
cdc_ncm: using rmnet interface for icera modem
Bug
1318940
Change-Id: I4889275ab25fd4aadbb0debcd8ed8b7999cf3da5
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/244563
Reviewed-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-by: Mark Kuo <mkuo@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Animesh Kishore [Fri, 5 Jul 2013 21:51:23 +0000 (14:51 -0700)]
video: tegra: dsi: Fix DCS video for ganged mode
Bug
1283850
Change-Id: I86bc29d4fce1ea0086fbd632d1ab10d57f730a05
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/245625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Animesh Kishore [Fri, 5 Jul 2013 21:49:57 +0000 (14:49 -0700)]
arm: tegra: ardbeg: Implement DCS video mode sharp 25x16
Bug
1283850
Change-Id: I5260090578126e24420aa44cabe4d35b9e5ee7ba
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/245624
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Kaz Fukuoka [Fri, 5 Jul 2013 20:29:52 +0000 (13:29 -0700)]
ARM: tegra12: clock: Fix table and limit of PLL_D2
- VCO min/max values were wrong.
- Also fixed PLL_DP and PLL_C4.
- Separated frequency table to support exact HDMI frequency for PLL_D2.
bug
1320807
Change-Id: Ie69cd5eb44922bf4d742dd5882b571c284262ebd
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/245597
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
Krishna Sitaraman [Fri, 5 Jul 2013 18:56:33 +0000 (11:56 -0700)]
ARM: Tegra12: Clocks: Enable full EMC clock range.
Enable full safe table clocks for EMC. Using high memory clock for EMC is still
okay in terms of thermals as long as cpu and gpu dont have very high clocks.
Change-Id: I556c6085c6993efdeb5cd509a3955256ed9c5390
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/245575
Reviewed-by: Chao Xu <cxu@nvidia.com>
Pablo Ceballos [Fri, 5 Jul 2013 08:15:50 +0000 (01:15 -0700)]
mach-tegra: ardbeg: sensors: mclk_name for ar0261
Add the mclk_name to the ar0261 data in the ardbeg board file.
Change-Id: I747409d54a4654b0b5e2c8f1d21d8006670f7c5a
Signed-off-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-on: http://git-master/r/245303
Reviewed-by: Amit Arora <amita@nvidia.com>
Tested-by: Amit Arora <amita@nvidia.com>
Pablo Ceballos [Tue, 2 Jul 2013 00:51:48 +0000 (17:51 -0700)]
media: video: tegra: ar0261: move MCLK into sensor
Move MCLK control from tegra_camera into sensor driver,
to allow for full controll over MCLK rate and enable timing,
per sensor power-on/off sequence specification.
Bug
1298672
Change-Id: Iec76d84197c82fcacfb4f21edf375d724a1e3fe1
Signed-off-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-on: http://git-master/r/244059
Reviewed-by: Amit Arora <amita@nvidia.com>
Tested-by: Amit Arora <amita@nvidia.com>
Vivek Aseeja [Fri, 5 Jul 2013 06:51:55 +0000 (23:51 -0700)]
arm: config: tegra: trim mods defconfig for ardbeg
disable GK20A and GRHOST drivers
disable camera and DSI drivers
Change-Id: Ide9727ba0e88193800339c6dfbd041b0723a0851
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-on: http://git-master/r/245287
Reviewed-by: Chao Xu <cxu@nvidia.com>
Arto Merilainen [Fri, 5 Jul 2013 08:45:15 +0000 (11:45 +0300)]
video: tegra: host: Fix build errors on gk20a
A recent change added a hard dependency between nvhost and gk20a which
effectively makes the build fail on non-T124 platforms.
This patch adds a stub function to allow compilation of gk20a also
on older platforms.
Change-Id: Ifbea6179a81e5db5ef0518e802ea219840c31ba5
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/245316
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Petlozu Pravareshwar [Fri, 5 Jul 2013 12:34:45 +0000 (18:04 +0530)]
ARM: tegra: ardbeg: Update USB calibration data
USB calibration data is updated as per h/w suggestion.
Bug
1319480
Change-Id: I0d22ac463a98c648d9f3253dc31dc1a67277eba4
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/245384
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Shravani Dingari [Fri, 5 Jul 2013 11:03:04 +0000 (16:33 +0530)]
ARM: tegra: Add t124_swgid for tegra12-se
Bug
1319206
Change-Id: I6b4f0466bc6965c063f2d37c840bdda31f67bb9a
Signed-off-by: Shravani Dingari <shravanid@nvidia.com>
Reviewed-on: http://git-master/r/245293
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Johnny Qiu [Thu, 4 Jul 2013 04:45:42 +0000 (21:45 -0700)]
arm: tegra: laguna: correct pinmux for hdmi ddc
Change-Id: I44ca3ba0c028852104ad79f66c0501da5c7eb2f2
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/244968
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Chaitanya Bandi [Thu, 4 Jul 2013 15:06:11 +0000 (20:36 +0530)]
ARM: tegra: pinmux: Fix DDC_I2C pinmux setting
Fixed DDC_I2C pinmux setting in Ardbeg.
Change-Id: I9ad642568eb3d6c97556d547404293646125eb1d
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/245163
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Mitch Luban [Fri, 5 Jul 2013 01:09:58 +0000 (18:09 -0700)]
arm: tegra: enable gpu rail for laguna AMS
Change-Id: Ia0c3c78f51d5e0fdc7d04cbae6301fac527d4e83
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/245239
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Antoine Chauveau [Fri, 5 Jul 2013 03:06:00 +0000 (20:06 -0700)]
nvmap: Fix merge conflict
Assign different values to the KIND_SPECIFIED and
ZEROED_PAGES flags.
Bug
1319597
Change-Id: Id1c4f4a84c8fa37f57fc7d66124044f5d3734cca
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: http://git-master/r/245238
Reviewed-by: Adeel Raza <araza@nvidia.com>
Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Arto Merilainen [Mon, 1 Jul 2013 07:03:26 +0000 (10:03 +0300)]
video: tegra: host: gk20a: Implement fast remap
Userspace may map a buffer soon after it has been unmapped.
Currently, this operation creates much overhead as we are actually
mapping the buffer again *and* we later remove the old mapping.
This patch adds a list of buffers that are unmapped by userspace but
are still in use by hardware. If a buffer is on the list while
userspace is doing mapping, the buffer is removed from the list and
returned into use. This allows userspace to do fast remapping as
long as the hardware is still using the buffer.
Change-Id: I926dc1791d02ae31a8b8d3c3f1fcf5d848cf8521
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/243822
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Arto Merilainen [Thu, 27 Jun 2013 11:33:00 +0000 (14:33 +0300)]
video: tegra: host: gk20a: Defer unmapping
This patch adds refcounting for mapped buffers. This allows to defer
unmapping to the point when the channel has actually finished
processing the job.
Change-Id: Ibeb5da3e88b3aecf6b817a7952992d3ccfc69d9e
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/242877
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Arto Merilainen [Wed, 26 Jun 2013 06:51:00 +0000 (09:51 +0300)]
video: tegra: host: gk20a: Add mapped_buffer_lock
This patch adds locking for mapped_buffers list.
Change-Id: I5f4ae22256864e851c2604a3d2710d83981fab0b
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/242449
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Pavan Kunapuli [Thu, 4 Jul 2013 23:46:17 +0000 (16:46 -0700)]
mmc: sdio: Set SDR12,SDR25 mode support by default
All SDIO cards support SDR12 and SDR25 modes. Enabling this support in the card
capabilities by default.
Change-Id: I24ba177d7662ed22dd8e779ec08ed727d7efd7e7
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/245207
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Ashwini Ghuge [Thu, 4 Jul 2013 07:08:40 +0000 (12:38 +0530)]
ARM: tegra: ardbeg: differentiate interposer pin configs
Change-Id: Ifbd81c2254cd80f38aa3c8271b26e1f14db96a21
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/245008
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pradeep Goudagunta [Thu, 4 Jul 2013 10:34:52 +0000 (16:04 +0530)]
ARM: tegra: Add t124_swgid for serial-tegra
Bug
1319810
Change-Id: Icc90f83b97202083daff2324d056890992ae6da9
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/245077
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Ashwini Ghuge [Thu, 4 Jul 2013 10:06:35 +0000 (15:36 +0530)]
ARM: tegra: pinmux: fix T124 pinmux warnings
Change-Id: I3ecd06acf3dc927b1713347397f1d3719eefac30
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/245063
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
R Raj Kumar [Thu, 4 Jul 2013 08:19:22 +0000 (13:49 +0530)]
ARM: tegra: ardbeg: Fix voltage range for ldo6 rail
ldo6 power rail min voltage should be 1.8V
Change-Id: If1e9e228dad7870f6ed17d2eebc4c9dcdf92025f
Signed-off-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/245039
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Animesh Kishore [Thu, 4 Jul 2013 06:07:12 +0000 (23:07 -0700)]
arm: tegra: ardbeg: Implement one-shot for sharp 25x16
Change-Id: I323f0417f997127173885acfae4fd99d60291ca9
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/244993
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Animesh Kishore [Thu, 4 Jul 2013 06:06:15 +0000 (23:06 -0700)]
arm: tegra: ardbeg: Fix LCD_TE pinmux
Change-Id: I6f7eee33d8f51f5a2178e2afd9bdcf849af8d916
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/244992
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Johnny Qiu [Wed, 3 Jul 2013 23:47:06 +0000 (16:47 -0700)]
arm: tegra: laguna: t12x: set pull-up for USB vbus pins
Change-Id: I12b3c904351cd6abfff5cbe8a050a5857e1b2274
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/244903
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Shardar Shariff Md [Wed, 3 Jul 2013 17:46:34 +0000 (23:16 +0530)]
arm: tegra: ardbeg: t12x: spi:Pull up for SPI1 signals
Change-Id: I10c0ffed868895a7a473d6feb514ad6c08b94828
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/244803
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Pavan Kunapuli [Thu, 4 Jul 2013 04:26:26 +0000 (21:26 -0700)]
ARM: tegra: t124: Disable smmu for sdmmc
Disable smmu for all sdmmc instances. Enabling smmu for sdmmc
breaks the transfers.
Bug
1319012 :
Change-Id: I2a100d9a19d0330d965ca74c198765240ed046a4
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244958
Johnny Qiu [Wed, 3 Jul 2013 22:35:01 +0000 (15:35 -0700)]
arm: tegra: get board info from cmdline if there's no system serial
Minimal BL doesn't pass board info through either DT or Atag. In
this case, get board info from cmdline.
Change-Id: I9d5fd4a70c406bd1f9eb4a66e92b6e7430c88876
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Reviewed-on: http://git-master/r/244883
Kaz Fukuoka [Wed, 3 Jul 2013 00:57:01 +0000 (17:57 -0700)]
ARM: tegra12: clock: Fix xusb clock source
Change-Id: Ie3521e650606283f6b35149bd1a4fbf53e48b6a1
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/244587
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Chao Xu [Sat, 22 Jun 2013 00:41:46 +0000 (17:41 -0700)]
video: tegra: dc: Update SOR power sequence
Bug
1309089 .
Change-Id: Ia6253f8496c4b8c453d63e5486054a5bcc381157
Signed-off-by: Chao Xu <cxu@nvidia.com>
Reviewed-on: http://git-master/r/243739
Vivek Aseeja [Wed, 3 Jul 2013 16:59:30 +0000 (09:59 -0700)]
arm: config: tegra: trim mods defconfig for ardbeg
disable bluetooth, SE, wireless, HDA drivers
disable USB modem, IOMMU, APBDMA drivers
Change-Id: I8801b5aa8b800bf501ce1c18def2a0e7b788d307
Signed-off-by: Vivek Aseeja <vaseeja@nvidia.com>
Reviewed-on: http://git-master/r/244801
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Kiran Kasamsetty <kkasamsetty@nvidia.com>
Seema Khowala [Wed, 3 Jul 2013 16:26:08 +0000 (09:26 -0700)]
arm: tegra: ardbeg: t12x: Touch: changed clk2_out pinmux
-gpio mode for clk2_out is removed
-default_pinmux added for clk2_out
Change-Id: I2b96a242d2df4c06fab87282f4744d5486006e29
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/244796
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Pavan Kunapuli [Wed, 3 Jul 2013 14:00:43 +0000 (07:00 -0700)]
ARM: tegra: ardbeg: SDMMC4 ddr trim,clk limits
Set DDR50 mode trim delay to 0x4. Also, set the ddr mode and
default mode clock limits for sdmmc4.
Change-Id: I79047c805f7c6ebc66100382199e2778e77675dd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244769
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Pavan Kunapuli [Wed, 3 Jul 2013 14:16:05 +0000 (07:16 -0700)]
ARM: tegra: pinmux: Fix GMA,SDIO1,SDIO3 pad config
Fixed the offsets for different fields for the SDIO1, SDIO3, GMA
pad groups in T124 pinmux tables
Change-Id: Ia4d9fd13bcf913d8375eea6fa34588edc0cd1952
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244771
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Pavan Kunapuli [Wed, 3 Jul 2013 14:28:02 +0000 (07:28 -0700)]
mmc: sdhci: No warning for v4.0 SDhost
Warn only if a host with a version higher than v4.0 is detected.
Change-Id: Ie7cfebd5d117a5c62698e98410350f686a0e7f7a
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244772
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Pavan Kunapuli [Wed, 3 Jul 2013 14:39:34 +0000 (07:39 -0700)]
ARM: tegra: clocks: Remove sdmmc4 shared emc bus entry
Do not boost the emc clocks for sdmmc4 transfers during bringup.
This should be done once the system is stable.
Change-Id: Ie4d44c5889f94c018d7c0ba3ccc88ad90d124f24
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/244777
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Animesh Kishore [Wed, 3 Jul 2013 12:24:45 +0000 (05:24 -0700)]
video: tegra: dsi: Fix pad select for dsib
Enable dsib pad for ganged mode.
Bug
1283850
Change-Id: Id5e8c56b660db783bf00a42af0c9ca5bcbe45537
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/244742
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Animesh Kishore [Wed, 3 Jul 2013 12:21:36 +0000 (05:21 -0700)]
arm: tegra: ardbeg: Enable regulator and gpios for sharp 25x16
Bug
1283850
Change-Id: Id727c5c59de8d498c45a1632dbd2797af5ecbb85
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/244741
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Mallikarjun Kasoju [Wed, 3 Jul 2013 06:49:18 +0000 (12:19 +0530)]
arm: tegra: ardbeg: t12x: set pull-up for USB vbus pins
Change-Id: Ifc8aca53cd2aceae5f15d89f428a718209197738
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/244661
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Vineel Kumar Reddy Kovvuri [Wed, 26 Jun 2013 03:46:59 +0000 (09:16 +0530)]
video: tegra: dc: display colorbar testcase
Colorbar testcase
Change-Id: I442f3268c1e876282ea9d659763e5b910e1f2385
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/244408
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Tested-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Chaitanya Bandi [Tue, 2 Jul 2013 11:10:36 +0000 (16:40 +0530)]
ARM: tegra: clock: Fix apbdma clock entry
Fixed apbdma clock entry as per device name
Change-Id: I4428d94a5b36c09937342f77f11b56eff0ef9844
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/244300
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Vineel Kumar Reddy Kovvuri [Tue, 2 Jul 2013 10:55:47 +0000 (16:25 +0530)]
video: tegra: dsi: Added Mipi calibration clock entry
Added mipi-cal-fixed entry in tegra12 clocks file
Change-Id: I78b504aa7c9428c615ff6fb6013099bf2fe5ff53
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/244281
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Mitch Luban [Tue, 2 Jul 2013 10:04:42 +0000 (03:04 -0700)]
arm: ardbeg: register pinmux for t124 ardbeg
Change-Id: I387cc2c3ba3f2c88ba2e337115c0b1a44e3a0ea1
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/244287
Seshendra Gadagottu [Tue, 2 Jul 2013 09:19:54 +0000 (02:19 -0700)]
ARM: tegra12: clocks: Add the correct mux for cclk_g
Change-Id: Iaf16800aaf745f7b2c2e5411cc4cec821dddd61e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/244272
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
Seshendra Gadagottu [Tue, 2 Jul 2013 09:11:58 +0000 (02:11 -0700)]
ARM: tegra12: fuse: Correct initial process ids
Correct initial values for cpu/core process ids.
For bringup just use "0" for all process ids.
Change-Id: I07094470377cc5f01be70a6a276eef2e14bd6764
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/244271
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>