5 years agoARM: tegra: ardbeg: Pass vcore limits in plat data
Naveen Kumar Arepalli [Wed, 11 Sep 2013 13:25:10 +0000]
ARM: tegra: ardbeg: Pass vcore limits in plat data

Pass boot core voltage, nominal core voltage, min vcore override
voltage limits through platform data for sdmmc1/3/4.

Bug 1344651
Bug 1344649
Bug 1340258

Change-Id: Ibb234f03f0c750c3ba645280ca2d72485959a74e
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/273195
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoRM: tegra: Enable TEGRA_VDD_CORE_OVERRIDE
Naveen Kumar Arepalli [Wed, 11 Sep 2013 13:09:42 +0000]
RM: tegra: Enable TEGRA_VDD_CORE_OVERRIDE

Select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
is enabled.

SDMMC Driver uses dvfs API's to set override voltages.
Hence TEGRA_VDD_CORE_OVERRIDE should be enabled.

Bug 1344651
Bug 1344649
Bug 1340258

Change-Id: Ibe4d3d1eb0a92abde98590436bc87f4a7bb2ed76
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/273194
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agodma: tegra: De-init channel isr_handler when releasing
Chaitanya Bandi [Wed, 11 Sep 2013 08:16:18 +0000]
dma: tegra: De-init channel isr_handler when releasing

Set the isr_handler to NULL while releasing a channel

Bug 1354798

Change-Id: Idad5b3f257d1613b7a5de1e47e684ed0457fa093
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/272992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agomedia:platform:tegra:fuse id for ar0261
Amey Asgaonkar [Fri, 30 Aug 2013 02:20:44 +0000]
media:platform:tegra:fuse id for ar0261

adds code for reading fuse id for ar0261.

Bug 1330898

Change-Id: Iad27adafe34e1d0ed6165b1f8ae9c7d257beef11
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-on: http://git-master/r/268282
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: clock: Add PERIPH_ON_APB to MIPI-CAL
Kaz Fukuoka [Wed, 11 Sep 2013 18:06:42 +0000]
ARM: tegra: clock: Add PERIPH_ON_APB to MIPI-CAL

bug 1363948

Change-Id: I8df09b8d121358a56255e32147cbc6345f69151b
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/273275
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Add PERIPH_ON_APB to SATA
Kaz Fukuoka [Wed, 11 Sep 2013 17:41:50 +0000]
ARM: tegra12: clock: Add PERIPH_ON_APB to SATA

Ported from Tegar30 Change-Id: I12be16dbc2614224ba852216a645d0f84c795334

bug 1363948

Change-Id: If9e59db37969431f5c1f0a51da4c8fe82a22eb9c
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/273269
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dc: Fix CRC read on one shot mode
Michael Frydrych [Tue, 10 Sep 2013 12:44:33 +0000]
video: tegra: dc: Fix CRC read on one shot mode

Wait for frame_end interrupt at most once per flip
in one shot mode, even if CRC is read multiple times
after the flip.

bug 1366106

Change-Id: Ie872e81e85bda500caab48728b7cd4c3b7db535f
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-on: http://git-master/r/272580
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra12: Add CPU EDP support for SKU 1
Diwakar Tundlam [Tue, 10 Sep 2013 22:00:35 +0000]
arm: tegra12: Add CPU EDP support for SKU 1

Bug 1342499

Change-Id: I4913e9981df6c3222af94d3e415910bb82434ece
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/272740
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoALSA: HDA: wait for IRQ handlers
Sang-Hun Lee [Wed, 28 Aug 2013 21:11:10 +0000]
ALSA: HDA: wait for IRQ handlers

Problem description:
 - Even after disabling interrupts on the module, interrupt handlers
   could be running on other CPUs.

Fix description:
 - When disabling interrupts, also wait for any interrupt handler
   to finish as well

Bug 1353286

Change-Id: I59bde67c51341cf52ca5f7f7a31a45d9f9887666
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/267543
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>

5 years agomedia:video:tegra:as364x deafult max torch current
David Wang [Fri, 16 Aug 2013 01:31:49 +0000]
media:video:tegra:as364x deafult max torch current

Added deafult max torch current to the as364x config
and limit calculation based on max total current for
2 leds.

bug 1346615

Change-Id: I006f041728b74cc2171bebb34532af4d40d94f87
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/270955
Reviewed-by: Michael Stewart <mstewart@nvidia.com>
Reviewed-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoarm:mach-tegra:ardbeg max torch current for as364x
David Wang [Fri, 16 Aug 2013 01:39:12 +0000]
arm:mach-tegra:ardbeg max torch current for as364x

Added max torch current for as364x pdata in the
ardbeg sensor board file.

bug 1346615

Change-Id: If412fbecf61ba0f719ad7db94693042a7ee60d95
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/270954
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>

5 years agoregulator: palmas: pass regulator voltage through descriptor
Laxman Dewangan [Wed, 11 Sep 2013 09:22:59 +0000]
regulator: palmas: pass regulator voltage through descriptor

In place of adding callback to get the rail voltage of fixed rail like
extreg, chargepmup, pass the regulator voltage through descriptor.

Change-Id: I028344f363584a66c8bb46dadacb53f35b51a210
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/273023
GVS: Gerrit_Virtual_Submit

5 years agoregulator: core: provide fixed voltage in desc for single voltage rail
Laxman Dewangan [Wed, 11 Sep 2013 09:18:41 +0000]
regulator: core: provide fixed voltage in desc for single voltage rail

If given rail has the single voltage (n_voltages = 1) then provide the
rail voltage through regulator descriptor so that core can use this
value for finding voltage.

This will avoid the implementation of the callback for get_voltage() or
list_voltage() callback on regulator driver.

Change-Id: Ia148194cde37df2e5b1447e8c550072d8738af71
signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/273021
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: host: Use new MC flush API
Terje Bergstrom [Mon, 9 Sep 2013 10:52:25 +0000]
video: tegra: host: Use new MC flush API

Use new tegra_mc_flush() and tegra_mc_flush_done() to have a better
control on which MC clients are reset.

Bug 1355069

Change-Id: I759cdecbdf9e76254bcc4cd6441bbb464d0ea45b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272009
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: New tegra_mc_flush() API
Terje Bergstrom [Mon, 9 Sep 2013 10:51:01 +0000]
ARM: tegra: New tegra_mc_flush() API

Introduce new tegra_mc_flush() and tegra_mc_flush_done() calls. They
give better granilarity on which client is flushed than
tegra_powergate_mc_flush() and tegra_powergate_mc_flush_done().

Bug 1355069

Change-Id: I1723238f0b25809cabef10a3fa6a063736d92a2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272008
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Add ISPB hotreset on powergate
Terje Bergstrom [Mon, 9 Sep 2013 08:37:13 +0000]
video: tegra: host: Add ISPB hotreset on powergate

ISPB was not set to hotreset when power gating.

Bug 1355069

Change-Id: Ibdc53f4e9dea399e29660d75d361ab09359d96cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/272006
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Add VI reset sequence
Terje Bergstrom [Mon, 9 Sep 2013 07:18:07 +0000]
video: tegra: host: Add VI reset sequence

We do not reset VI from CAR, but instead only reset its MCCIF.

Bug 1355069

Change-Id: I152fdb62d3b0b82731634ed3f891ee4a7f085e0f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271961
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Alloc iomem before module init
Terje Bergstrom [Mon, 9 Sep 2013 07:46:28 +0000]
video: tegra: host: Alloc iomem before module init

Allocate and request IOMEM resources for all clients before calling
nvhost_module_init(). Also moves setting of callbacks to the SoC
specific file.

Bug 1355069

Change-Id: Ic7483dba969be8e5e985d5abbba11393afdc2a2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271960
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Add reset override
Terje Bergstrom [Mon, 9 Sep 2013 06:51:36 +0000]
video: tegra: host: Add reset override

Add a reset callback that drivers can use for overriding the default
reset sequence.

Bug 1355069

Change-Id: I789f28978d60e20e2244251e395d665da098c769
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Add register access to vi.1
Terje Bergstrom [Fri, 6 Sep 2013 10:16:18 +0000]
video: tegra: host: Add register access to vi.1

Tegra124 has one VI, but we have two channels for it, vi and vi.1. We
do that by creating a platform device vi.1. The aperture of VI needs
to be accessible from both channels.

Bug 1346075
Bug 1355069

Change-Id: I555244f14488551770f037277f4a8c267fb9aa69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271510
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Make second ISP a real device
Terje Bergstrom [Thu, 5 Sep 2013 13:15:36 +0000]
video: tegra: host: Make second ISP a real device

Second ISP is actually a separate ISP unit, not a part of first ISP.
Reflect that in device setup.

Bug 1346075
Bug 1355069

Change-Id: I5ef6c1c50b6114b97942a85ab438e49da19fce47
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/271509
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoregulator: max77660: fix compile warnings
Philip Rakity [Mon, 22 Jul 2013 10:11:20 +0000]
regulator: max77660: fix compile warnings

Change-Id: Ifd2202d642c8d8c7e29c9f8cdbd1a3ace03d54ac
Signed-off-by: Philip Rakity <prakity@nvidia.com>
(cherry picked from commit fde0f5498800b09a13b3f50d92a025a24459a991)
Reviewed-on: http://git-master/r/271470
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agonet: mhi: Fix compiler warnings
Philip Rakity [Fri, 5 Jul 2013 10:08:51 +0000]
net: mhi:  Fix compiler warnings

Change-Id: Ib862e0c63309b5fb57636a413747e414bca4cda4
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/245336
(cherry picked from commit 3bcc5973b22bcba4a14c1ba4f75f60969c867af4)
(cherry picked from commit 12ca14abb53cb653583149add13681b0133c3e90)
(cherry picked from commit 063da7274c54ccf9418eddceff4cb88c8bb6368c)
Reviewed-on: http://git-master/r/269575
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agousb: hub: enable autosuspend for all devices
Krishna Yarlagadda [Fri, 6 Sep 2013 13:47:18 +0000]
usb: hub: enable autosuspend for all devices

enable autosuspend for all the devices enumerated to
save power. If device is wakeup capable and inactive it
will suspend and no need to manually set it.

Bug 1324116

Change-Id: Ic53e4d49ededa68626e16c73d2e4babb2c84e5b4
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/271522
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoarm: tegra: spi: fix rx_tap_delay
Shardar Shariff Md [Fri, 6 Sep 2013 11:11:15 +0000]
arm: tegra: spi: fix rx_tap_delay

Instead on using rx_tap_delay value, tx_tap_delay value
is passed to SPI_RX_TAP_DELAY macro resulting in
undesired value in command2 reg.

Change-Id: I4592e98b240a7d23a81507bddf80e81008f73a7d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/271475
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: spi: Make rx_tap_delay = tx_tap_delay
Shardar Shariff Md [Tue, 10 Sep 2013 06:06:31 +0000]
arm: tegra: spi: Make rx_tap_delay = tx_tap_delay

rx_tap_delay is not being used in spi tegra driver
instead tx_tap_delay been used in place of rx_tap_delay
Making rx_tap_delay equal to tx_tap_delay to avoid any
issues when fixing rx_tap_delay issue

Change-Id: I8a06766fc217a8a2bd46ab676d579ec56ff3e22d
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/272341
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agousb: xhci: set tracking data using pmc api
Krishna Yarlagadda [Thu, 5 Sep 2013 17:28:19 +0000]
usb: xhci: set tracking data using pmc api

set tracking data using pmc api for snps when there is
atleast one snps port in use.

Bug 1334159

Change-Id: Id15f31ba487d8ad07485509002392821b99bf8f8
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270910
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agousb: snps: move tracking data to pmc
Krishna Yarlagadda [Thu, 5 Sep 2013 17:25:34 +0000]
usb: snps: move tracking data to pmc

move tracking data api to pmc code and update
using thsi api

Bug 1334159

Change-Id: Iaf9172545749c558716e94c49fb1e57587a0d25b
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270909
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tn8: SMPS10-OUT1 source the sw regulator for HDMI
Laxman Dewangan [Wed, 11 Sep 2013 07:45:40 +0000]
ARM: tn8: SMPS10-OUT1 source the sw regulator for HDMI

HDMI switch regulator is sourced by SMPS-OUT1. Registering
SMPS10-OUT1 and correcting supply of HDMI switch regulator.

bug 1364346

Change-Id: I62703d60d0e4f544dbc3c7c55ea6f3ea8652c459
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272967
Tested-by: Hayden Du <haydend@nvidia.com>

5 years agoARM: tegra: Ardbeg: Changing LDO8 LP0 voltage
Terry Wang [Wed, 4 Sep 2013 11:53:42 +0000]
ARM: tegra: Ardbeg: Changing LDO8 LP0 voltage

Changing ldo8 LP0 voltage from 1V to 0.9V for
Ardbeg with TI PMIC module E1735.

Bug 1317293

Change-Id: I3766ee888156591bca5bb6816409a43f91b4ec52
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/264216
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tn8: register all fixed regulator as part of arch init
Laxman Dewangan [Tue, 10 Sep 2013 13:26:53 +0000]
ARM: tn8: register all fixed regulator as part of arch init

In place of doing all fixed regulator registration on sys_initcall_sync(),
registering it during the tn8 drivers initialisation.

Change-Id: I1d3cd353430b893687157d414f9c8cd5e584e69c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272608

5 years agoARM: move the FIXED_REG macro definition to pmu board files.
Laxman Dewangan [Tue, 10 Sep 2013 13:25:30 +0000]
ARM: move the FIXED_REG macro definition to pmu board files.

This will avoid the duplication of the macro definition across
the power file.

Change-Id: I26573f4f0be77274a7385528ec69256b9252ff22
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272607

5 years agoregulator: fixed: add provision to register driver little late
Laxman Dewangan [Tue, 10 Sep 2013 13:20:59 +0000]
regulator: fixed: add provision to register driver little late

Some of i2c based devices register themself as the GPIO. Deferring
the fixed regulator little bit late by using subsys_initcall_sync
level of initialisation to have fixed regulator registration after
the GPIO initialisation so that driver can get all the GPIOs.

Change-Id: I21c41e13242d37dbae3e9b9164c3600d2ac02c55
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272606

5 years agoregulator: palmas: remove sleep_mode callback
Laxman Dewangan [Tue, 10 Sep 2013 07:00:58 +0000]
regulator: palmas: remove sleep_mode callback

The sleep mode of the rails are configured through the mode-sleep
property and hence providing the sleep mode callbacks duplicate the
same. Hence removing the sleep mode callbacks.

Change-Id: I9f174813dd03041ed020a9e8c5090766efbfd5fc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/272351
Reviewed-by: Automatic_Commit_Validation_User

5 years agoRevert "vide: tegra: host: fix nvmap handle leak"
Krishna Reddy [Wed, 11 Sep 2013 03:23:02 +0000]
Revert "vide: tegra: host: fix nvmap handle leak"

This reverts commit 818bd872f47e2ad5088406a101d13e1a42ff20b8.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Change-Id: I82c7968acb0543db4e4fcc0618043aae6f37bf5f
Reviewed-on: http://git-master/r/272872
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agomedia: platform: tegra: IMX135: Add preview mode
Frank Chen [Fri, 6 Sep 2013 22:26:32 +0000]
media: platform: tegra: IMX135: Add preview mode

Add 2104x1560 HDR preview mode

Bug 1359962

Change-Id: Iec82164e38b06addb18eb6f4844ea111971a8dc9
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/272247
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pablo Ceballos <pceballos@nvidia.com>
Reviewed-by: Bhushan Rayrikar <brayrikar@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoARM: tegra12: dvfs: update gpu table data
Prashant Malani [Wed, 11 Sep 2013 01:04:21 +0000]
ARM: tegra12: dvfs: update gpu table data

Incorporate latest SiVal data from 09/10/13.

Bug 1352610

Change-Id: I73d20a3d7f0be7d2acf22a5eccec98dbfb43da6f
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/272846
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agomisc: tegra-baseband: enable auto PM for Bruce
Vinayak Pane [Wed, 28 Aug 2013 01:16:32 +0000]
misc: tegra-baseband: enable auto PM for Bruce

Enable auto PM functionality for Bruce modem.

Change-Id: Ida7555691c198e1ef13ddbdfff2d39f32648414a
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/270445
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agoARM: Tegra12: Clocks: Update CPU dvfs table
Krishna Sitaraman [Thu, 5 Sep 2013 18:34:39 +0000]
ARM: Tegra12: Clocks: Update CPU dvfs table

Update CPU dvfs table with first cut of post silicon parameters and
SKU information.

Bug 1342499

Change-Id: I2737d4635c59b9361fc07bfeb6b4b4b1998bc062
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/270939
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: Tegra12: Clocks: Decode SKU information for clocks
Krishna Sitaraman [Thu, 5 Sep 2013 18:20:01 +0000]
ARM: Tegra12: Clocks: Decode SKU information for clocks

Update the speedo and procees ids for cpu to reflect the
appropriate SKU.

Bug 1342499

Change-Id: I79ec4ef57b8f8af27469900ac42f0a04cb3e3a69
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/270933
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Enable PLLE spread spectrum
Kaz Fukuoka [Tue, 10 Sep 2013 18:17:52 +0000]
ARM: tegra12: clock: Enable PLLE spread spectrum

bug 1361458
bug 1346041

Change-Id: I79057b2437ceab44e7969913c0d449d349852840
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/272669
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm: tegra: loki: enable cl-dvfs support
siddardha naraharisetti [Tue, 10 Sep 2013 02:37:06 +0000]
arm: tegra: loki: enable cl-dvfs support

Added platform data to enable cl-dvfs on loki

Bug 1363892

Change-Id: I5c1ab23bd7a72570fdc693747b0d1ed572464f51
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/272696
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra12: clock: Add host1x shared bus
Alex Frid [Mon, 9 Sep 2013 19:48:07 +0000]
ARM: tegra12: clock: Add host1x shared bus

Ported from Tegra14:
commit fc86a5f24dbb2ee59fa8a43975b8a7915fc69c6b
commit 0120b418704b6152c30b05de3689a415bad34d23
commit 8e7c3690ea540f4371ca0df8fdeb9852365ec499
commit 5003bde3cbec22f14d94af11dadf41af8de60307

Change-Id: I1e9e04496a0ba550bde2fe105583c1486c0d4837
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/272121
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarch: config: tegra enable pcie support
Anand Bhatia [Wed, 4 Sep 2013 18:38:54 +0000]
arch: config: tegra enable pcie support

Enabled config options TEGRA_PCI, PCIEPORTBUS, PCIAER,
PCIEASPM, PCI_MSI.

Change-Id: I8be6992aa5c825244910363392b489f6fa2c646d
Signed-off-by: Anand Bhatia <anandb@nvidia.com>
Reviewed-on: http://git-master/r/270225
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kiran Kasamsetty <kkasamsetty@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra12: dvfs: Update GPU tables
Prashant Malani [Fri, 30 Aug 2013 23:39:01 +0000]
ARM: tegra12: dvfs: Update GPU tables

Update GPU tables based on latest SiVal data,
as of 08/30/2013.

Bug 1352610

Change-Id: Iebadfa658df8eac24beec4f61cae0ba8a9db8ad5
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/271606
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Add AHB/APB shared buses chain
Kaz Fukuoka [Sat, 31 Aug 2013 00:53:46 +0000]
ARM: tegra12: clock: Add AHB/APB shared buses chain

So far, only top most tegra system bus SBUS was exposed as shared bus
by tegra clock framework. All system, AHB, APB clock users requested
directly SBUS rate, and SCLK:HCLK:PCLK rate ratios were fixed at 1:1:2.

This commit added AHB/APB shared buses chain on Tegra12: AHB shared
bus is a shared user of SBUs, and APB shared bus is a shared user of
AHB, respectively.

USB shared users are moved from SBUS to AHB, and SBC shared users are
moved from SBUS to APB. All other SBUS shared users are still children
of the top most SBUS. All "leaves" users in the chain are protected
with cross-bus mutex to avoid races when different segments of the
chain are updated concurrently.

The bus clocks ratios are now dynamically changed based in the rates
requested by the users of each bus. There are, however, limitations on
scaling SCLK:HCLK:PCLK dividers:
(A) H/w limitation: if SCLK >= 60MHz, must have SCLK:PCLK >= 2
(B) S/w policy limitation, in addition to (A): if any APB bus shared
user request is enabled, set HCLK:PCLK >= 2
Limitation (B) is necessary, since otherwise we can not guarantee safe
transition from HCLK:PCLK = 1:1 below 60MHz to HCLK rate above 60MHz
without under-clocking APB user.

When SBUS is throttled by thermal or EDP manager, AHB and APB buses
will be throttled as well to satisfy limitations (A) and (B).

When SBUS rate is fixed via debugfs override user, bus dividers are
also fixed as SCLK:HCLK:PCLK = 1:1:2

(Note for Tegra12: The limitation descried above may have been relaxed
on Tegra12. This issue has to be visited again once the new limitation
is clarified.)

Ported from Tegra14 Change-Id: I8d2999aa8399f86c592ee9b5ee5c66aa0d036c93

Change-Id: Idab839cd227ff9f97db2471c9168f07b6383f653
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/268796
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm:tegra:loki: enable dynamic VDD_CPU EDP management
siddardha naraharisetti [Tue, 10 Sep 2013 01:30:39 +0000]
arm:tegra:loki: enable dynamic VDD_CPU EDP management

Bug 1365048

Change-Id: I83e58e3386c5ac82e1c19ddfd212af6990957c5c
Signed-off-by: siddardha naraharisetti <siddardhan@nvidia.com>
Reviewed-on: http://git-master/r/272263
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agotegra: hdmi: add hdmi_audio capability exposure via sysfs
Emma Yan [Wed, 10 Apr 2013 08:10:27 +0000]
tegra: hdmi: add hdmi_audio capability exposure via sysfs

Add checking of the CEA extension bit 6 of byte #3 and expose this
information for userspace to set audio path properly.

Bug 1261178

(cherry-picked from commit 7cb4be8a47081a1468faa29509475eed462fb671)
Reviewed-on: http://git-master/r/218151
Change-Id: Id2780f735da13c7292f269d7ddd9a87b3d09d0d6
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271954
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: fbmon: added HDMI_Video_Format condition checking
Emma Yan [Tue, 3 Sep 2013 11:38:59 +0000]
video: fbmon: added HDMI_Video_Format condition checking

Bug 1357380

Change-Id: I4b10c31b1c5124539b648764cfae8b17b5764f0a
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271339
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/271896
GVS: Gerrit_Virtual_Submit

5 years agousb: pmc: set utmip tracking data with snps
Krishna Yarlagadda [Thu, 5 Sep 2013 17:18:53 +0000]
usb: pmc: set utmip tracking data with snps

provide api to read tracking data from snps register space

Bug 1334159

Change-Id: Ieb46f178226678295ce5ec03701209b11422bf43
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/270908
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoUSB: tegra: reinit hw fixes upon phy_on
Suresh Mangipudi [Thu, 5 Sep 2013 09:40:40 +0000]
USB: tegra: reinit hw fixes upon phy_on

H/W fixes have to be reinitialized after the tegra resumes from LP0.
TXFILL_TUNING needs to be programmed properly for resume from LP0 and
Non LP0 cases.

Bug 1347167

Change-Id: I91bd87bae31988ccf0c36f372ac5b1ca1f767557
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/270703
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

5 years agoARM: tegra: Rename defconfig for vcm30_t124.
Ashwin Joshi [Tue, 10 Sep 2013 07:30:12 +0000]
ARM: tegra: Rename defconfig for vcm30_t124.

Renamed defconfig for vcm30_t124 from:

arch/arm/configs/tegra12_vcm30_t124_defconfig

to:

arch/arm/configs/tegra_vcm30-t124_gnu_linux_defconfig

Bug 1330469
Bug 1319925
Bug 1365252

Change-Id: I16a6b15ddf42ca80041b191f5fe7c7bb9d3105a4
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/272375
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: dsi: Make phy warning verbose
Animesh Kishore [Fri, 6 Sep 2013 09:00:17 +0000]
video: tegra: dsi: Make phy warning verbose

Increase verboseness of phy timing warnings.

Bug 1357180

Change-Id: I58577cf4cbab765f23a9edae793e031fbec38a55
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/271398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: ardbeg: Fix sharp 25x16 panel timings
Animesh Kishore [Fri, 6 Sep 2013 08:59:32 +0000]
arm: tegra: ardbeg: Fix sharp 25x16 panel timings

Bug 1357180

Change-Id: If21ef99eb89e34b76ad8d22bd6c1bfb0003bc5e4
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/271397
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra: pinmux: Add drive pinmux for I2Cs in T12x
Chaitanya Bandi [Thu, 29 Aug 2013 10:24:05 +0000]
ARM: tegra: pinmux: Add drive pinmux for I2Cs in T12x

Added drive pinmux settings for all I2Cs in T12x

Bug 1347466

Change-Id: Iaeff4439f92ca2bbfb8b317758e11626da73ac5e
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/267905
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agovideo: tegra: host: Remove DEVICE_UNKNOWN
Arto Merilainen [Mon, 9 Sep 2013 11:23:14 +0000]
video: tegra: host: Remove DEVICE_UNKNOWN

nvhost scale profiles informed by DEVICE_UNKNOWN that the device
has not received idle/busy events since the last probe. This case
has never been used.

This patch replaces DEVICE_UNKNOWN by DEVICE_IDLE (on boot) and
keeps the current status untouched if nothing has changed.

Change-Id: I021d6ebf788ad9532cd25370ba30af32145aa148
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/272013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: Fix devfreq profiles
Arto Merilainen [Mon, 9 Sep 2013 11:12:58 +0000]
video: tegra: host: Fix devfreq profiles

Devfreq profiles did not inform the busyness correctly for the device
profiles. This patch adds the missing code to copy the information
correctly for the profile

Change-Id: I8603f12657be6e1723c309c5c3cf37555b377f2e
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/272012
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: nvmap: fix warnings from nvmap_free_sg_table
Krishna Reddy [Mon, 9 Sep 2013 22:15:25 +0000]
video: tegra: nvmap: fix warnings from nvmap_free_sg_table

remove checks for validity of ref and ref->handle as ref memory
may not exist during sgt free.

Change-Id: I07f075c25ec1702a3ea9dbead83ac20b54094b9c
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272162
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: gk20a: remove pmu debugfs node
Prashant Malani [Tue, 10 Sep 2013 01:06:12 +0000]
video: tegra: gk20a: remove pmu debugfs node

PMU debugfs node isn't required. The load value
is already exposed by gk20a nvhost sysfs node,
and the elpg_stats field is currently empty.

It's better to just remove the node and have all
relevant entries in one place.

Change-Id: Ia8acceff341ee8acd1e774fdf730e3700ca4ddd3
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/272252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovide: tegra: host: fix nvmap handle leak
Krishna Reddy [Mon, 9 Sep 2013 23:28:16 +0000]
vide: tegra: host: fix nvmap handle leak

nvmap pinned handle in pinned during nvhost_nvmap_pin. But it
is not unpinned during nvhost_nvmap_unpin. This holds the handle
forever and leaks the memory.
Bug 1356091

Change-Id: Ie2d884720f21527c24ea79de6f128a9b29303fdd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272190
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: tegra11: clock: Set wait count after EMC clock change
Alex Frid [Sat, 22 Jun 2013 07:29:23 +0000]
ARM: tegra11: clock: Set wait count after EMC clock change

Unconditionally update EMC_ZCAL_WAIT_CNT after EMC clock change.

Bug 1312928

Change-Id: I35a24757ed8f2cbca73393fb0d95533491524b3f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/241212
(cherry picked from commit a0919e7dbba0a39fabbfd48f8270c72288b1240c)
Reviewed-on: http://git-master/r/257681
(cherry picked from commit e04f8cd6055c34a81fa65e415c25b0b8ef84fbe3)
Reviewed-on: http://git-master/r/271886
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: clock: Add debugfs node for EMC DFS table info
Alex Frid [Sun, 16 Jun 2013 05:08:05 +0000]
ARM: tegra11: clock: Add debugfs node for EMC DFS table info

Bug 1308928

Change-Id: I9b4318a37902c78e61417e62ea1e51687bbf1ea5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239138
(cherry picked from commit 23f6e8484f9565f5f02c26a363b4b5177c9872b9)
Reviewed-on: http://git-master/r/245968
(cherry picked from commit a6a35548781184f998df2c70cc9c30b8f0b02382)
Reviewed-on: http://git-master/r/271885
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: ardbeg: added tshut info for AMS PMU
Diwakar Tundlam [Sat, 7 Sep 2013 01:58:55 +0000]
arm: tegra: ardbeg: added tshut info for AMS PMU

On ardgeb boards with AMS PMU, we need different tshut data to enable
therm-trip with soctherm. Added dynamic detection of PMU type and set
the tshut info.

Bug 1291108

Change-Id: I828cd43b98481f47cec0be8aa6dab4b6581e081f
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/271778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra12: clock: Rename "gpu" to "gpu_ref"
Kaz Fukuoka [Thu, 5 Sep 2013 23:25:24 +0000]
ARM: tegra12: clock: Rename "gpu" to "gpu_ref"

GPU PLL reference clock was mistakenly named as "gpu".

Change-Id: I5083cdfd98795002d46a68806e2c9d41282eb9a4
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/271103
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agosecurity: tlk_driver: shared req/param reg SMC
Chris Johnson [Wed, 4 Sep 2013 00:48:59 +0000]
security: tlk_driver: shared req/param reg SMC

Add support for attempting to register the req/param buffers with
TLK. If it fails, we know we're on an older TLK and have to use
phys address to indicate where the buffers are.

If the SMC succeeds, we pass the virtual pointers to the buffers
knowing TLK will map them in and use them directly. This takes
care of the coherency and reduces our dependence on phys addrs.

Once both TLK and kernel changes have been synced up, we'll remove
the legacy support.

Bug 1353314

Change-Id: I1a73ddc66f002f966e80579ac49bbbd3e64a1f72
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/269802
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarch: config: enable nvhdcp for t12x.
Marvin Zhang [Fri, 30 Aug 2013 18:55:15 +0000]
arch: config: enable nvhdcp for t12x.

bug 1347934

Change-Id: I9b7e1ca19e2891515bbce7b4e4640ffa3c4c5423
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/268657
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: dvfs: Don't apply rail maximum limit
Alex Frid [Sat, 7 Sep 2013 00:20:54 +0000]
ARM: tegra: dvfs: Don't apply rail maximum limit

Removed clipping of target rail voltage to maximum limit. No clock
domain should ever request voltage above maximum. If happened it is
a bug, and now it would hit BUG() in regulator core (applying limit
before this change just masked the bug).

Change-Id: Ic482e546cf75aa968a548ba1eaf66ebf28abe861
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271819
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Re-name rail offset variable
Alex Frid [Sat, 7 Sep 2013 00:59:09 +0000]
ARM: tegra: dvfs: Re-name rail offset variable

Re-named rail offset variable from offset_millivolts to dbg_mv_offs,
since it is controlled by debugfs only.

Change-Id: I5b218769c01538b6f152d052ea2e0d409dd5e872
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271818
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Add tegra_dvfs_ prefix
Alex Frid [Sat, 7 Sep 2013 06:32:35 +0000]
ARM: tegra: dvfs: Add tegra_dvfs_ prefix

Added tegra_dvfs_ prefix to public dvfs functions.

Change-Id: I65995465fa79f4554504a4b37fa1e8f83f83ab1c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271817
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: dc: updated tegra_hdmi_audio_config table
Emma Yan [Thu, 21 Mar 2013 11:28:42 +0000]
video: tegra: dc: updated tegra_hdmi_audio_config table

Added 241500000 pclk entry for 1440p (2560x1440) HDMI support

Bug 1254995

(cherry picked from commit 87fa6a27e55983e3bb6f472fd05677ca80874dec)
Reviewed-on: http://git-master/r/211936
Change-Id: If68cee3eed532ef06d23e6a967836fde161c3e58
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/271897
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra: power: Disable CL-DVFS clock on LP1 entry
Alex Frid [Sun, 16 Jun 2013 02:11:15 +0000]
ARM: tegra: power: Disable CL-DVFS clock on LP1 entry

Disabled CL-DVFS logic clock on LP1 entry, and re-enabled it during
resume. If running DFLL is in open loop in LP1, and there is no need
to clock closed loop logic.

Change-Id: I097aa431d99cd24d1dd6a409ad37faecf8f579dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239134
(cherry picked from commit 8b56a79525817fab6e4bc7a6d905f6544d791116)
Reviewed-on: http://git-master/r/240863
(cherry picked from commit adbe3ecbb0d81a8a5eaf548dc209cabdd2f58a51)
Reviewed-on: http://git-master/r/271888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support
Alex Frid [Wed, 24 Jul 2013 02:58:41 +0000]
ARM: tegra11: dvfs: Add AP40X sku and Vmin fuse support

- added dvfs tables for AP40X sku
- set DFLL mode Vmin with 0.9V if designated fuse is set

Bug 1326355

Change-Id: Id604580d02d820db5fcf40f77fd3afd8b9c79f35
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253188
Reviewed-on: http://git-master/r/237072
Reviewed-on: http://git-master/r/257730
(cherry picked from commit 97feb5338870afa3b0c499adc99a5554a488c78f)
Reviewed-on: http://git-master/r/271884
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: power: Add AP40X cpu EDP table
Alex Frid [Thu, 25 Jul 2013 03:46:56 +0000]
ARM: tegra11: power: Add AP40X cpu EDP table

Bug 1326355

Change-Id: I19b0a6dea4712b718477ca76f479fab0ff8b14b5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253187
(cherry picked from commit fdd98a8a7524cfe540a117cc183c9b817a935614)
Reviewed-on: http://git-master/r/257729
(cherry picked from commit eefc0988bdc336000adfe63e0477b928da0425a2)
Reviewed-on: http://git-master/r/271883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: power: Add AP40X core EDP tables
Alex Frid [Wed, 24 Jul 2013 20:51:38 +0000]
ARM: tegra11: power: Add AP40X core EDP tables

Bug 1326355

Change-Id: Ic6932da6da1aa83ce8582d68167ff50f8ea4663a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253186
(cherry picked from commit b0600e1d87f2eb30acd0ebf58baef42288a7222f)
Reviewed-on: http://git-master/r/257727
(cherry picked from commit ab2bf5b822d917b33b7e147fb4c44c6f55edee95)
Reviewed-on: http://git-master/r/271882
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11: dvfs: Increase max AMX/ADX clock rate
Alex Frid [Sun, 16 Jun 2013 06:03:06 +0000]
ARM: tegra11: dvfs: Increase max AMX/ADX clock rate

Increased maximum AMX/ADX clock rate from 19.91MHz to 24.73MHz.

Bug 1161126

Change-Id: I637eb483a570a91511ae472053bac5287ac9f92f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/239140
(cherry picked from commit d1861462d318d4c6483543f26a1f1bc6e2dc3043)
Reviewed-on: http://git-master/r/241233
(cherry picked from commit 0d4302e2f31caeea4dbce2d3c0379d5eedf57d5c)
Reviewed-on: http://git-master/r/271881
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: Use devfreq scaling for gk20a
Arto Merilainen [Mon, 29 Jul 2013 11:38:10 +0000]
ARM: tegra12: Use devfreq scaling for gk20a

This patch disables perfmon frequency scaling and enables devfreq
scaling on gk20a.

Bug 1330780

Change-Id: Ia4081128389f93f16ca7ed35aa5c4e2a956ddade
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/263239
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Use pod governor
Arto Merilainen [Mon, 9 Sep 2013 10:19:58 +0000]
video: tegra: host: gk20a: Use pod governor

This patch sets nvhost_pod to be the default devfreq governor for
gk20a.

Bug 1330780

Change-Id: I6b594b3e1c7ea0e76a36a68045fc0a94321e8d27
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/271995
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: gk20a: Don't duplicate freqs
Arto Merilainen [Mon, 9 Sep 2013 05:46:55 +0000]
video: tegra: host: gk20a: Don't duplicate freqs

gk20a clock frequencies used to be doubled in the clock structure.
This, however, has been changed and therefore the gk20a devfreq
profile has currently too small frequencies.

This patch modifies the scale profile to use clock structure
frequencies "as is".

Bug 1330780

Change-Id: I278c3ab5de23be6dc3c528122b7420aa188947c0
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/271933
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoARM: PMC: tegra12: enable IO DPD function for T124
Terry Wang [Thu, 29 Aug 2013 06:36:08 +0000]
ARM: PMC: tegra12: enable IO DPD function for T124

Enable PMC IO DPD function for T124.

Bug 1352773

Change-Id: I18387f8054957745bf3f7de70e9e5fa4ce581cb7
Signed-off-by: Terry Wang <terwang@nvidia.com>
Reviewed-on: http://git-master/r/267755
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hunk Lin <hulin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoregulator: palmas: provide enable_time through desc instead of callback
Laxman Dewangan [Sat, 7 Sep 2013 09:00:43 +0000]
regulator: palmas: provide enable_time through desc instead of callback

Change-Id: I48184f33f3e1bcc9fac1fe74d00601edd1364957
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271823
GVS: Gerrit_Virtual_Submit

5 years agoregulator: palmas: remove unused macros
Laxman Dewangan [Sat, 7 Sep 2013 08:53:12 +0000]
regulator: palmas: remove unused macros

Some macro defined on the driver file is no more used. Removing
such macros.

Change-Id: I3b2d837d595b012f9731f4e4f71d7de80cb66ce2
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271822
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoRevert "media:video:tegra: add HDR for ar0261"
Mitch Luban [Sat, 7 Sep 2013 20:50:27 +0000]
Revert "media:video:tegra: add HDR for ar0261"

This reverts commit 9de14ad78781f63ed2306f7c6f7c1f328e41e132.

Change-Id: I263a614a5afe1eee17cda5e251510e0a205d7256
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/271842
Reviewed-by: Automatic_Commit_Validation_User

5 years agoiommu/tegra: smmu: smaller preempt latency for map_pages
Hiroshi Doyu [Fri, 6 Sep 2013 10:31:32 +0000]
iommu/tegra: smmu: smaller preempt latency for map_pages

Take smaller preemption latency for map_pages since there's not much
perf improvement on this larger lock range.

Bug 1290869

Change-Id: Ic7579fe9ffe89d01ad6e7fc3e18404b742b38b50
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/271447
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoRevert "iommu/tegra: smmu: fix perf regression with map_sg"
Hiroshi Doyu [Fri, 6 Sep 2013 10:26:09 +0000]
Revert "iommu/tegra: smmu: fix perf regression with map_sg"

This reverts commit da57b0c27246871c93f5e541ba8803de95c311bf.

No perf improvement but better to have smaller preemption latency.

Bug 1290869

Change-Id: I368381c82f42ef0baf9cdd573f97ea9e9724923a
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/271446
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Replace nvmap heap management
Vandana Salve [Mon, 2 Sep 2013 14:16:46 +0000]
video: tegra: nvmap: Replace nvmap heap management

Replace nvmap heap management functionality with DMA coherent APIs
Bug 898152

Change-Id: Ia632c23c3ee86bb6017d9cb1b4280d356c2b977b

Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Change-Id: I95c9bd013841f018cf9e706b3e82a804a4a0554a
Reviewed-on: http://git-master/r/269517
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoregulator: palmas: add DT support
Laxman Dewangan [Fri, 6 Sep 2013 11:24:41 +0000]
regulator: palmas: add DT support

Add DT support for palmas regulators.

Change-Id: Ia453390de433a0bc9ca75daf2afe55523b415726
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271501

5 years agoregulator: palmas: cleanup in the roof floor and ext control handling
Laxman Dewangan [Fri, 6 Sep 2013 11:15:14 +0000]
regulator: palmas: cleanup in the roof floor and ext control handling

Use sparte ops struture for the smps which is controlled externally
and get rid of the roof_floor storage.

Change-Id: I444fd7845766d48c5215ebaf09f954b30589dda8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/271500
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: use ARRAY_SIZE() to check bounds
Diwakar Tundlam [Thu, 5 Sep 2013 22:21:14 +0000]
arm: tegra: use ARRAY_SIZE() to check bounds

Bug 1291108

Change-Id: I81c29b46481c90956acf3ff4f027cf6abdfb2338
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/271073
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

5 years agoARM: tegra12: dvfs: Add GPU rail Vmin thermal floor
Alex Frid [Fri, 6 Sep 2013 03:49:59 +0000]
ARM: tegra12: dvfs: Add GPU rail Vmin thermal floor

Implemented Tegra12 GPU rail Vmin floor 0.9V when temperature is
below 20C.

Bug 1273253
Bug 1342499

Change-Id: I5e8fce0c798145d5682c9e60c219e7f603703324
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271329
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra: dvfs: Use common rail thermal profile init
Alex Frid [Fri, 6 Sep 2013 00:13:46 +0000]
ARM: tegra: dvfs: Use common rail thermal profile init

Moved dvfs rail thermal profiles initialization to common tegra
dvfs code.

Change-Id: Iae26a9704135479bce90e108104af8569bb87848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/271328
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: use general clock framework for GPU throttling
Hyungwoo Yang [Thu, 5 Sep 2013 23:51:41 +0000]
ARM: tegra: use general clock framework for GPU throttling

Bug 1363262

Change-Id: Ic455507d191a5b980d8d54580048c2dbb7b828df
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/271123
Reviewed-by: Philip Rakity <prakity@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: ardbeg : update thermal throttling table
Hyungwoo Yang [Fri, 23 Aug 2013 20:26:53 +0000]
arm: tegra: ardbeg : update thermal throttling table

Bug 1315460

Change-Id: I47c99888eef8c6e92e9a74c8fa8c2592ccabc2f0
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/265680
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: tegra12: clock: Add "PERIPH_ON_APB" to HDA
Sang-Hun Lee [Fri, 6 Sep 2013 01:16:58 +0000]
ARM: tegra12: clock: Add "PERIPH_ON_APB" to HDA

Added "PERIPH_ON_APB" flag to HDA clocks.

Bug 1353286

Change-Id: Ia99fcaa18419fe8894b401d218e57727a867ec14
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/271279
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>

5 years agoARM: tegra: loki: update smps123 for gpu
Ray Poudrier [Fri, 6 Sep 2013 17:50:45 +0000]
ARM: tegra: loki: update smps123 for gpu

Because GPU regulator was programmed out
of range, we were falling back to SW rendering

Bug 1362416

Change-Id: I27859ea2e1e32b121610abb3bad0b168847c2907
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/271564
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Siddardha Naraharisetti <siddardhan@nvidia.com>
Reviewed-by: Tao Xie <txie@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>

5 years agovideo: tegra: nvmap: fix comment
Alex Waterman [Thu, 5 Sep 2013 21:40:28 +0000]
video: tegra: nvmap: fix comment

Fix up the punctuation and clarity of the comment for
__nvmap_validate_id_locked().

Change-Id: Ie8cf12093d5b83107c7802eb1266d87333f5b683
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/271049
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: nvmap: Fix virt mem checks
Alex Waterman [Thu, 5 Sep 2013 21:38:45 +0000]
video: tegra: nvmap: Fix virt mem checks

Make it so that __nvmap_free_sg_table() does no error checking
and that nvmap_free_sg_table does all the error checking.

Change-Id: I4e9a8953b278c9317c4baa7d3ec0daeff455e981
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/271047
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agovideo: tegra: gk20a: enable elpg.
Kevin Huang [Tue, 6 Aug 2013 17:59:32 +0000]
video: tegra: gk20a: enable elpg.

Bug 1317989

Change-Id: Ic309b934e26f064569d444e9e552f74fc1dbaddb
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/270397
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: clock: Add read fence in delayed writes
Alex Frid [Thu, 5 Sep 2013 03:02:35 +0000]
ARM: tegra: clock: Add read fence in delayed writes

Added explicit read fence after clock register writes that include
propagation delay. This is necessary on Tegra11 and Tegra12 platforms
where udelay implementation is based on CPU arch timers (on platforms
that use tegra microsecond timer for udelay, timer count read serves
as a fence).

Change-Id: I56a9af1bfa5ae7a9f6f51d129708eaa5cbd8ee27
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/270481
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>

5 years agovideo: tegra: gk20a: add ZBC save and restore.
Kevin Huang [Tue, 6 Aug 2013 17:51:22 +0000]
video: tegra: gk20a: add ZBC save and restore.

Save all ZBC entries once after PMU initialization. Save valid
entries afterwards.

Bug 1317989

Change-Id: I2cfd264e33125894d495f19f0e22be0dd593c502
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/269680
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoarm: tegra: change HDMI prod settings
Xue Dong [Fri, 6 Sep 2013 00:22:35 +0000]
arm: tegra: change HDMI prod settings

bug 1327251

Change-Id: Iaba928cd2a4d196a466a8ef77432260a8c99cc37
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/271140
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>