Jin Qian [Thu, 21 Apr 2011 19:55:47 +0000 (12:55 -0700)]
ARM: tegra: powergate: Add hot reset sequence for powergate
Original-Change-Id: I0e37b788c666ae99f46e7e6995c3700b0b23d412
Reviewed-on: http://git-master/r/29901 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R24afa8e7f33265722cee139f37ad53774d1dcb96
During dvfs initialization, change propagation of sleeping attribute
from "current_parent-to-child" to "possible_parent-to-child". This would
guarantee that any non-sleeping clock has only non-sleeping parents, and
it is no longer required for sleeping clock to be a sole parent of all
its children.
When current CPU complex frequency is above target range:
- bring new core on-line only if cpufreq governor requests for
all already on-lined CPUs are above 50% of current CPU frequency
- off-line one core (despite high pick request) if cpufreq
governor requests for at least 2 on-lined CPUs are below 25% of
current CPU frequency
- do nothing if neither of the above conditions is true
Original-Change-Id: I77e1bd543a8fadd51974f7d574f256a6e7e2979a
Reviewed-on: http://git-master/r/29702 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc5c717454d1e09ca97ccc79fff60cb33fcf854e9
Alex Frid [Wed, 20 Apr 2011 06:38:46 +0000 (23:38 -0700)]
ARM: tegra: power: Update Tegra3 CPU auto-hotplug
- taking CPU core off-line: selected CPU with minimum load
- switching from ULP to G CPU mode: set CPU clock to cpufreq
target rate after the mode switch is completed
Alex Frid [Tue, 19 Apr 2011 04:35:58 +0000 (21:35 -0700)]
ARM: tegra: power: Set minimum LP2 target residency
Added board level tuning parameter to specify minimum LP2 residency
time (previous policy allows down to zero residency targets limited
only by LP2 exit latency).
Alex Frid [Wed, 6 Apr 2011 03:24:36 +0000 (20:24 -0700)]
ARM: tegra: power: Re-initialize Tegra3 EMC after LP0
Since EMC frequency is not restored after exit from LP0, re-initialize
EMC clock with the new warm boot configuration, and make sure that the
1st after LP0 clock change does not use stale timing cache.
Skip Tegra2 specific EMC restoration on Tegra3 platforms.
Original-Change-Id: I4be0d3b839e871151c3c2158a002a0c763de34c2
Reviewed-on: http://git-master/r/26807 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2ffeb64d96a425966d258d0479b3561c4a6eb406
Alex Frid [Thu, 7 Apr 2011 03:43:55 +0000 (20:43 -0700)]
ARM: tegra: power: Add CPU EDP support
CPU electrical design point (EDP) limits specify maximum CPU frequency
depending on number of CPU cores on-line, and chip temperature. This
commit added initial edp governor to cpufreq driver. Governor is aware
of CPU departure/arrival, but temperature dependency is yet to be added.
Therefore CPU EDP support is left disabled for now.
Original-Change-Id: Ia875aa6904df7ec25ac98863d59a173703034241
Reviewed-on: http://git-master/r/26982 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iae2e9d47c2d3fd4cb32104adbad4f4b26c46064c
Jin Qian [Wed, 16 Mar 2011 19:30:41 +0000 (12:30 -0700)]
ARM: tegra: power: add partition power check before suspend
Original-Change-Id: Ie4b29d1119bc2f640891525ab781c8de1bf64ddf
Reviewed-on: http://git-master/r/23215 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idc616485ecdb9e7c39728409d91a511e1de79e05
Alex Frid [Tue, 5 Apr 2011 23:45:05 +0000 (16:45 -0700)]
ARM: tegra: clock: Modify EMC maximum rate settings
On A01 Tegra3 chip EMC rate may not reach full PLLM range - set
maximum EMC rate equal to boot rate. Use PLLM frequency as EMC
rate limit for A02+ chips.
Original-Change-Id: I0b901a29d628362b09f2a3d0ce908b4019804cfd
Reviewed-on: http://git-master/r/26786 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I741fcfca646ba0a2a8732dbccaf7a2642d839809
Original-Change-Id: I0fad4b8d931b92c8dbbdd3b6ce7dd63b42c6464f
Reviewed-on: http://git-master/r/25177 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I109a5cff6b53cfea4b48b20c9114aa4a1c02f1d8
Hiro Sugawara [Thu, 17 Mar 2011 18:19:29 +0000 (11:19 -0700)]
arm: tegra: iovmm: Move SMMU window to bottom 1GB for AVP
Tegra3 A01 continues to use the high address range.
Tegra3 A02 (and after) uses the bottom 1GB.
The new AHB register bit access has no effect to Tegra3 A01.
Original-Change-Id: I90cedbb22d9aae4307908750ebeb03bef639945c
Reviewed-on: http://git-master/r/23379 Tested-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I33253f8ae32c416a9d19694e87380dbae94c2f68
Alex Frid [Sat, 2 Apr 2011 04:25:40 +0000 (21:25 -0700)]
ARM: tegra: clock: Add clock time on statistic
Original-Change-Id: I361e00ef84ce4ca9a9c6d7340de2d095fc67a208
Reviewed-on: http://git-master/r/25180 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If382fc3b5d2ca678df8a9319a06bae967fc3c658
Alex Frid [Thu, 31 Mar 2011 03:31:30 +0000 (20:31 -0700)]
ARM: tegra: power: Modify auto-hotplug locking
Use cpufreq (cpu DFS) mutex for auto-hotplug (instead of a separate
one) to serialize cpu frequency scaling, hotplug, and CPU mode switch
operations.
Original-Change-Id: I7ea865894d1676c865294ab31a903248d9437534
Reviewed-on: http://git-master/r/24893 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I906a23561c1567079a41590a30b29b3d52fa5de8
Alex Frid [Thu, 31 Mar 2011 01:02:13 +0000 (18:02 -0700)]
ARM: tegra: clock: Add Tegra3 CPU clock round rate operation
Original-Change-Id: I9e10c8d4ed074f915769ae7c77d915d6b021e2c9
Reviewed-on: http://git-master/r/24892 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23820e1557d304d7a99417b99afaeb4a36c9d18f
Alex Frid [Sun, 13 Mar 2011 08:41:14 +0000 (00:41 -0800)]
ARM: tegra: clock: Re-factor Tegra3 cpu clocks
Added second level virtualization (on top of virtual cpu rate control)
to support different Tegra3 CPU power modes: low power (LP) mode and
geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is
defined as a child with two parents: virtual cpu_lp and virtual cpu_g
clocks for the respective modes. Mode switch sequence was integrated
into cpu_cmplx set parent implementation. (Before this commit mode
switch was triggered outside the clock framework, which created cpu
clock/mode synchronization problems).
Each mode clock is derived from its own super clock mux (cclk_lp and
cclk_g) to statically match Tegra3 h/w layout. (Before this commit the
code had to dynamically synchronize CPU mode and active mux selection).
This change also allowed to support PLLX output divider for low power
mode as fixed 1:2 divider with bypass control embedded into cclk_lp
parent section.
Updated auto and sysfs CPU mode switch calls to use new clock framework,
and removed clock manipulation from the low level mode switch
implementation.
Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b
Reviewed-on: http://git-master/r/24734 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be
Jin Qian [Fri, 25 Mar 2011 01:44:48 +0000 (18:44 -0700)]
ARM: tegra: set preset_lpj to reduce time bootup secondary cpus
Original-Change-Id: I21bf0464275dfd218084a6858bf2fb09f1eec6b6
Reviewed-on: http://git-master/r/24237 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iad6176a44f78e68578b606b77aeb9a0624248913
Scott Williams [Mon, 14 Mar 2011 22:24:46 +0000 (15:24 -0700)]
arm: tegra: timer: New Tegra3 IRQ mapping
Rename timer.c to timer-t2.c for consistency with other
chip-specific implementations.
Bug 790458
Bug 790448
Bug 738259
Original-Change-Id: I7e0fceb716590cd92b64ba00c0bebe659e9beb21
Reviewed-on: http://git-master/r/22885 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I322324c2177d57657a63e9428f8e49d5df2b828e
Scott Williams [Fri, 18 Mar 2011 20:38:02 +0000 (13:38 -0700)]
arm: tegra: Enable MC early ACK and scoreboard
Bug 791803
Original-Change-Id: I25be461cccd6e14618d8b43fd0738e9abfbe4432
Reviewed-on: http://git-master/r/23584 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I6bb5dcfbf48323919529c6271ea7696ecc413bb2
Alex Frid [Fri, 18 Mar 2011 23:40:15 +0000 (16:40 -0700)]
ARM: tegra: power: Don't enable stats interrupt on Tegra3
Tegra3 does not use stats monitor - do not blindly enable it on exit
from LP2
Original-Change-Id: I9fbcfcefc67510f6145a78edfc35362f9c059cf9
Reviewed-on: http://git-master/r/23731 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ib4797f3ab7ec047975edbaeac7c813e48b93ec0a
Alex Frid [Sun, 13 Feb 2011 01:20:43 +0000 (17:20 -0800)]
ARM: tegra: cpu: Update auto-hotplug policy
Do not switch to G cluster if cpufreq spikes above LP frequency limit
for a short time - currently set threshold to 100ms. Fixed timing
update for LP cluster statistic.
Alex Frid [Sat, 12 Feb 2011 02:17:28 +0000 (18:17 -0800)]
ARM: tegra: Update secondary CPU power up procedure
- Wait for power up status confirmation after secondary CPU was
un-gated by flow controller (instead of directly UN-gating CPU
again if the 1st status check failed).
- Enable CPU clock only after power up is confirmed.
- Insert propagation delays before and after removing clamps.
Scott Williams [Fri, 11 Feb 2011 22:37:19 +0000 (14:37 -0800)]
arm: tegra: Fix initial boot to LP cluster
Forbid cluster switch to G cluster if the G cluster doesn't exist.
Bug 791057
Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23
Reviewed-on: http://git-master/r/19302 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9
Scott Williams [Thu, 10 Feb 2011 22:35:32 +0000 (14:35 -0800)]
arm: tegra: Reserve SMMU I/O window address space
Bug 790951
Bug 791114
Original-Change-Id: I50ac8b20c1a1cd2ed5c135f940ec1791fb3dc6c0
Reviewed-on: http://git-master/r/19145 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I3406c6cc5b0733b91965983028dc5935f2ad62f8
Alex Frid [Sat, 5 Feb 2011 09:11:13 +0000 (01:11 -0800)]
ARM: tegra: Add auto-hotplug support for Tegra3
Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.
When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.
When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.
The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.
Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827
Alex Frid [Sat, 5 Feb 2011 05:41:50 +0000 (21:41 -0800)]
ARM: tegra: Shorten cluster switch timing reports
Original-Change-Id: I9e0744eb937223062e0582900fd0fb33a3ae1707
Reviewed-on: http://git-master/r/18468 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I40995652cb88c643b2e8ce5e7af707bbe7d9bfed
Scott Williams [Tue, 1 Feb 2011 20:52:39 +0000 (12:52 -0800)]
arm: tegra: Add run-time cluster switch debug control
Allow run-time control of cluster switch debug messages
so they can be enabled for debuggability and disabled for
performance measurement.
Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71
Reviewed-on: http://git-master/r/17927 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379
Scott Williams [Tue, 1 Feb 2011 03:56:16 +0000 (19:56 -0800)]
arm: tegra: Instrument cluster switch transitions
Original-Change-Id: I1526de69a1224f42ce3ff11ba1b6fa949c2f13a5
Reviewed-on: http://git-master/r/17787 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I43caec7348d970dc076f27cc2bb4b6ded234a38c
Dara Ramesh [Wed, 12 Jan 2011 04:15:54 +0000 (09:45 +0530)]
[ARM/tegra] HDA Driver support
Adding HDA audio driver support for Tegra3
Original-Change-Id: I81a76a54f6ce5390051d96dbeadf447682f9ff0e
Reviewed-on: http://git-master/r/15405 Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8525ef7317606b895818e73ec92ca174dddf609e
Laxman Dewangan [Mon, 31 Jan 2011 09:29:07 +0000 (14:59 +0530)]
arm: config: tegra: cardhu: config for Verbier E1187
Adding config variables for the Verbier E1187 configuration.
By default cardhu will be build for E1198.
The cardhu can be build for E1187 by saying config variable
CONFIG_TEGRA_VERBIER_E1187 to yes.
vdumpa [Wed, 17 Nov 2010 23:57:13 +0000 (15:57 -0800)]
tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes
Change the cacheability attributes in the normal memory remap
register (NMRR) to inner write-back write-allocate/outer write-back
no-write-allocate to improve L2 cache performance.
Bug 728231
Bug 751146
Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d
Reviewed-on: http://git-master/r/11077 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/17475 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7
Pavan Kunapuli [Wed, 26 Jan 2011 19:14:53 +0000 (11:14 -0800)]
arm: tegra: sdhci: Do not disable sdmmc4 clock
Do not switch off sdmmc4 clock. Also, removed ddr
mode temporarily from linux mmc driver.
Programming tap_delays and internal clock.
Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0
Reviewed-on: http://git-master/r/17070 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1
Alex Frid [Tue, 25 Jan 2011 06:12:28 +0000 (22:12 -0800)]
ARM: tegra: clock: Prevent parent over-clocking
Pre-set clock rate when changing parent to avoid parent over-clocking
during clock initialization from common/board specific tables. Drivers
however, may still hit over-clocking error.
Original-Change-Id: Ib101d85e90ab4c1194ac98680c930eebd8c56b76
Reviewed-on: http://git-master/r/16877 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I307e7eb507d885c381087812d262d56338aab861
Alex Frid [Tue, 25 Jan 2011 04:33:16 +0000 (20:33 -0800)]
ARM: tegra: clock: Add check for parent over-clocking
Fail clk_set_parent() interface if switching the clock parent will set
the rate above maximum limit.
Original-Change-Id: I47c0798dafe5f8f497dcacfcd23f6957244cdb0a
Reviewed-on: http://git-master/r/16876 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie5fef027411096a465ae5aa84fe84a08a769a613
Alex Frid [Sun, 23 Jan 2011 02:40:45 +0000 (18:40 -0800)]
ARM: tegra: clock: Add Tegra3 PLLE support
Original-Change-Id: Iba29ff515fd850cd0f736d5ef693877e85fb0c5c
Reviewed-on: http://git-master/r/16660 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8d6efae37847fcbda12290b6cd5d61e6a61c2777
Alex Frid [Sun, 23 Jan 2011 03:08:54 +0000 (19:08 -0800)]
ARM: tegra: clock: Propagate errors in debugfs
Original-Change-Id: I7d7f4f49cc1e41707032467197d53967d3ecaf06
Reviewed-on: http://git-master/r/16659 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I9e04b2833ef12466664cf6f6c2666d440600db08
Alex Frid [Sun, 23 Jan 2011 01:05:01 +0000 (17:05 -0800)]
ARM: tegra: clock: Add clock state debugfs control
Original-Change-Id: I2a16c36c8ee414a1f046eda2f3bdb9c1d71caf8b
Reviewed-on: http://git-master/r/16657 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Icc4b526f44697bd788d83434f6e9a62de005b09c
Hiro Sugawara [Wed, 19 Jan 2011 21:57:30 +0000 (13:57 -0800)]
[arm:tegra] Adding MC_DECERR interrupt handler
Adding MC_DECERR interrupt handler ported from Froyo.
This addition will not gracefully terminate a failing DMA transfer.
The handler does noting but simply reporting the error status with prink,
and the clinet software will likely hang forever waiting for a non-
completing DMA transfer. But it is still useful for debugging.
Original-Change-Id: I7b19c70d8cbb62be9ab3f955bf19c707c1e5045d
Reviewed-on: http://git-master/r/16590 Tested-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibdcfe63d56d22e39d8c5398ff50eb663bd0d82f3
Yen Lin [Thu, 13 Jan 2011 20:37:10 +0000 (12:37 -0800)]
arm: tegra: Add SATA support
Original-Change-Id: I18c63f1c69e155ddc1cec1718af9684d861815b7
Reviewed-on: http://git-master/r/15863 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/16485
Original-Change-Id: I6afa5a097b4fc7d6c45614107118458da0d9d888
Scott Williams [Fri, 7 Jan 2011 18:48:48 +0000 (10:48 -0800)]
arm: tegra: Enable Tegra3 cluster control
Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3
Reviewed-on: http://git-master/r/15269 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae
Scott Williams [Thu, 13 Jan 2011 22:30:20 +0000 (14:30 -0800)]
arm: tegra: Fix reserved memory area reporting
Also fixes:
- possible unitialized global variable usage.
- corruption of the LP0 code segment if there is no bootloader framebuffer.
Original-Change-Id: Ic163be339dad8b9bb3c3ffe509ccfd8ea33c8299
Reviewed-on: http://git-master/r/15875 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibc6838c412caf0e2f452a4737ec36ad67434f636
Original-Change-Id: I5b39fd8ea2284828e9cb3b5ce4330728e20b1662
Reviewed-on: http://git-master/r/15736 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I71ecd7c4426e7e82500f12d57b85a6bcc417065c
[ARM] tegra: Fixing the details of config TEGRA_FPGA_PLATFORM
Adding the details like default value and help for the config
variable TEGRA_FPGA_PLATFORM in Kconfig file.
Making cardhu as depends on Tegra3 soc architecture.
Original-Change-Id: Ib395ffa09c44a8924fdc6bf514132d98acec7bc8
Reviewed-on: http://git-master/r/15408 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic797d7f5fbcec7c7763f8fe4b694afb385e3ad4c
Scott Williams [Tue, 11 Jan 2011 18:50:52 +0000 (10:50 -0800)]
arm: tegra: Fix hardcoded frame buffer addresses
Dynamically obtain the carveout and framebuffer addresses.
Bug 769986
Original-Change-Id: I9b8eeb710e5198ab9ae4e7e6c7095cfd23209e66
Reviewed-on: http://git-master/r/15534 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia6f68817b65281bd5da4f8774476a947fd970950
Alex Frid [Sun, 9 Jan 2011 05:00:54 +0000 (21:00 -0800)]
ARM: tegra: clock: Add Tegra3 EMC shared bus
Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94
Reviewed-on: http://git-master/r/15349 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777
Scott Williams [Thu, 6 Jan 2011 01:19:58 +0000 (17:19 -0800)]
arm: tegra: Enable DCC sysfs device node
Original-Change-Id: Ifdad566dfc809771de5f66301d3a8a98a49bb679
Reviewed-on: http://git-master/r/15079 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I47af8814b72786b52c25e824c79ccf4e52ca0b62
The tag and data RAM latency values for the PL310 L2 cache controller
are different between the G and LP CPU clusters. Set the correct
cluster-dependent value whenever initializing or re-initializing
the L2 cache controller.
Original-Change-Id: I7681ebec58eaff293577269a85c51994140b1e34
Reviewed-on: http://git-master/r/15082 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I3f637783b52930f1d9303e044b645c7d136efc70
Scott Williams [Tue, 4 Jan 2011 03:17:59 +0000 (19:17 -0800)]
arm: tegra3: Fix chip unique id generation
Original-Change-Id: I1bb441213edfd6440e890e0eb77c07577168d2a9
Reviewed-on: http://git-master/r/14854 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id4470677f046ef4f3ff9f592cb5d7aafee460e07
Alex Frid [Wed, 29 Dec 2010 19:30:52 +0000 (11:30 -0800)]
ARM: tegra: clock: Update LP-cluster related interfaces
Original-Change-Id: Ifde476a05bd01cdce8c3f4802b268a193a832a1b
Reviewed-on: http://git-master/r/14584 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I41204d17c5d8092b1a24b3138efe12cfbd16d7e7
Scott Williams [Wed, 22 Dec 2010 21:44:20 +0000 (13:44 -0800)]
PARTIAL arm: tegra3: Add CPU idle support
Original-Change-Id: I5464b01ebb454b7fdc6fd316ba31de110a642063
Reviewed-on: http://git-master/r/14167 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I201cdb6dc4e78f762266cb96e48689d4d4f963f6
Scott Williams [Tue, 21 Dec 2010 17:44:12 +0000 (09:44 -0800)]
ARM: tegra3: Swap PCIE and VDE power gate controls
The PCIE and VDE power gated controls are not swapped on just
Tegra2. The swapping has been enshrined as a "feature" now.
Original-Change-Id: Iad8820570414d5377d9d6eed65a57190c4eaec7f
Reviewed-on: http://git-master/r/14000 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ieb72637c659ca05ff1a3b2c363e2d76a66f48ad8
Scott Williams [Tue, 7 Dec 2010 19:19:20 +0000 (11:19 -0800)]
[ARM/tegra] Add Tegra3 support
Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Code Review / linux-3.10.git / log