5 years agoARM: tegra: dvfs: Remove obsolete gpu_dvfs debugfs node
Alex Frid [Sat, 12 Oct 2013 04:01:23 +0000]
ARM: tegra: dvfs: Remove obsolete gpu_dvfs debugfs node

Change-Id: Idb9e5b225b2b94232200154e00f5843889516106
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/298529
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>

5 years agomedia: platform: tegra: update ov5693 driver.
Frank Chen [Thu, 3 Oct 2013 02:10:01 +0000]
media: platform: tegra: update ov5693 driver.

Update the ov5693 driver to reflect changes made during
tegranote development on serperate branch.

Fixing the following issues:
- Sluggish preview
- Pink preview in video mode

Bug 1373309
Bug 1367317

Change-Id: Ic0de85a6b783678cebfc328e38cf84c30e6bf316
Signed-off-by: Frank Chen <frankc@nvidia.com>
Signed-off-by: David Wang <davidw@nvidia.com>
Reviewed-on: http://git-master/r/298692
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agomedia: platform: tegra: update ad5823 driver
Frank Chen [Thu, 3 Oct 2013 01:37:38 +0000]
media: platform: tegra: update ad5823 driver

This is to bring the ad5823 focuser driver to
the same state of TegraNote ad5823 driver.

This should solve the focuser timeout issue.

Bug 1371717

Change-Id: I33ea762f489f38e92a024bb3c49596c96a88606b
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/282828
Tested-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agostaging: android: nvmap page pool free memory should be in other_free
Krishna Reddy [Mon, 14 Oct 2013 18:23:19 +0000]
staging: android: nvmap page pool free memory should be in other_free

nvmap page pool free memory should be added to other_free, which is
used to detect low memory conditions.
Bug 1385817
Bug 1387131

Change-Id: I60adf77c004383e43940c3fc586099f4da80a1f5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/299032
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: get dma_buf from fd
Krishna Reddy [Wed, 2 Oct 2013 21:34:14 +0000]
video: tegra: host: get dma_buf from fd

get dma_buf from fd directly when nvmap handles are
represented using fd's.

Change-Id: Iccf1e55e08c42f86e958a4ea6a8d707b44a8628d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294245
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agomedia: platform: tegra: nvavp: get dma_buf from fd
Krishna Reddy [Wed, 2 Oct 2013 21:30:15 +0000]
media: platform: tegra: nvavp: get dma_buf from fd

get dma_buf from fd directly when nvmap handles are
represented using fd's.

Change-Id: I360ff76b713ef076d3bcc03d66d656bf2ccacea5
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294243
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Soumenkumar Dey <sdey@nvidia.com>

5 years agoARM: tegra12: update tegra12_defconfig for L4T
Bibek Basu [Tue, 15 Oct 2013 09:51:47 +0000]
ARM: tegra12: update tegra12_defconfig for L4T

Enable FRAMEBUFFER_CONSOLE
Enable LOGO
Disable TEGRA_EHCI_BOOST_CPU_FREQ

Bug 1387426

Change-Id: I669d8bc4f10d80b62efd27b78e179bd5509fe0b1
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/299548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>

5 years agoRevert "usb: gadget: tegra: Reduce CPU boost trigger size"
Mitch Luban [Tue, 15 Oct 2013 22:52:42 +0000]
Revert "usb: gadget: tegra: Reduce CPU boost trigger size"

This reverts commit b0be3cdc61bc17398d2363d484366053ea097bcb.

Bug 1383091

Change-Id: I02ad6b260a62648d6cfad2e0ff889a4d6415d16f
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/299666
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>

5 years agoarm: tegra: add tegra12-se to MC clock domain
Prashant Gaikwad [Wed, 16 Oct 2013 09:52:37 +0000]
arm: tegra: add tegra12-se to MC clock domain

Bug 1307958

Change-Id: Ic99ef03be4483d664d118863b6b16f6661526f2b
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299915
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: common: fix unused variable warning
Philip Rakity [Fri, 11 Oct 2013 13:20:44 +0000]
arm: tegra: common: fix unused variable warning

/home/prakity/dev-kernel_linux/kernel/arch/arm/mach-tegra/common.c:
In function 'tegra_reserve':

/home/prakity/dev-kernel_linux/kernel/arch/arm/mach-tegra/common.c:1786:6:
warning: unused variable 'i' [-Wunused-variable

Change-Id: I91416c4720b639e3333adba242466fb022e7fedc
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/289853
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agocpufreq: Interactive: make cpufreq_interactive_tunables global
Ajay Nandakumar [Tue, 15 Oct 2013 20:32:18 +0000]
cpufreq: Interactive: make cpufreq_interactive_tunables global

Making cpufreq_interactive_tunables global so that the tuning knobs
values set from user space presist.

This needs to be re-visited once per-cpu governor is enabled.

Change-Id: I762510c8e588a73a4dfcaac95d2b6008e7fee0f4
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Reviewed-on: http://git-master/r/299598
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: host: Enable gk20a on debug spew
Terje Bergstrom [Mon, 14 Oct 2013 08:18:54 +0000]
video: tegra: host: Enable gk20a on debug spew

Change-Id: Ia5efe3c46f46ebe6494f3a023ea3d8783f0739f2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/298881
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: Add mutex for PMU dmem copy
Eric Eells [Wed, 2 Oct 2013 22:25:28 +0000]
video: tegra: host: Add mutex for PMU dmem copy

For copying data between system memory and GK20a
PMU data memory, there are two functions.
pmu_copy_to_dmem and pmu_copy_from_dmem use
registers that must have only one transaction
happening at a given time.  That is, there can be
exactly _one_ read happening or exactly _one_
write happening, but not both.  Using an atomic
integer, we could see that there were multiple
reads and writes happening simultaneously.  This
change prevents this situation by adding a simple
mutex around execution of these functions.

Change-Id: I70bf1f1c0bb4b53adfba231c6f3646d3dac63367
Signed-off-by: Eric Eells <eeells@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/289710

5 years agoarm: tegra: make sure that the PG request is accepted by PMC
Prashant Gaikwad [Tue, 15 Oct 2013 12:19:54 +0000]
arm: tegra: make sure that the PG request is accepted by PMC

The role of START bit has changed, beginning T35. To account
for bug 863229 start bit will now be cleared by HW when PMC
accepts the request to powergate or unpowergate the partition.
So in order to powergate/unpowergate a partition SW needs to
do the following.

1. Check to see if the partition is already in the correct state,
by looking at the PWRGATE_STATUS register. If not then SW reads
the PWRGATE_TOGGLE register to see if START bit is 0. If not poll
till start bit is set to 0.
2. After that program the PWRGATE_TOGGLE register with start bit
set as 1 and choose the required partition to be powrgated.
3. Ideally then SW can poll to check the START bit going back to 0,
to indicate that PMC has accepted the request.
4. Then poll the STATUS register to make sure the required partition
is powergated/unpowergated.

Also, in current implementation SW is polling REMOVE_CLAMPING_CMD to
check the CLAMP remove status. As per the HW guys this register is
write only and does no make sense polling it. Instead use CLAMP_STATUS
for polling.

Bug 1376147

Change-Id: Id34e900dff870d4d22288922ee1d0487ab4911dc
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299801
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: enabled PASR config for T124
Prashant Gaikwad [Tue, 1 Oct 2013 09:11:42 +0000]
arm: tegra: enabled PASR config for T124

Bug 1347784

Change-Id: I14679000206399188e006cfa0fe4fc8fd9c85b92
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299364
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: add PASR support for T124
Prashant Gaikwad [Tue, 15 Oct 2013 07:55:28 +0000]
arm: tegra: add PASR support for T124

This supports only LPDDR2/3 DRAM parts.

Bug 1347784

Change-Id: I5772a552938ac7c3cb20543e2b096587e0531f77
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299363
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoiommu/tegra: smmu: save and restore smmu context
Prashant Gaikwad [Tue, 15 Oct 2013 11:45:07 +0000]
iommu/tegra: smmu: save and restore smmu context

Save SMMU context before entering LP0 from cpuidle
and restore on exit.

Bug 1254633

Change-Id: I9069a9eceae1c4ab89c04d3bc40fe0f97ac5138f
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agovideo: tegra: host: gk20a: don't enable ARCH timer
Edgardo Handal [Tue, 15 Oct 2013 21:37:55 +0000]
video: tegra: host: gk20a: don't enable ARCH timer

Change-Id: I592a0bd0f4276cbab92ccf7aa95ad89c4090038b
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/299618
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agoarm: tegra: register save and restore ops
Prashant Gaikwad [Fri, 20 Sep 2013 10:17:31 +0000]
arm: tegra: register save and restore ops

Register syscore ops for modules whose context has to
saved/restore during entry/exit to LP0 state from CPU
Idle.

Bug 1254633

Change-Id: Idf4a67535754db3ccc2fc528469fb17ec198cee0
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299447
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoPM / Core: add save and restore syscore ops
Prashant Gaikwad [Fri, 20 Sep 2013 10:09:25 +0000]
PM / Core: add save and restore syscore ops

Add ops to save and restore system context when entering deep
idle state.

Bug 1254633

Change-Id: Iea36ed98544827ce73b50fcb2bf201c233baf2ca
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299446
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agommc: tegra: Set calibration offsets for all modes
Pavan Kunapuli [Tue, 15 Oct 2013 13:52:01 +0000]
mmc: tegra: Set calibration offsets for all modes

Characterization team agreed for two sets of calibration offsets - one
for 3.3V and one for 1.8V. The 1.8V offsets would be applicable for all
UHS modes and HS200 mode as well.

Calibration would be run when voltage is set. There is no requirement to
run calibration after setting UHS mode. Removing the related changes.

Bug 1347531

Change-Id: If74b0722c630a36ad53807ba64d1fffc4904920b
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/299521
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: ardbeg/loki: Fix calibration offsets
Pavan Kunapuli [Tue, 15 Oct 2013 13:35:57 +0000]
ARM: tegra: ardbeg/loki: Fix calibration offsets

Based on the latest characterization results, calibration offsets should
be set for all modes. Removing the platform data that would selectively
set calibration offsets for some modes.

Bug 1347531

Change-Id: I40e92c6b2f11a7030e0b0cc6fac03ad12767ada7
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/299520
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: tegra: add ops for vdd_core domain
Prashant Gaikwad [Tue, 15 Oct 2013 11:01:49 +0000]
arm: tegra: add ops for vdd_core domain

Before turning off VDD_CORE from CPU Idle it is
required to save context of all modules powered
from VDD_CORE rail. This change add ops to call
suspend function of all device in VDD_CORE domain.

Bug 1254633

Change-Id: I0bcacc5c7049e87f91289ccd9c2d54c9389b8ed1
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299443
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: update power state residency
Prashant Gaikwad [Thu, 19 Sep 2013 08:12:05 +0000]
arm: tegra: update power state residency

Update minimum residency expected for different power
states as derived from analysis done in bug 1347388

Bug 1347388

Change-Id: Ifd3d1e68d58a3c0bf5015b33be5ed8c926dd1e91
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/299462
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: support for FIQ debugger with secure OS
Varun Wadekar [Fri, 11 Oct 2013 07:13:03 +0000]
arm: tegra: support for FIQ debugger with secure OS

Most of the set up for the debugger is done by the secure
OS, but the kernel setup that needs to be done is done here.

Use the following config options to enable the debugger -

CONFIG_FIQ=y
CONFIG_TEGRA_FIQ_DEBUGGER=y
CONFIG_FIQ_GLUE=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_TEGRA_WATCHDOG=y
CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE=y

Bug 1326082

Original-author: Hyung Taek Ryoo <hryoo@nvidia.com>

Change-Id: If1a5dd4f158530dea6c0455ead74a8eeaa226163
Reviewed-on: http://git-master/r/#/c/261217
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/289165

5 years agovideo: tegra: t124: Add emc clocks for VI/ISP
Sudhir Vyas [Tue, 15 Oct 2013 08:51:45 +0000]
video: tegra: t124: Add emc clocks for VI/ISP

Bug 1328905

Change-Id: I473c493301bef53203feea1724d1d94369f8c529
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/299390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: tegra: Create VI/ISP emc clocks
Sudhir Vyas [Tue, 15 Oct 2013 08:49:36 +0000]
arm: tegra: Create VI/ISP emc clocks

Bug 1328905

Change-Id: Ide1c6fb232ba818598b2dc130b8c127d5113b190
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/299389
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dsi: Disable TE during OSidle
Animesh Kishore [Tue, 8 Oct 2013 14:30:41 +0000]
video: tegra: dsi: Disable TE during OSidle

Bug 1381539

Change-Id: I4758b12f782dc3c669af3937182f77e8e74c4a6a
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/289990
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: pcie: Enable PLL Power down and WAR
Jay Agarwal [Tue, 15 Oct 2013 09:25:37 +0000]
ARM: tegra: pcie: Enable PLL Power down and WAR

1. Support added for PLL power down.
2. High temp refclk disappear WAR:
CLKREQ PEX pins are used to determine whether to
drive 100MHz refclk, but some platfroms have CLKREQ
floating resulting in disappear of refclk specially
at higher temperatures. This WAR overrides CLKREQ
to always drive REFCLK and revert it later if any
device connected to RP has CLKREQ capability after
applying pullup on CLKREQ# PEX pins.

Bug 1356695
Bug 1330959

Change-Id: I9178cc748fcd28bef728dfad0f023e2ff900cd61
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/299399
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoARM: tegra: ardbeg: set LDOUSB to always on
Mallikarjun Kasoju [Tue, 15 Oct 2013 05:06:47 +0000]
ARM: tegra: ardbeg: set LDOUSB to always on

set LDOUSB to always on to get cable state of USB-ID

Bug 1360804

Change-Id: Ie89bc691f60864a1229333ba2ed8eb3339e73417
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/299295
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agonet: wireless: bcmdhd: NULL checks for dhd and wlfc state pointers
Mohan T [Wed, 16 Oct 2013 06:32:31 +0000]
net: wireless: bcmdhd: NULL checks for dhd and wlfc state pointers

On wlan reset state wlfc_state is getting cleared.
If The bw call on this stage are leading to
kernel panic. So do NULL checks for wlfc_state
and dhdp to avoid kernel panic.

Bug 1380656

Change-Id: I71255620f1c751a06ca55f7c9398ab80a4686475
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/289606
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>

5 years agoARM: tegra: pcie: Add WAR for Eye Diagram failure
Jay Agarwal [Tue, 15 Oct 2013 09:11:36 +0000]
ARM: tegra: pcie: Add WAR for Eye Diagram failure

1. Apply WAR for EYE diagram failure
2. USE board ID to distinguish implementation for
   different boards on same chip

Bug 1346141

Change-Id: I8ead24a5e8bcd00608dfa3a6d087353c2a8c22b6
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/299398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agovideo: tegra: gk20a: Fix GPCPLL lock timeout
Kaz Fukuoka [Tue, 1 Oct 2013 22:55:24 +0000]
video: tegra: gk20a: Fix GPCPLL lock timeout

bug 1372372

Change-Id: I548e19a8c611eb7e9bb8029d3a939909945b7005
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/299011
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agodrivers: nor: Make NOR mapping size configurable
Ashwin Joshi [Fri, 11 Oct 2013 10:15:06 +0000]
drivers: nor: Make NOR mapping size configurable

Keep NOR static mapping size configurable since different boards could
have NOR of different size.

Bug 1373849
Bug 1386803

Change-Id: If009fb09125ff3d6576c2a82ed82a8984bdf11d2
Signed-off-by: Ashwin Joshi <asjoshi@nvidia.com>
Reviewed-on: http://git-master/r/289676
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: tegra: dp: Implement full link training
Animesh Kishore [Wed, 2 Oct 2013 10:31:55 +0000]
video: tegra: dp: Implement full link training

Bug 1368069

Change-Id: Ibb4144a328aa5775cd9d0dbf231fc3402df070ba
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/298720
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

5 years agomedia:video:tegra: add HDR for ar0261
Amey Asgaonkar [Thu, 15 Aug 2013 00:32:11 +0000]
media:video:tegra: add HDR for ar0261

adding HDR support code for front camera
sensor ar0261.

Bug 1330898

Change-Id: I455d8d9fc8b529ea0bd35ce4538932fd48b6882a
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Reviewed-on: http://git-master/r/299108
Reviewed-by: David Wang (SW-TEGRA) <davidw@nvidia.com>
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoextcon: palmas: don't check line state
Mallikarjun Kasoju [Tue, 15 Oct 2013 05:05:18 +0000]
extcon: palmas: don't check line state

No need to check line state for getting cable state.

Bug 1360804

Change-Id: Id1b591939f5aa931281cbb32336d3234d0b23c4a
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/299294
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoarm: ardbeg: board file change for maxim touch
Xiaohui Tao [Fri, 20 Sep 2013 20:37:30 +0000]
arm: ardbeg: board file change for maxim touch

Bug 1364399

Change-Id: I4c8f854e7d3c08dcf6d91350c41a490ffdeb2f7e
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289391
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoxhci: tegra: Fix bias pad power control
joyw [Fri, 13 Sep 2013 09:59:52 +0000]
xhci: tegra: Fix bias pad power control

Per UTMIP software guideline document, if xusb own OTG port0,
use xusb padctl register space to power on/off bias pad.

Bug 1334491

Change-Id: I8037cd2811b6069e7c19957975a7e12b05cd834c
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/289624
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: Redefine SWGROUP ID
Hiroshi Doyu [Fri, 11 Oct 2013 08:19:28 +0000]
ARM: tegra: Redefine SWGROUP ID

Redefine SWGROUP ID for the future chips with more HWAs.

Also modified how to calculate MC_SMMU_<SWGROUP ID>_ASID_0 offset from
ID in SMMU in order not to break git bisctability.

Change-Id: If7239e626fba6e935a48b525897ed7e592882a0a
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/299346
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: la: program bbc ptsa dynamically
Krishna Reddy [Tue, 6 Aug 2013 23:23:07 +0000]
arm: tegra: la: program bbc ptsa dynamically

program bbc ptsa dynamically based on bw requested for BBCR and BBCW
add sysfs nodes to disable display, bbc ptsa's.
Bug 1322650

Change-Id: I8dbb9445c1fa9ca32072c77a9193164925aaa8da
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/272179
(cherry picked from commit 0ec1afbc0d38fbbe3a86542169f137d6c4241ae3)
Reviewed-on: http://git-master/r/294241
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: dsi: Fix unbalanced clk API calls
Vineel Kumar Reddy Kovvuri [Mon, 7 Oct 2013 07:53:41 +0000]
video: tegra: dsi: Fix unbalanced clk API calls

Fixes unbalanced clk enable disable calls

Bug 1376053

Change-Id: I9a6933fa21b91989c5f36f110c47690455148909
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/288740
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

5 years agousb: xhci: tegra: Fix error in non-SMP build
Edgardo Handal [Mon, 14 Oct 2013 17:22:38 +0000]
usb: xhci: tegra: Fix error in non-SMP build

Bug 1386515

Change-Id: Ic297f5a4fe08888b71062f284ad75b62e7393ee8
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/299015
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm: t124: fury: update fury dtb to latest status.
Hayden Du [Tue, 15 Oct 2013 05:25:44 +0000]
arm: t124: fury: update fury dtb to latest status.

Change-Id: Id68caa538b987d18597191aff82f5734dc02979f
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/299303
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoinput: touch: maxim_sti: Update to version 1.4.1, v28
Andy Chiang [Fri, 13 Sep 2013 09:44:16 +0000]
input: touch: maxim_sti: Update to version 1.4.1, v28

Fast-forward code from the first maxim code drop.

Bug 1364399

Change-Id: I01f1078b6c4942cd3e5102c0c33d823b54bb56e8
Signed-off-by: Andy Chiang <achiang@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289390
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>

5 years agoarm: ardbeg: defconfig change for adding maxim touch
Xiaohui Tao [Thu, 26 Sep 2013 00:00:30 +0000]
arm: ardbeg: defconfig change for adding maxim touch

Bug 1364399

Change-Id: I0ed38a61aff83c28ddad0aa070f18f1130d13b93
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Signed-off-by: Hayden Du <haydend@nvidia.com>
Reviewed-on: http://git-master/r/289388
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agoArm: tegra12: actmon: Update count_weight for T124
Puneet Saxena [Tue, 15 Oct 2013 14:54:11 +0000]
Arm: tegra12: actmon: Update count_weight for T124

T124 takes 4 emc clocks for each memory transaction.
Hence updating weight as "4 * memory_transaction_per_sample"
for Actmon actvity counter.

Bug 1385877

Change-Id: I12df367478630113c7bfc6161a714deb590b0d63
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/299535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoarm:tegra:ardbeg: export SAR detection I/O
Greg Heinrich [Thu, 10 Oct 2013 11:36:24 +0000]
arm:tegra:ardbeg: export SAR detection I/O

Export GPIO50. This is used to notify baseband of SAR
detection changes.

bug 1357692

Change-Id: I850b8f9fcffb7629e5c6d4dd063109b284cfdf3d
Signed-off-by: Greg Heinrich <gheinrich@nvidia.com>
Reviewed-on: http://git-master/r/298971
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Herve Fache <hfache@nvidia.com>
Reviewed-by: Martin Chabot <mchabot@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agotegra: hdmi: support HDMI VSDB VIC parsing
Emma Yan [Mon, 30 Sep 2013 13:39:14 +0000]
tegra: hdmi: support HDMI VSDB VIC parsing

Bug 1167856
Bug 1357380
Bug 1366416
Bug 1369156
Bug 1375947

(cherry-picked from commit f649c7aded9902bbeb6e79423e1af87553441949)
Change-Id: Ifd2fce407405bed92d8c399c742635f6e9c59918
Signed-off-by: Emma Yan <eyan@nvidia.com>
Reviewed-on: http://git-master/r/280300
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/299001
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra: dvfs: add missing arg to warn
Philip Rakity [Fri, 27 Sep 2013 11:54:58 +0000]
ARM: tegra: dvfs: add missing arg to warn

/nvidia/DEV_KERNEL/kernel/arch/arm/mach-tegra/dvfs.c:
In function 'dvfs_rail_update':
/nvidia/DEV_KERNEL/kernel/arch/arm/mach-tegra/dvfs.c:417:3:
warning: format '%s' expects a matching 'char *' argument [-Wformat]

Change-Id: I3b012fdcc12ec364a8e82c3e9eea65be915bc5fc
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/298534
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Remove unrelated to code comment
Alex Frid [Sat, 12 Oct 2013 04:36:00 +0000]
ARM: tegra12: clock: Remove unrelated to code comment

Change-Id: Ifd0be95f4b48ba9de71f48406e5aa42466dd35e4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/298535
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: ardbeg: Tristate CL-DVFS PWM data output
Alex Frid [Sat, 12 Oct 2013 07:06:05 +0000]
ARM: tegra12: ardbeg: Tristate CL-DVFS PWM data output

All PWM regulators used with Ardbeg platforms require PWM input to be
tri-stated during boot. So far, it was done by tri-stating external
level shifter connected between tegra PWM output and regulator input.
New version of the PWM regulator does not need level shifter, so PWM
output must be tri-stated directly.

Bug 1349163

Change-Id: Iff636dca645ac96aec2f94a9fff97cb7ac90de28
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/298709
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: dvfs: Explicitly enumerate CL-DVFS PWM buses
Alex Frid [Sat, 12 Oct 2013 06:32:04 +0000]
ARM: tegra: dvfs: Explicitly enumerate CL-DVFS PWM buses

Defined explicit enumeration for supported Cl-DVFS PWM configurations:
- 1-wire bus with external buffer between CL-DVFS data output and PMIC
input
- 1-wire bus with direct connection from CL-DVFS data output and PMIC
input
- 2-wire bus with direct connection from CL-DVFS data/clock outputs
and PMIC inputs

Re-factored PWM control code to use this explicit definitions instead
of inferring bus configuration from gpio and/or pingroup specification
in platform data.

Populate bus enumerations entries in platform data on platforms that
use Cl-DVFS PWM interface (ardbeg and loki Tegra12 platforms).

Bug 1349163

Change-Id: I1af3a7c2ee189f891b7639d4cbed9f057355b9cf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/298708
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agovideo: tegra: host: Fix power gating at unblank
Terje Bergstrom [Mon, 14 Oct 2013 08:18:08 +0000]
video: tegra: host: Fix power gating at unblank

When display is unblanked, we set can_powergate to false. This causes
nvhost_module_power_on() to skip calling to rail un-gating.

Bug 1385539

Change-Id: Iebdf94c39bca79207adfc150b79f1d489720ba57
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/298880
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLC2/3 filter settings
Kaz Fukuoka [Thu, 26 Sep 2013 23:52:08 +0000]
ARM: tegra12: clock: Update PLLC2/3 filter settings

Using old values until PROD values are ready for Tegra12.

Ported from Tegra11 Change-Id: I374e39fe30a7326105aca9012857e5783b2949ff

Bug 1339555

Change-Id: Ic32c1de265e709fafac38fcdaad67fbfb31e05b1
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/290008
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLD cpcon settings
Krishna Sitaraman [Fri, 11 Oct 2013 20:38:58 +0000]
ARM: tegra12: clock: Update PLLD cpcon settings

Update PROD setting for PLLD when N greater than 1000

Bug 1339555

Change-Id: I95eee519601cec37bf8f4dfcf218de500d3d481a
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/289997
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLD/U cpcon settings
Kaz Fukuoka [Thu, 26 Sep 2013 23:49:49 +0000]
ARM: tegra12: clock: Update PLLD/U cpcon settings

Using old values until PROD values are ready for Tegra12.

Ported from Tegra11 Change-Id: I5b24b0375f8e756d44cd64220ac4655bc0624d2d

Bug 1339555

Change-Id: I104929d06b12833b8bb4378aba3c94661f91ed08
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/289947
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra12: clock: Update PLLD configuration
Kaz Fukuoka [Mon, 30 Sep 2013 22:33:43 +0000]
ARM: tegra12: clock: Update PLLD configuration

Using old values until PROD values are ready for Tegra12.

For non-tabulated PLLD output rates selected comparison frequency
according to recommendations in pll specification.

Ported from Tegra11 change Icb652d9dd5d0131e959f7cd280e5d8e41960f7af

Bug 1339555

Change-Id: I4c67a16791a878913ce354c7d268272e920f0a60
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/289946
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoRevert "ARM: tegra: Redefine SWGROUP ID"
Hiroshi Doyu [Mon, 14 Oct 2013 11:39:57 +0000]
Revert "ARM: tegra: Redefine SWGROUP ID"

This reverts commit d6d56590c5c36d2f6e172e8e0e26d100be5125a3.

Change-Id: I855b4ce189ec3756f41a7c5c17194af6cc65a235
Reviewed-on: http://git-master/r/298949
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: Keep ISP & VI powered up
Terje Bergstrom [Wed, 2 Oct 2013 07:13:14 +0000]
video: tegra: host: Keep ISP & VI powered up

Keep ISP & VI powered on when the channel is open.

Change-Id: I808761b2b38ad0a2e9b9faa1b571a6dafce3df30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288829
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: Clock gate keepalive device
Terje Bergstrom [Wed, 2 Oct 2013 07:10:43 +0000]
video: tegra: host: Clock gate keepalive device

Change behavior of keepalive to allow clock gating, but prevent
power/rail gating.

Change-Id: Ia3e832daad77a0049992374a4e3cfe9f87cce663
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288828
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: Fix ISPB memory client id
Terje Bergstrom [Thu, 26 Sep 2013 05:57:15 +0000]
ARM: tegra: Fix ISPB memory client id

Change-Id: I90ade967f704a0ab2761e156242d24d74528717e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288827
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agovideo: tegra: host: gk20a: add elpg stats knob
Prashant Malani [Thu, 10 Oct 2013 21:00:34 +0000]
video: tegra: host: gk20a: add elpg stats knob

Add a debugfs knob to calculate the time spent in ELPG.
These values are preserved across rail-gates.

Bug 1349649

Change-Id: I8e5fbc03574d0ad177dded01a3678ea10ad1718f
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/289506
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: use dma apis for host1x_cdma.c
Deepak Nibade [Wed, 9 Oct 2013 07:01:19 +0000]
video: tegra: host: use dma apis for host1x_cdma.c

- use dma_alloc_writecombine()/dma_free_writecombine() apis to
  allocate/free memory instead of nvhost_memmgr apis

Bug 1380150

Change-Id: Icee0154886217c4c348c25896cf27e80cb1461ed
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/288994
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: make VIC firmware read-only
Deepak Nibade [Thu, 10 Oct 2013 10:01:21 +0000]
video: tegra: host: make VIC firmware read-only

- use dma_alloc_attrs() to allocate memory for VIC firmware
- pass 'DMA_ATTR_READ_ONLY' to above API to make the memory
  read-only

Bug 1309863
Bug 1380122

Change-Id: Ifef29474289e7c456e74cedba91750b021926513
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/288993
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agovideo: tegra: host: make TSEC firmware read-only
Deepak Nibade [Mon, 7 Oct 2013 06:37:05 +0000]
video: tegra: host: make TSEC firmware read-only

- use dma_alloc_attrs() to allocate memory for TSEC firmware
- pass 'DMA_ATTR_READ_ONLY' to above API to make the memory
  read-only

Bug 1309863
Bug 1380129

Change-Id: Ie6223116c885d8061794c2cc0ae1a3e28a79893f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/288992
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agocpufreq: Fix tracing for CPU scaling
Antti P Miettinen [Sun, 13 Oct 2013 14:19:49 +0000]
cpufreq: Fix tracing for CPU scaling

Make sure that CPU frequency change requests get always traced.

Change-Id: I69c70150f44bb3baf934ca08a7cbe1c86fe3e135
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/298730
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agousb: gadget: tegra: Add callback to boost_enable
Antti P Miettinen [Mon, 30 Sep 2013 10:14:58 +0000]
usb: gadget: tegra: Add callback to boost_enable

Cancel PM QoS request upon enabled to disabled
transition.

Change-Id: Iaf28d2d0daca312996e2cb1a1280769d814fd066
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/280232
(cherry picked from commit 9a25a04c42ed0feeb1aff1dcf696b54e122a8c65)
Reviewed-on: http://git-master/r/298663
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoinput: cfboost: Add module parameter callback
Antti P Miettinen [Tue, 1 Oct 2013 13:37:57 +0000]
input: cfboost: Add module parameter callback

Cancel PM QoS request upon frequency changing to zero.

Change-Id: Ie6bba1eb3f3177751449d53d9237e021140edf82
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/280744
(cherry picked from commit 8623a52d17f0e0788d393fbc4e8a9b2987ae492d)
Reviewed-on: http://git-master/r/298662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra11: add INT_RTC as a wakeup source
Antti P Miettinen [Tue, 8 Oct 2013 11:17:57 +0000]
ARM: tegra11: add INT_RTC as a wakeup source

Required for suspend_sanity test.

Change-Id: I6a4e24ad7a65e4e8b8c49ca4854e1c06933e218c
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/289151
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agommc: tegra: Add DFS disable knob
Antti P Miettinen [Mon, 16 Sep 2013 20:26:29 +0000]
mmc: tegra: Add DFS disable knob

For testing purposes it is useful to be able to disable
scaling.

Change-Id: I591cbab92ad78ba5d265d8d049e303040e04dc26
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/289126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: tegra12: smmu: remove dependency on ppcs1/2
Krishna Reddy [Tue, 1 Oct 2013 19:09:33 +0000]
arm: tegra12: smmu: remove dependency on ppcs1/2

remove incorrect dependency on swgids ppcs1 and ppcs2.

Change-Id: I7a13ea4d01f0dca92b1994a3027f47e6435836d7
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294250
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoiommu/core: Error rewinding for map_{pages,sg}()
Hiroshi Doyu [Thu, 10 Oct 2013 07:13:24 +0000]
iommu/core: Error rewinding for map_{pages,sg}()

Similiar with other IOMMU API, add clean up at error.

Bug 1375251

Change-Id: Ie5461eb557b3d4ad7dd0605f37afba9ffc038d6b
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/288845
Reviewed-on: http://git-master/r/289611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agomm: Expose lazy vfree pages to control via sysctl
Hiroshi Doyu [Fri, 12 Apr 2013 09:43:43 +0000]
mm: Expose lazy vfree pages to control via sysctl

Create "/proc/sys/lazy_vfree_pages" file to control lazy vfree pages

Bug 1238957

Change-Id: I75a296ae035d8cedb817319d8f4a5579ae6cf1ba
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/289616
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: Redefine SWGROUP ID
Hiroshi Doyu [Fri, 11 Oct 2013 08:19:28 +0000]
ARM: tegra: Redefine SWGROUP ID

Redefine SWGROUP ID for the future chips with more HWAs.

Also modified how to calculate MC_SMMU_<SWGROUP ID>_ASID_0 offset from
ID in SMMU in order not to break git bisctability.

Change-Id: Ie024985ae3fbbcf555199b951107f84346bb702d
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/289637
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agobase: dma-coherent: fix overflow issue
Krishna Reddy [Wed, 9 Oct 2013 05:20:56 +0000]
base: dma-coherent: fix overflow issue

fix overflow issue during coherent memory free.
Bug 1375907

Change-Id: Ib7164508acf9dd399d1028bd07c5b532c205aa02
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/283737
(cherry picked from commit 8cd3e197e00cb4402f0b6d01aa3ea7412baaf58d)
Reviewed-on: http://git-master/r/294259
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vandana Salve <vsalve@nvidia.com>

5 years agovideo: tegra: dc: get dma_buf from fd
Krishna Reddy [Wed, 2 Oct 2013 21:33:01 +0000]
video: tegra: dc: get dma_buf from fd

get dma_buf from fd directly when nvmap handles are
represented using fd's.

Change-Id: I9593e144f850d0852b091e7966278220d8fb4c06
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294244
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agomedia: platform: tegra: nvavp: fix error checks
Krishna Reddy [Wed, 2 Oct 2013 21:28:26 +0000]
media: platform: tegra: nvavp: fix error checks

fix error checks for dmabuf api calls.

Change-Id: Ief53a5bff5f5e467eaf3faa20c093c9052db7aa7
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294242
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: nvmap: handle fd to id failure
Krishna Reddy [Wed, 2 Oct 2013 22:37:11 +0000]
video: tegra: nvmap: handle fd to id failure

hande fd to id failure correct.

Change-Id: I0b3b201579dc0f010f67231555c2c1a294a79039
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/294248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: nvmap: handle page fault for CMA mem correct
Krishna Reddy [Thu, 10 Oct 2013 23:51:11 +0000]
video: tegra: nvmap: handle page fault for CMA mem correct

CMA reserves memory, which keeps pfn as valid. When
pfn is valid vm_insert_pfn should not be used.
Bug 1279160

Change-Id: I333e2a6e5825db2ee5d60f5cfa1fc0ca38e657b6
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289419
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: dc: hdmi: remove dangling pointer
Jong Kim [Thu, 11 Jul 2013 22:43:30 +0000]
video: tegra: dc: hdmi: remove dangling pointer

Remove dangling pointer by removing kfree in tegra_dc_add_modes.
specs.modedb is allocated by tegra_dc_add_modes(), but is consumed
by tegra_fb_update_monspecs(), so releasing specs.modedb creates a
dangling pointer and make the system crashed, especially when the
system suspends to lp0.

bug 1264520

Change-Id: Ic944e75b631800ed552b7e56b5799a3e60b48afe
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/248089
(cherry picked from commit e00bcba1c2d54f91d9ff93c5f8fd61c40a9ab5bd)
Reviewed-on: http://git-master/r/289277
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agovideo: tegra: hdmi: set VIC for all aspect ratios
Xue Dong [Fri, 27 Sep 2013 01:42:19 +0000]
video: tegra: hdmi: set VIC for all aspect ratios

bug 1374561

Change-Id: I3db9b42e41d2d20bea5ca52360ed7250daa41000
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/290005
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agotegra: video: fix polarity setting for 4k modes
Xue Dong [Wed, 2 Oct 2013 00:21:22 +0000]
tegra: video: fix polarity setting for 4k modes

bug 1375552

Change-Id: I09b4d639751c99f5768f2cf2324c9a810b95484e
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/290007
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agotegra: dc: add hdcp reset in handle_recheck_edid_l
sharath [Tue, 8 Oct 2013 00:41:00 +0000]
tegra: dc: add hdcp reset in handle_recheck_edid_l

Added HDCP reset logic in handle_recheck_edid_l to pass HDCP Compliance.

bug 1382386
bug 1382265

Change-Id: I9e53be05f36b6dfc90bd610760e4a2bdc2970c8c
Signed-off-by: sharath <ssarangpur@nvidia.com>
Reviewed-on: http://git-master/r/284333
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/298490
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

5 years agoARM: tegra12: clock: Decouple bus limits from bus state
Alex Frid [Tue, 1 Oct 2013 05:04:39 +0000]
ARM: tegra12: clock: Decouple bus limits from bus state

Select BUS_RATE_LIMIT flag for cap, and floor users of Tegra12 shared
buses: c2bus, c3bus, gbus, and host1x bus. Hence, applying/removing
(enabling/disabling) the limits won't affect bus enable/disable state.
Made sure that bus rate is retained in case when only limit clocks are
enabled (for gbus that supports rate retention).

Note that bus caps were already initialized as always on clocks, and
that effectively decoupled caps from the parent bus state; floors,
however, are decoupled by this commit.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: I905e9fbeafd9c2afe10f0e417477a0551d598bcb
Reviewed-on: http://git-master/r/289518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: clock: Update memory PLL resume state
Alex Frid [Thu, 3 Oct 2013 00:09:19 +0000]
ARM: tegra12: clock: Update memory PLL resume state

On exit from LP0 suspend EMC clock configuration is set by bootrom,
and it may be different from the suspend state. It may create the
following differences in h/w and s/w states:
(a) New EMC parent PLL does match parent recorded in s/w
(b) EMC divider does not match value recorded in s/w
(c) New parent PLL state and usage does not match s/w usage refcount
(d) Old parent PLL state and usage does not match s/w usage refcount
(e) EMC parent PLL rate does not match rate recorded in s/w
(f) EMC voltage requirement does not match actual rate

Current resume code properly update s/w state to cover (a), (b), (c),
(d), but missed (e) and (f). Also in (d) case when old parent refcount
reaches zero PLL was left enabled.

This commit updated resume procedure to cover discrepancies (e), (f),
and to disable old EMC parent if it does not have any other children.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: I44a785dfab9f2ace929466c35763db011cacf594
Reviewed-on: http://git-master/r/289541
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: clock: Preserve parent state on rate limit changes
Alex Frid [Tue, 1 Oct 2013 01:20:25 +0000]
ARM: tegra: clock: Preserve parent state on rate limit changes

Added BUS_RATE_LIMIT flag to identify shared bus users that specify
bus rate limits. Don't propagate enable/disable state to the parent
bus when such users are enabled/disabled.

Change-Id: I6cae2dbe73f32fede8759db080eb97b9345acbd5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289517
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: ardbeg: clear fb if bl fb not defined.
Jong Kim [Thu, 10 Oct 2013 20:16:43 +0000]
ARM: tegra: ardbeg: clear fb if bl fb not defined.

Clear primary framebuffer if bootloader framebuffer is not defined.
(Some bootloader such as u-boot may not support LCD display and not
supporting LCD in bootloader is purely customer's choice and the
kernel display driver should survive such configuration).

bug 1301464
bug 1264520

Signed-off-by: Jong Kim <jongk@nvidia.com>

Change-Id: Ib78d926ab7903a283be8b73e2785c7a78639507d
Reviewed-on: http://git-master/r/289280
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Jong Kim <jongk@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoARM: tegra12: clock: Separate EMC DVFS voltage steps
Alex Frid [Sun, 29 Sep 2013 06:22:39 +0000]
ARM: tegra12: clock: Separate EMC DVFS voltage steps

Separated EMC DVFS voltage steps from all other VDD_CORE clock
domains, since EMC steps are, in fact, different, and can very for
different board and DDR manufacturer combinations.

Change-Id: I6f01e664ba70dbd105124e31dee8c805d3823217
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289510
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: Set GPU scaling trip-points
Alex Frid [Sat, 28 Sep 2013 04:27:55 +0000]
ARM: tegra12: Set GPU scaling trip-points

Set GPU scaling trip-points in SOC-THERM or NCT thermal zones on
Tegra12 platforms (zone selection depends on thermal fuses settings).
As a result GPU scaling cooling device is binded with the respective
thermal zone, and enables GPU thermal DVFS.

Bug 1273253

Change-Id: I51fca20fd49d6dd42cff1219653ac5a7d541827f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289547
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra12: dvfs: Add GPU thermal CVB and DVFS tables
Alex Frid [Sat, 21 Sep 2013 07:06:40 +0000]
ARM: tegra12: dvfs: Add GPU thermal CVB and DVFS tables

Added temperature dependent terms to GPU continues virtual binning
(CVB) equation for calculating minimum voltage required to operate
at the particular frequency. Expanded CVB parameters data structure
with the respective coefficients. Populated expanded CVB tables based
on initial GPU characterization data.

Constructed thermal DVFS tables in the following temperature ranges
- below 10C: voltage for each frequency is maximum of CVB equation
outputs at -10C, and 10C
- below 30C: voltage for each frequency is maximum of CVB equation
outputs at 10C, and 30C
- between 30C and 50C: voltage for each frequency is maximum of CVB
equation outputs at 30C, and 50C
- between 50C and 70C: voltage for each frequency is maximum of CVB
equation outputs at 50C, and 70C
- above 70C: voltage for each frequency is CVB equation output at 70C

Added cooling device for voltage temperature scaling on GPU rail
(not binded to any thermal zone, yet).

Bug 1273253

Change-Id: Iec297347732d7db212e3994143bddae5b8f3fd6a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/289546
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra: reserve contiguous mem using CMA
Vandana Salve [Thu, 19 Sep 2013 12:34:48 +0000]
arm: tegra: reserve contiguous mem using CMA

Reserve contiguous memory using dma_declare_contiguous
for generic and VPR carveout.

Change-Id: If3dbc3ecb1e664ed21f4c804f5c7d7f536ca8bc1
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289420
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

5 years agoarm: tegra: dalmore: increase carveout size
Krishna Reddy [Fri, 11 Oct 2013 00:19:18 +0000]
arm: tegra: dalmore: increase carveout size

increase carveout size to 512MB. This is necessary
for SMMU disable case.

Change-Id: Ia0deccbba47be27a5159b999f3f902330974f5dc
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289422
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agovideo: tegra: add config NVMAP_USE_CMA_FOR_CARVEOUT
Krishna Reddy [Thu, 10 Oct 2013 23:03:53 +0000]
video: tegra: add config NVMAP_USE_CMA_FOR_CARVEOUT

Add config option to use CMA reserved memory for carveouts.
CMA would allow reserved memory to be used by applications
when it is not in use by the device that reserved it.
Bug 1279160

Change-Id: I5bcf11a962f1de1fd5bb7db244ae90923de5873d
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/289416
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

5 years agoARM: tegra: mcerr: Update message printing
Alex Waterman [Mon, 7 Oct 2013 22:00:54 +0000]
ARM: tegra: mcerr: Update message printing

Upgdate and upgrade the messages that get printed by mcerr.
Now both the swgid and the actual specific client are printed
when an error is detected.

Change-Id: Id4b27ace8dad5823ecbc7b5d8fd5eb64d212b709
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/288593
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: mcerr: Update client arrays
Alex Waterman [Mon, 7 Oct 2013 20:44:21 +0000]
ARM: tegra: mcerr: Update client arrays

Use a script to generate the client arrays. Also modifies the
usge of the name field in the client and adds a swgid field.
Before 'name' was really the swgid, but now name holds to true
client name instead of the swgid. This allow for more detail
in the error messages printed by mcerr.

Change-Id: I2a7a912524a1d06b121d9567d32d29bc0b5a1282
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/288592
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoarm: tegra12: ardbeg: Support E1792 with E1735
Kamal Kannan Balagopalan [Tue, 1 Oct 2013 23:40:22 +0000]
arm: tegra12: ardbeg: Support E1792 with E1735

Fix DDR rail voltage set higher than required for LPDDR3

Bug 1350759

Change-Id: I168b1371d870489acfac0e35ac314a9559080848
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/289905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agovideo: tegra: host: Handle FECS interrupt
Terje Bergstrom [Mon, 7 Oct 2013 08:06:48 +0000]
video: tegra: host: Handle FECS interrupt

Read FECS interrupt and clear it.

Change-Id: I1ee5b5bd470084fea86db8c7023818e0ff5c7666
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/288785
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: Remove alloc & bind
Terje Bergstrom [Thu, 10 Oct 2013 12:03:33 +0000]
video: tegra: host: Remove alloc & bind

If we're allocating GPFIFO before we have an address space, we
allocate one. Don't do that anymore as it can be used for panicking
the kernel.

Bug 1374242

Change-Id: Ie6ddc0197272f596e9875dc019f4689443f24801
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/289172

5 years agovideo: tegra: host: gk20a: Add locking to l2 ops
Arto Merilainen [Wed, 9 Oct 2013 10:07:31 +0000]
video: tegra: host: gk20a: Add locking to l2 ops

L2 operations were totally unlocked. This patchs adds a lock to
prevent concurrent access to L2 flushes/invalidates.

Bug 1385054

Change-Id: I98e76dcdb9e8202c5ded0b06d86d7985951f2e5f
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/289043
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>