5 years agoARM: tegra11x: Define ncpu residency for 2 clusters
Bo Yan [Tue, 5 Feb 2013 17:57:10 +0000]
ARM: tegra11x: Define ncpu residency for 2 clusters

There is no compelling reason to define minimum residency of non CPU
power gating for each different platform. Non CPU power gating has
far less dependency on platform in terms of latency when compared
against rail gating. So move this parameter to CPU specific idle
driver code.

Define minimum residency of non CPU power gating for both slow and
fast cluster. The entry criteria is different for two clusters, so
different value are required.

Change-Id: I3f734d056f6de6a804ca4c14e037a98bc07c646d
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/197537
Reviewed-on: http://git-master/r/200856
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11x: Fix wake-up time adjustment
Bo Yan [Mon, 4 Feb 2013 19:09:57 +0000]
ARM: tegra11x: Fix wake-up time adjustment

The wake up time adjustment for per-core CPU power down entry has
a few issues: the logic of checking masking bit is wrong and
unnecessary, the timer function for getting context is not used
elsewhere and seems redundant, the calculating statement itself
is confusing.

This patch aims to fix issues above.

Change-Id: Id717f50005e0c32db80af786d9b1fbbe628c196a
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/197065
(cherry picked from commit 544629015e3a2924ea094e9809131dd0be30954d)
Reviewed-on: http://git-master/r/200855
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

5 years agoARM: mm: Skip I-cache invalidate for Cortex-A15 boot
Bo Yan [Thu, 31 Jan 2013 18:41:44 +0000]
ARM: mm: Skip I-cache invalidate for Cortex-A15 boot

This is not required since cache is invalidated by HW in the reset
sequence. Bootloader is supposed to do the same before it hands
over control to kernel.

Change-Id: I0991de3ba1015a32f2c49a0333fd0b17a51a4f31
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/197028
(cherry picked from commit 9c49ffd08d6da03caa820711db83f561d9333aee)
Reviewed-on: http://git-master/r/200854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra11x: Remove redundant cpu_number calls
Bo Yan [Thu, 7 Feb 2013 00:30:50 +0000]
ARM: tegra11x: Remove redundant cpu_number calls

The "cpu_number" maps cpu number for slow cluster to "4", this can
be reused later, no need to call "cpu_number" every time.

Change-Id: Ib0636b80b587868e23a6b07a5cc9960e13d38353
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/198580
(cherry picked from commit 79faef4783ff207f38d76c283704e3b70ea31f18)
Reviewed-on: http://git-master/r/200853
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoARM: tegra: add "memory" to clobber list
Peter De Schrijver [Thu, 14 Feb 2013 10:41:59 +0000]
ARM: tegra: add "memory" to clobber list

The inline asm needs "memory" in its clobber list to prevent gcc from caching
the mcr read too agressively.

Bug 1207116

Change-Id: Ia93e8115b9bd8bf0539e7b7d55ffeda2efc0e7e6
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/200751
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: tegra: cpuquiet: make userspace governor actions synchronous
Peter De Schrijver [Tue, 12 Feb 2013 15:51:26 +0000]
ARM: tegra: cpuquiet: make userspace governor actions synchronous

Userspace expects changes to happen synchronously. Implement this by waiting
with a (configureable) timeout for the action to happen.

Bug 1220065

Change-Id: I81301719707e4baf2b3aea62c38fc771ffe1205d
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/200013
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: cpuquiet: Honor G->LP delay on last core down
Peter Boonstoppel [Thu, 31 Jan 2013 21:22:02 +0000]
ARM: tegra: cpuquiet: Honor G->LP delay on last core down

We cluster switch G->LP when 2 conditions are met:
1) we are in single core mode
2) CPU freq reaches idle_bottom_freq

After these 2 conditions are met, we wait for down_delay ms before
cluster switching. This patch ensures the timeout is also honored when
the first condition is met last.

Bug 1226607

Change-Id: Ic36f9cab09a5967b71409e44dbe89290f39cb26b
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/196171
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: tegra: roth: add gpio init for joystick
Karthik Gunda [Wed, 26 Dec 2012 12:39:19 +0000]
arm: tegra: roth: add gpio init for joystick

added gpio init for reset, clock and data pins of
joystick controller. Put them in output mode and
set reset pin to low to deassert.
set clock and data to low.

Bug 1208859

Change-Id: I3bfe919563215fe85c1ad2ae39827e50bbe09297
Signed-off-by: Karthik Gunda <kgunda@nvidia.com>
Reviewed-on: http://git-master/r/174287
(cherry picked from commit c906352621f12335d1eb067c26a5f5890ebd03ca)
Reviewed-on: http://git-master/r/194582
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra30: Remove dead code for LP2
Bo Yan [Thu, 7 Feb 2013 00:13:30 +0000]
ARM: tegra30: Remove dead code for LP2

The LP2 on T30 A01 is broken. Since T30 A01 is not productized,
remove relevant code which is effectively dead and not being
used, so that the coverage tool will stop complaining them as
being untested.

bug 1227750

Change-Id: Ic5c99ec2d401880a2ead3a7cfd9822bdb54e6f94
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/198179
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agovideo: tegra: dc: Bail out on incorrect window attributes
Raghavendra VK [Fri, 18 Jan 2013 19:16:11 +0000]
video: tegra: dc: Bail out on incorrect window attributes

bug 1066942

Change-Id: I139b6a340ba570ff020cc41ec6ad219c578e14f9
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/192455
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoarm: tegra: config: Removing uart console entry
Darbha Sriharsha [Tue, 5 Feb 2013 05:59:05 +0000]
arm: tegra: config: Removing uart console entry

This change is intended to disable the
"CONFIG_TEGRA_DEBUG_UART" entry in the
tegra11_defconfig config file as this
was enabled for debugging purposes on
pismo and is no longer necessary, also
because it causes a conflict and boot
hang when the ODM data specifies different
uart debug console options

Bug 1218535

Change-Id: I9b8b278d88eb299e4fd9d3edd073349704eb7150
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/197318
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agohwmon: ina230: use correct configuration modes
Deepak Nibade [Wed, 6 Feb 2013 15:47:24 +0000]
hwmon: ina230: use correct configuration modes

Bug 1228591

Change-Id: I5a4b2b59d32118d57ee0ff6c21b8423268fc1926
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/197993
(cherry picked from commit 2b1e73a6f01c1bf14d4e9c7c493a83ae97b593f3)
Reviewed-on: http://git-master/r/199985
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

5 years agovideo: tegra: nvavp: use dev_pm_ops
Mayuresh Kulkarni [Tue, 12 Feb 2013 09:25:16 +0000]
video: tegra: nvavp: use dev_pm_ops

- this commit replaces the legacy suspend/resume calls
with the dev_pm_ops call-backs
- dev_pm_ops has many other call-backs related to
runtime pm and pm domains along with system
suspend/resume call-backs

Change-Id: I24d691672b3d9804a42561d8f7b78b99646a2f42
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/199937
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: Add barriers after cache operations
Amit Kamath [Tue, 29 Jan 2013 10:09:58 +0000]
ARM: tegra: Add barriers after cache operations

memory and instruction barriers are needed after the tlb is
invalidated and BTAC is flushed as per ARM TRM. Without this
there is a invalid page translation in some cases.

Bug 1189280

Reviewed-on: http://git-master/r/195070
(cherry picked from commit 997c54686349728cdf54cfeae96b5f4078ccb436)

Change-Id: I85e297ffd9245c5066f656bbb70ea257b8b3b317
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/199867
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Sarvesh Satavalekar <ssatavalekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agomedia: video: tegra: add stub runtime PM for camera
Prashant Gaikwad [Mon, 11 Feb 2013 11:20:15 +0000]
media: video: tegra: add stub runtime PM for camera

Add stub runtime PM implementation for Tegra camera. This will
help to notify the events to MC clock power domain.

Bug 1010971
Bug 887355

Change-Id: I72b1120ade18f0511bd2f9513fdf1565dd3c6277
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/199407
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agodriver: nor: tegra: Correct Module detection logic
Ashutosh Patel [Mon, 11 Feb 2013 10:40:42 +0000]
driver: nor: tegra: Correct Module detection logic

- Removed return EIO statement to detect half flash
if single NOR flash module is connected

bug 1234582

Change-Id: I4d7d2a9b871566cd23509eaaa5140fb093a164c1
Signed-off-by: Ashutosh Patel <ashutoshp@nvidia.com>
Reviewed-on: http://git-master/r/199384
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoARM: tegra11: clock: Add graphics bus capping interface
Alex Frid [Sat, 2 Feb 2013 07:59:04 +0000]
ARM: tegra11: clock: Add graphics bus capping interface

Added sysfs nodes to limit Tegra11 graphics bus rate:

/sys/kernel/tegra_cap/cbus_cap_level
/sys/kernel/tegra_cap/cbus_cap_state

Bug 1186037

Change-Id: I8659f8ac25eea78f8fb7fadda0130fc32c884e02
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196731
(cherry picked from commit 5100dadf197587e9d5afca110811c0121aac20b6)
Reviewed-on: http://git-master/r/199180
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agovideo: tegra: camera: squash changes for pll_d2_clk
Jihoon Bang [Thu, 17 Jan 2013 18:19:29 +0000]
video: tegra: camera: squash changes for pll_d2_clk

Squash following changes. These changes are about
handling pll_d2_clk which is used to test pattern
generator in VI/CSI.

08c492d1d7d13: fix test pattern generator
60817b5005851: enable/disable pll_d2 in balance

Fix build error related for T148.
3beca1de87b49: fix build error

Fix uneven clk_enable/clk_disable.

Bug 1189789
Bug 1168336
Bug 1214620

Reviewed-on: http://git-master/r/192115
(cherry picked from commit b526c6cbed623f86b0c7ddba2796c40ffb489826)

Change-Id: Ie6dd1dcfb5e68e522eb5817369ef49eff59f46af
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/194806
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 years agomedia: video: tegra: camera: move tegra_camera
Jihoon Bang [Thu, 27 Dec 2012 18:31:01 +0000]
media: video: tegra: camera: move tegra_camera

Move tegra_camera from platform_driver to
part of nvhost vi driver. Split tegra_camera.c file into
multiple files incluidng camera.c, camera_power.c,
camera_emc.c and camera_clk.c according to functionality.

tegra_camera is registered/unregistered in nvhost vi driver.

Bug 1189789

Reviewed-on: http://git-master/r/174508
(cherry picked from commit e503a08b809844b53b7737e504e9f376f4a8a1eb)

Change-Id: Ia8e189e809e18e16b780d3ff064bc96db84ade85
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/194805
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agocpuquiet: Remove synchronization from runnables_work_func()
Peter Boonstoppel [Thu, 24 Jan 2013 19:04:02 +0000]
cpuquiet: Remove synchronization from runnables_work_func()

runnables_stop() can deadlock when cancel_work_sync() waits for the
work function to end and the work function blocks on the same lock
held by runnables_stop().

Removing the locks from runnables_work_func() fixes this. This should
be safe because runnables_lock protects runnables_state and
runnables_work_func() only reads runnables_state. Also, the functions
that change state to DISABLED do a cancel_work_sync() to guarantee the
work function stopped running.

Bug 1215668

Change-Id: I70617b3b0fc81db8555869e67e3b11652af8d94c
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/193881
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

5 years agoARM: tegra30: Remove extra check for ARM version
Bo Yan [Wed, 6 Feb 2013 22:44:54 +0000]
ARM: tegra30: Remove extra check for ARM version

cpuidle-t3.c is only used for tegra30, there is no need to check
ARM version here since it's guaranteed to be Cortex A9.

bug 1230268

Change-Id: Iafc24e957bf4d0cfee2c22fe6eec7617d7a3eb7a
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/198141
Reviewed-by: Automatic_Commit_Validation_User

5 years agoarm:tegra:pluto: Enable pull-up for MDM1 UART RX
Alexandre Berdery [Tue, 5 Feb 2013 10:18:05 +0000]
arm:tegra:pluto: Enable pull-up for MDM1 UART RX

Bug 1180005

Change-Id: Icb3a45b8c6ce68168b4b2e890493fc1456044cf4
Signed-off-by: Alexandre Berdery <aberdery@nvidia.com>
Reviewed-on: http://git-master/r/197418
(cherry picked from commit 50d23244aaa4df6a2dee83cc7f9457d9f4aeb164)
Reviewed-on: http://git-master/r/199448
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

5 years agodrivers: mfd: palmas: make smps10_boost_disable optional
Matt Wagner [Tue, 11 Dec 2012 05:43:47 +0000]
drivers: mfd: palmas: make smps10_boost_disable optional

Allow the board to pick whether they want to disable
smps10_boost on suspend

Bug 1172908

Change-Id: I0121f7e24716eb8731af3b14100d81ef63168929
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/170340
(cherry picked from commit 4c6a241b1433362447782e047f7b78226362ea47)

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I56a0e8fec03fa47547052a965aa123f88517ca70
Reviewed-on: http://git-master/r/196901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agoarm: tegra: soctherm: changes to support throttling on GPU zone
Diwakar Tundlam [Fri, 1 Feb 2013 22:21:12 +0000]
arm: tegra: soctherm: changes to support throttling on GPU zone

Old code was resuming only CPU zone initiates throttling. Fixed INTR
handling, threshold setting, etc.

Added support to bind cooling devices to GPU (or PLL, MEM) zone.
Added support to set hotspot offsets for cpu, gpu, mem zones.

Cleaned up some unnecessary code.

Bug 1169070
Bug 1200077

Change-Id: If584d1acee301d97ff169b65e8451e9ebd8c4ffe
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/196657
Reviewed-by: Automatic_Commit_Validation_User
(cherry picked from commit 1db44611dc6fcf254e13a092ce7c9fc86b7276c4)
Reviewed-on: http://git-master/r/199756

5 years agoARM: tegra: clock: Moved common bus capping code
Alex Frid [Sat, 2 Feb 2013 06:31:50 +0000]
ARM: tegra: clock: Moved common bus capping code

Moved common shared bus capping code into a separate file (currently
bus capping is supported on Tegra3 only).

Bug 1186037

Change-Id: Ie35c74cf9b4db65beacb9408942efb632c845193
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196730
(cherry picked from commit 3d3f186204691a731f693c05924a5b80798773d1)
Reviewed-on: http://git-master/r/199178
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agosecurity: tf_driver: fix incorrect cpu affinity in tf_driver
Hyung Taek Ryoo [Thu, 31 Jan 2013 04:50:03 +0000]
security: tf_driver: fix incorrect cpu affinity in tf_driver

This change fixes incorrect cpu affinity after excuting tf_driver.
The process using tf_driver sometimes can't be schecduled to
available onlined cpu. It is because cpu affinity has changed
after using tf_driver. tf_driver saves current cpu affinity by
calling sched_getaffinity which returns cpu affinity AND-masked
by onlined cpus. tf_driver should save just current cpu affinity,
not cpu affinity AND-masked by onlined cpus.

bug 1218943

cherry picked from commit bba209aa7fe8b4f52f5d42acc1b21d8f54c18fe0)
Reviewed-on: http://git-master/r/#change,195830

Change-Id: I4f39b9768f95dd773582fbff6bb4577c3debd9b3
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/198844
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

5 years agoarm: tegra11: config: Enable CONFIG_USE_OF for L4T
Matt Pedro [Thu, 24 Jan 2013 17:08:20 +0000]
arm: tegra11: config: Enable CONFIG_USE_OF for L4T

Enable CONFIG_USE_OF for tegra11 L4T config.

bug 1029338

Change-Id: I584b60c75c6cb030f6e8632ce82cdc3e956808d3
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/193850
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: dvfs: Apply constraints to nominal voltage
Alex Frid [Sun, 3 Feb 2013 07:20:19 +0000]
ARM: tegra11: dvfs: Apply constraints to nominal voltage

Applied rail constraints (offset/min/max) to nominal voltage when rail
is disabled or suspended. Effectively the only real change introduced
by this commit is application of debugfs offset, since nominal voltage
is always set within min/max rail limits.

Change-Id: If2bb13166353bc674b2e19141ad2af5428ed74d4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196777
(cherry picked from commit 5a3eba360cd7713c6edae4ffe73123c93486f30e)
Reviewed-on: http://git-master/r/199176
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dvfs: Update voltage recording in dfll mode
Alex Frid [Sun, 3 Feb 2013 06:17:19 +0000]
ARM: tegra: dvfs: Update voltage recording in dfll mode

In dfll mode rail voltage is adjusted automatically, but not exactly
to the expected level. When/if control is switched back from dfll h/w
cl-dvfs to s/w dvfs, false detection of matching voltage between new
target, and old dfll record is possible. To avoid this false detection
1mV was subtracted every time dfll voltage was recorded. After this
commit record is distorted by 1mV only once before the switch.

Change-Id: If3045293bda8c0240e2ce7fb3f1176288c9d150f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196776
(cherry picked from commit b91a719567a57e96a628f9bb6dd5708070bf5b2a)
Reviewed-on: http://git-master/r/199175
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dvfs: Add rail NULL-pointer check
Alex Frid [Sun, 3 Feb 2013 05:51:27 +0000]
ARM: tegra: dvfs: Add rail NULL-pointer check

Add rail NULL-pointer check in public interfaces.

Change-Id: If4174471d6d9ce6935316db72ec5bf273cb2b486
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196775
(cherry picked from commit 1b7d7b6c39d45a84135d66c7cf784dc4bbee788e)
Reviewed-on: http://git-master/r/199174
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: dvfs: Increase number of rail stats bins
Alex Frid [Sun, 3 Feb 2013 05:40:37 +0000]
ARM: tegra: dvfs: Increase number of rail stats bins

Change-Id: I0a043ff1f4a2fc665c41f75ac8e91107bdbf1c83
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196774
(cherry picked from commit d5a4477a003f01985aeb14e7e4902aaa37e0f482)
Reviewed-on: http://git-master/r/199173
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra14: clock: Force out-of-table shared bus max limit
Alex Frid [Sun, 10 Feb 2013 04:16:53 +0000]
ARM: tegra14: clock: Force out-of-table shared bus max limit

Ported from Tegra11 commit c6ea56f11d575a02b4ec2e08152043ac8fc5bf35

Change-Id: I6d6dbbcc5824d360f5fafd54453137697d563f65
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/199170
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra14: clock: Update CPU clock control operations
Alex Frid [Sun, 10 Feb 2013 03:06:44 +0000]
ARM: tegra14: clock: Update CPU clock control operations

Ported from Tegra11 commits:

bf0d93b965c91143a4140f5a43b5fbd8acc6a305
bb6bd2c6c5be76ebd3340003a17ac5675c18ef5a
b0689c8dec259847087362922d2cf3249fd85c83
fea89035708cc9f21f995194cb1586672e9c0e05

Change-Id: I756935793cf58aaf141b74a1cad2b14ec1ca586a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/199168
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra11: power: Set safe cold voltage in DFLL mode
Alex Frid [Thu, 31 Jan 2013 22:52:01 +0000]
ARM: tegra11: power: Set safe cold voltage in DFLL mode

Used regulator API to set CPU voltage at cold temperature minimum
limit if DFLL is selected as fast G CPU clock source, and

- CPU is switching to LP cluster
- on entry to system suspend

This is done since in both cases: suspend and LP cluster operations,
CPU rail is off while temperature may go down, and on exit from each
state CPU will be running on DFLL clock for some time before CL-DVFS
regulation starts.

Change-Id: I02e06a2e92f348a147693ad2b811d7bedb4e70e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196289
(cherry picked from commit fea89035708cc9f21f995194cb1586672e9c0e05)
Reviewed-on: http://git-master/r/199167
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: dvfs: Don't force CL-DVFS request entering open loop
Alex Frid [Thu, 31 Jan 2013 20:20:26 +0000]
ARM: tegra11: dvfs: Don't force CL-DVFS request entering open loop

Don't force CL-DVFS request when entering open loop (in order to
avoid unnecessary extra transaction).

Change-Id: I25955920d4d1a9d5d96007c09694a923c000e148
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196288
(cherry picked from commit d049c47291b9a94f2b72fc64a40559cc37c0498a)
Reviewed-on: http://git-master/r/199166
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra11: power: Keep CPU power On when DFLL mode changing
Alex Frid [Wed, 30 Jan 2013 08:09:47 +0000]
ARM: tegra11: power: Keep CPU power On when DFLL mode changing

Don't power down fast CPU cluster when DFLL mode is changing
- during CPU clock source switch between PLL and DFLL
- during CPU cluster switch

Change-Id: I987383a39ce23a19f837eba441c59f9e6513d069
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/195789
(cherry picked from commit b0689c8dec259847087362922d2cf3249fd85c83)
Reviewed-on: http://git-master/r/199165
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra11: clock: Add direct access to CPU DFLL
Alex Frid [Wed, 30 Jan 2013 01:04:19 +0000]
ARM: tegra11: clock: Add direct access to CPU DFLL

Added CPU DFLL access API for CPU idle driver to directly manipulate
DFLL rate underneath cpufreq governor, provided CPU rail is under DFLL
control.

Change-Id: I108cbffe530e8620513fb11e89707b003cb34b9d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/195399
(cherry picked from commit 70ba214be307f805944ba3e3386201689ddec287)
Reviewed-on: http://git-master/r/199164
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: soctherm: Fix setting hi-thresh for passive trips
Diwakar Tundlam [Tue, 5 Feb 2013 02:28:59 +0000]
arm: tegra: soctherm: Fix setting hi-thresh for passive trips

Set the hardware high-threshold = passive trip point instead of 128C.
There's only one passive trip point that software thermal governor
monitors (and polls if the temperature is higher).

This avoids certain thermal runaway cases, esp. with small passive
delays and large hysteresis because the high threshold = passive trip
point raises an interrupt if the temperature goes above it.

Bug 1200077

Change-Id: I4638a85065e4662ba44d291d6eb2ce13f39d5d52
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/197348
(cherry picked from commit 9fcb5e5b1962d2104409c8f5ba7c4911bde28ad2)
Reviewed-on: http://git-master/r/198960
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: soctherm: PMC scratch register config for thermtrip
Diwakar Tundlam [Thu, 20 Dec 2012 20:56:10 +0000]
arm: tegra: soctherm: PMC scratch register config for thermtrip

Initalize PMC scratch registers with regulator PMIC I2C bus and address.
Setup parameters to do shutdown on THERMTRIP from soc_therm.

Added support for Dalmore and Pluto and placeholders for ceres and pismo.

Bug 1200075

Change-Id: Ie9165febd88bd552c533e38c9cd073d8fe4f562d
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/173218
(cherry picked from commit e7b1053fac4275c1d4dd8ee7202366f7de1bb69c)
Reviewed-on: http://git-master/r/198959
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoThermal: pid_thermal_gov: Add compensation
Jinyoung Park [Thu, 17 Jan 2013 17:19:11 +0000]
Thermal: pid_thermal_gov: Add compensation

Added compensation to get steady state transition.
And added sysfs node for compensation rate.

Bug 1200111

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/193836
(cherry picked from commit 4d2d134e71efce2cd652ccb0eac4946c0e3743f2)

Change-Id: I406a9fa60c705f01d5c7a2194eecdf9babe09634
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/198875
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agomisc: nct1008: Add thermal_zone_params in struct nct1008_platform_data
Jinyoung Park [Thu, 31 Jan 2013 13:15:44 +0000]
misc: nct1008: Add thermal_zone_params in struct nct1008_platform_data

Added thermal_zone_params in struct nct1008_platform_data in order to
pass governor and binding params to nct1008 thermal zone device.

Bug 1200111

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/196028
(cherry picked from commit 7de865bccc8da80cf950346edab75a3e7221a45e)

Change-Id: I825d7380f6f29a1dd8d4a9333ed873255b2deb67
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/198873
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: soctherm: Add thermal_zone_params in struct soctherm_therm
Jinyoung Park [Thu, 31 Jan 2013 13:10:36 +0000]
arm: tegra: soctherm: Add thermal_zone_params in struct soctherm_therm

Added thermal_zone_params in struct soctherm_therm in orther to set
governor and binding params to soctherm thermal zone devices.

Bug 1200111

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/196027
(cherry picked from commit 91ede6523270d5ad808c39133067686ea6ec74f0)

Change-Id: I44a5ef9a29e9a773f2ce26b6e5c72213e982272b
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/198872
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoThermal: Fix binding problem when there is thermal zone params
Jinyoung Park [Thu, 31 Jan 2013 12:32:21 +0000]
Thermal: Fix binding problem when there is thermal zone params

The thermal zone params can be used to set governor to specific thermal
governor for thermal zone device. But if the thermal zone params has only
governor name without thermal bind params, then the thermal zone device
will not be binding to cooling device. Because tz->ops->bind operator is not
invoked in bind_tz() and bind_cdev() when there is thermal zone params.

Bug 1200111

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/196026
(cherry picked from commit 602c6b3827650f3aee04554ba1a31663fe9e89b0)

Change-Id: I50643f6e6474a143981fc177291d5ac6cfa85c97
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/198871
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoARM: config: tegra11: enable THERMAL_GOV_PID config
Jinyoung Park [Thu, 20 Dec 2012 13:44:04 +0000]
ARM: config: tegra11: enable THERMAL_GOV_PID config

Enable PID thermal governor.

Bug 1200111

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/188327
(cherry picked from commit 5cbc8969a43b3aa08f1938e0f1d341bd9a358460)

Change-Id: I1f4df9e2341f08a22bd5e350a702fca96df55eba
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/198870
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoARM: tegra: restrict battery EDP manager to pluto
Sivaram Nair [Fri, 8 Feb 2013 11:00:13 +0000]
ARM: tegra: restrict battery EDP manager to pluto

Battery EDP manager is needed only in pluto at the moment. Removing it
from elsewhere.

Change-Id: Ic758f2b26cac37b7ed6a99844b5b583d4655219c
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/198751
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agogpio: tegra: enable bank irq for wakeup based on wake depth
Laxman Dewangan [Fri, 8 Feb 2013 15:15:06 +0000]
gpio: tegra: enable bank irq for wakeup based on wake depth

Eanble/disable the bank irq wakes based on wake-depth which
directly related to the number of gpios on that bank are
wake enabled/disabled.

bug 1230573

Change-Id: I94fc8cb8dac890bdd3a07e82ad9d5a58004d6b82
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198804
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoArm: tegra: pmc: fix regression issues
Krishna Yarlagadda [Thu, 7 Feb 2013 14:45:52 +0000]
Arm: tegra: pmc: fix regression issues

Fixed regression created by pmc separation by
adding recent pending changes

Bug 1232698

Change-Id: I5f6e9b87d7252941ea8ddbb115f4197318369a18
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/198423
Tested-by: Stephane Dion <sdion@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

5 years agoasoc: AIC3262: Fix headset detection failure during bootup
Vijay Mali [Tue, 5 Feb 2013 12:56:35 +0000]
asoc: AIC3262: Fix headset detection failure during bootup

Remove codec driver call for headset detection.
On Pluto headset detection is done using AP GPIO pin.
Remove unused code.

For bug 1228726

Change-Id: I4be5a0c89375749919eb3222293564318bde9547
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/197463
(cherry picked from commit aa96d4bcf679d80963ba11c3a73d5918bfc95943)
Reviewed-on: http://git-master/r/198778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

5 years agovideo: tegra: dc: Power on host1x for CSC, frame end interrupt
Raghavendra VK [Thu, 7 Feb 2013 23:40:16 +0000]
video: tegra: dc: Power on host1x for CSC, frame end interrupt

bug 1233236

Change-Id: I47ffa44e292c65e89914b58d88c52ffdcb35fdbc
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/198567
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: config: tegra11: enable CMA
Hiroshi Doyu [Thu, 7 Feb 2013 19:40:26 +0000]
arm: config: tegra11: enable CMA

Enable contiguous memory allocator (CMA).

bug 1215481

Change-Id: I859aca7167588beb7227667a755d2a83b6459fef
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/198461
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Atte Peltomaki <apeltomaki@nvidia.com>

5 years agoARM: tegra: power-edp table
Diwakar Tundlam [Tue, 22 Jan 2013 20:48:25 +0000]
ARM: tegra: power-edp table

Added code for populating cpu power edp table during init. This is
needed for the AP+DRAM super system EDP client.

Bug 1159974

Change-Id: If1f5c3e53416a1edb1df42ff1cb356e0b1d507c6
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/198023

5 years agoARM: tegra11: add frequency cap clocks
Sivaram Nair [Fri, 1 Feb 2013 09:39:10 +0000]
ARM: tegra11: add frequency cap clocks

Frequency cap clocks for EMC and CBUS are added for AP+DRAM EDP
super-client support.

Bug 1159974

Change-Id: I72d3c716c5c916e3ecca47b5124cddae3a7bf719
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/196387
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agoarm: tegra: Preserve TZRAM GIZMO value during suspend
Bhavesh Parekh [Mon, 7 Jan 2013 07:32:23 +0000]
arm: tegra: Preserve TZRAM GIZMO value during suspend

Add TZRAM GIZMO to the list, so that it value will be preserve during
suspend/resume cycle

bug 1053727

Signed-off-by: Bhavesh Parekh <bparekh@nvidia.com>
Change-Id: I3c2f18fcc4e7ba8224974c7ca98aeb646b92dd91
Reviewed-on: http://git-master/r/189082
(cherry picked from commit d58893e6ac9c0146f627a42e347763fc7685180c)
Reviewed-on: http://git-master/r/196925
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

5 years agodrivers: misc: bcm4329: support expander GPIOs
Haribabu Narayanan [Wed, 24 Oct 2012 22:11:36 +0000]
drivers: misc: bcm4329: support expander GPIOs

The current driver makes call to gpio_get_value() which is only
applicable if the GPIOs are accessible without sleeping.  If
used on expander GPIOs, stack trace is dumped at each access.
To additionally support expander GPIOs accesses that can sleep,
shift to gpio_get_value_cansleep().

Bug 1027964

Change-Id: I3609b9dc0020cf82cadc21797b69c023d21e080b
Signed-off-by: Haribabu Narayanan <hnarayanan@nvidia.com>
(cherry picked from commit 7d435abd95715faf1ff2c9164ff496092dd502cf)
Reviewed-on: http://git-master/r/147319
Signed-off-by: Haribabu Narayanan <hnarayanan@nvidia.com>
Reviewed-on: http://git-master/r/198253
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoARM: tegra: secure os: Add secure os carveout
Hyung Taek Ryoo [Wed, 30 Jan 2013 03:40:41 +0000]
ARM: tegra: secure os: Add secure os carveout

BSEV in OTF driver needs to access secure OS carveout,
then it needs to be setup with 1 to 1 mapping explicitly.
This change sets this secure os carveout with 1 to 1 mapping in SMMU.

Bug : 1204409

Change-Id: I853cb77eb1cb39d17ae0f3e03b5118fc4f048e5e
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/195387
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoEDP: fixing bug with priority definitions
Sivaram Nair [Wed, 6 Feb 2013 16:06:32 +0000]
EDP: fixing bug with priority definitions

The min and max priority constants are defined incorrectly (in the wrong
order). This patch corrects it and updates the affected drivers and
platform data.

Change-Id: Ie58742a85e4db96faf5b379384c59053a9716b64
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/198022
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agosecureos: tegra: Remove duplicated L2 cache flush
Hyung Taek Ryoo [Thu, 10 Jan 2013 23:42:16 +0000]
secureos: tegra: Remove duplicated L2 cache flush

This change removes deplicated L2 cache flush.
Moves SMC(0xFFFFFFE4) a bit later in the PM entry process,
replacing tegra_flush_cache in tegra_sleep_cpu_finish().

Bug 1195365

(cherry picked from commit aded133982f0d54e0be3446b8d15c185aa352aac)
Reviewed-on: http://git-master/r/#change,190431

Change-Id: I876ad1d8322f571d7c8561cea83bbf22915d01d8
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/190451
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: dma-mapping: Trace IOMMU atomic allocation
Hiroshi Doyu [Wed, 6 Feb 2013 04:15:25 +0000]
ARM: dma-mapping: Trace IOMMU atomic allocation

Add dev_dbg() to trance IOMMU atomic allocation,
__iommu_{alloc,free}_atomic().

Usage:
echo -n 'func __iommu_alloc_atomic +p' > /sys/kernel/debug/dynamic_debug/control
echo -n 'func __iommu_free_atomic +p' > /sys/kernel/debug/dynamic_debug/control

Change-Id: Ibe322c2d009652eb6b07fd988ff1fff97268e207
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/197752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: Tegra: Add power domain for MC clock
Prashant Gaikwad [Mon, 4 Feb 2013 10:07:49 +0000]
ARM: Tegra: Add power domain for MC clock

This domain is used to monitor the state of memory clients.
When all clients are runtime suspended this domain will
get turned off. If any client wakes up from runtime suspend
state then this domain will be turned on. When the domains is
off, MC clock can be stopped during cpuidle.

Bug 1010971

Change-Id: I608007a0c70ce9c3c18767b76c1cb489c6c3569b
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/197351
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agovideo: tegra: nvmap: Fix race condition in dupes dec
Krishna Reddy [Fri, 1 Feb 2013 20:29:54 +0000]
video: tegra: nvmap: Fix race condition in dupes dec

- Handle reference could be freed in the slow path. Hence, keep a copy
  of handle ptr.

Bug 1221693

Change-Id: Ia63df654c3f6f8eb2fcabbff13d413cf32251c42
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/196545
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: Call arm_iommu_detach_device() at BUS_NOTIFY_DEL_DEVICE
Hiroshi Doyu [Thu, 24 Jan 2013 12:51:02 +0000]
iommu/tegra: smmu: Call arm_iommu_detach_device() at BUS_NOTIFY_DEL_DEVICE

Call arm_iommu_detach_device() at BUS_NOTIFY_DEL_DEVICE as the conter
part of BUS_NOTIFY_ADD_DEVICE case.

bug 1215481

Change-Id: I3f6acd5ab086dc5c2db51982c35a4f9bed77c703
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/193788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agoARM: tegra: Move sim enet to pre-si config
Jeff Smith [Tue, 21 Aug 2012 15:43:19 +0000]
ARM: tegra: Move sim enet to pre-si config

Change-Id: I7502b72c3d8348d7f76bb3f3ec25613c5e34a6cb
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/162270
Reviewed-by: Automatic_Commit_Validation_User

5 years agogpio: tegra: Move new pre-silicon config
Jeff Smith [Mon, 20 Aug 2012 18:28:35 +0000]
gpio: tegra: Move new pre-silicon config

Change-Id: Ib649e5aac02d9d2e855381c71cc946b52617880d
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161907
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>

5 years agoARM: tegra: Build latency allowance in pre-si build
Jeff Smith [Tue, 6 Nov 2012 08:45:07 +0000]
ARM: tegra: Build latency allowance in pre-si build

Disable at run time on unsupported platforms.

Change-Id: I84a6eb7540f85a40b4b86ac224232fa07dcdb273
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/161706
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoinput: Fix input_dev_set_enabled() prototype
Sami Liedes [Tue, 5 Feb 2013 14:13:36 +0000]
input: Fix input_dev_set_enabled() prototype

The buf parameter to device_attribute->store is const. Change the
parameter type of input_dev_set_enabled() to match that. This also
fixes a GCC warning.

Change-Id: Ie98ebe0f1f76e0a733507f710f8c2775abfb0dda
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/197480
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agocpuquiet: Fix warning about unused variable
Sami Liedes [Tue, 5 Feb 2013 13:22:03 +0000]
cpuquiet: Fix warning about unused variable

drivers/cpuquiet/governors/runnable_threads.c: In function 'runnables_work_func':
drivers/cpuquiet/governors/runnable_threads.c:184:14: warning: unused variable 'state' [-Wunused-variable]

Change-Id: I26c2288876043cf3dd21e1b57317a1f5b2de5a9b
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/197469
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoarm: Fix warning in CORENPDQR code
Sami Liedes [Tue, 5 Feb 2013 12:12:12 +0000]
arm: Fix warning in CORENPDQR code

arch/arm/kernel/corenpdrq.c: In function 'corenpdrq_write':
arch/arm/kernel/corenpdrq.c:83:2: warning: passing argument 3 of 'kstrtoul' from incompatible pointer type [enabled by default]
include/linux/kernel.h:220:32: note: expected 'long unsigned int *' but argument is of type 'uint32_t *'

Change-Id: If5291f9ce02a1bd3d4356e8c6b215ce9acef7d44
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/197454
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Liang Cheng (SW) <licheng@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agomedia: video: nvavp: replace pm_runtime_put_sync with async
Prashant Gaikwad [Fri, 1 Feb 2013 05:26:11 +0000]
media: video: nvavp: replace pm_runtime_put_sync with async

nvavp_serivce is called in interrupt context hence replace
pm_runtime_put_sync with aynchronous version.

Bug 1010971

Change-Id: I1314d4408bed56129929fc2e451f286b2d49a994
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/196273
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Gajanan Bhat <gbhat@nvidia.com>

5 years agosdhci: tegra: Add option to use 3.2V input voltage.
Sumeet Gupta [Wed, 2 Jan 2013 07:19:31 +0000]
sdhci: tegra: Add option to use 3.2V input voltage.

Bug 1187691

Change-Id: I01dbd648e3fa8264b5e8706ccef49ac88b8bb106
Signed-off-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-on: http://git-master/r/187928
(cherry picked from commit a0dbcca0706d94c00ca472e029b94003d2db98ac)
Reviewed-on: http://git-master/r/194583
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agoInput: xpad - add ftrace logging
Vikas Jain [Wed, 30 Jan 2013 10:23:29 +0000]
Input: xpad - add ftrace logging

This will help to profile the xpad responsiveness and
overall latency in the system.

Bug 1226968

Change-Id: I20205a4a89beb4ae0d1c888eaf1e1b874e1a9772
Signed-off-by: Vikas Jain <vjain@nvidia.com>
Reviewed-on: http://git-master/r/195507
(cherry picked from commit 0adf09de7c8f58892cb05483a2f718fe0674fb93)
Reviewed-on: http://git-master/r/196342
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

5 years agovideo: fbmon: correct HDMI refresh rates
Jon Mayo [Sat, 12 Jan 2013 03:29:22 +0000]
video: fbmon: correct HDMI refresh rates

Some of the HDMI 4K modes were marked as 30Hz when they were 24/25Hz.

Change-Id: Id84bc05262f14d37cc9f6246f839eb8a99542d5b
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/196696
Reviewed-by: Automatic_Commit_Validation_User

5 years agovideo: tegra: host: add 3dfs user space control
Ilan Aelion [Tue, 23 Oct 2012 18:43:53 +0000]
video: tegra: host: add 3dfs user space control

Additional sysfs nodes user and freq_request may be used to control
gpu frequency. If user is set to non-zero, the value of freq_request
is used for setting the gpu frequency. freq_request is initialized to
the max gpu frequency.

Bug 1161410

Change-Id: I4065397450fd8774fbe7715145ab481698d41929
Signed-off-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-on: http://git-master/r/165100
Reviewed-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

5 years agodrivers: misc: publish fps, cpu load, thread count
Ilan Aelion [Fri, 26 Oct 2012 16:44:58 +0000]
drivers: misc: publish fps, cpu load, thread count

adapted cpufreq_interactive load estimation and averaging of the
number of runnable threads to a misc device that will write the
current cpu id, load and nr_runnable_threads for each cpu to a sysfs
node. Intended to provide an accurate cpu load reading to user space
scaling controllers. In addition the momentary frame rate is written
to /d/fps.

Bug 1161410
Bug 1164121

Change-Id: I041e230463fa7d4a3c83e4a2ab2ce199f9a5d8ba
Signed-off-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-on: http://git-master/r/165089
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoconfig: tegra3/11: enable ACL for tmpfs
Mursalin Akon [Fri, 1 Feb 2013 18:25:42 +0000]
config: tegra3/11: enable ACL for tmpfs

enable ACL for tmpfs to allow udev to
set extended permission.

Bug 1219372

Change-Id: Icf56cef4fdebc25dfb960694e51f40f8128a0ac8
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/196513
(cherry picked from commit c454a29a8ee73d1a0693035b721ffae1854cf481)
Reviewed-on: http://git-master/r/197521
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

5 years agoarm: tegra: roth: support higher frequency HDMI
Rakesh Iyer [Thu, 24 Jan 2013 23:33:22 +0000]
arm: tegra: roth: support higher frequency HDMI

Support up to 4K HDMI on this board.

Bug 1167856
Bug 1185882

Change-Id: Ia0d784480be4f7f81db993b7cb874f533811def5
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/193963
(cherry picked from commit 4e3f7d4da2625eb71721b8b8e385292a5d9eaaa4)
Reviewed-on: http://git-master/r/197074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agoarm: tegra: pluto: support higher frequency HDMI
Rakesh Iyer [Thu, 24 Jan 2013 23:26:34 +0000]
arm: tegra: pluto: support higher frequency HDMI

Support up to 4K HDMI on this board.

Bug 1167856
Bug 1185882

Change-Id: Idf097e9c2f75293f43c171a5a0b242c3f0c37c66
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/193962
(cherry picked from commit da2f17e0ee48a1f19a6978f423eacb3d9b7083ec)
Reviewed-on: http://git-master/r/197073
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

5 years agodrivers: video: nvmap: remove unnecessary message
Alex Waterman [Thu, 31 Jan 2013 21:45:04 +0000]
drivers: video: nvmap: remove unnecessary message

Change an unnecessary and annoying message in nvmap when a pinned
handle is freed to debug. Nvmap automatically unpins he handle before
freeing it.

bug 1228065

Change-Id: I6214537fd786cd4f5a54ef0d34450a68952ec3fa
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/196158
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

5 years agohwmon: ina219: Fix error case return values
Sami Liedes [Tue, 5 Feb 2013 13:52:06 +0000]
hwmon: ina219: Fix error case return values

In both show_power() and show_current(), an error case can cause the
value of `retval' to be returned without the variable having ever been
initialized.

Fix the error cases to return -EAGAIN.

Change-Id: I929097028ba861267a69e32d963fb225310a0ecd
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/197474
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

5 years agoARM: dma-mapping: coherent_pool_size: 2MB
Hiroshi Doyu [Fri, 1 Feb 2013 13:50:21 +0000]
ARM: dma-mapping: coherent_pool_size: 2MB

ap_icera requires more coherent_pool_size than 1MB.

bug 1215481

Change-Id: I075956b5cec64cc8be08c6288062735d8f498710
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/196481
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoasoc: tegra: SPI interface for TI codec
Scott Peterson [Wed, 23 Jan 2013 23:53:01 +0000]
asoc: tegra: SPI interface for TI codec

Add support for accessing the TI aic3262 codec
using the spi interface

Change-Id: I30c72ac2bec5cd51e472f8f4e0750cd533d354a3

Signed-off-by: Scott Peterson <speterson@nvidia.com>
Change-Id: I0dff26133be6c5f0ec36113a61e2b1b5b57b3339
Reviewed-on: http://git-master/r/194172
Reviewed-on: http://git-master/r/197231
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: Disable smmu_client_disable_hwgrp()
Hiroshi Doyu [Mon, 4 Feb 2013 07:02:54 +0000]
iommu/tegra: smmu: Disable smmu_client_disable_hwgrp()

Disable this until swgroup is implemented correctly.

bug 1215481

Change-Id: Ic6bdd10bf165e713326a4bcde8d0746d41e5cb23
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/196941
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoiommu/tegra: smmu: Fix unnecessary NULLfication
Hiroshi Doyu [Mon, 4 Feb 2013 07:01:50 +0000]
iommu/tegra: smmu: Fix unnecessary NULLfication

The parent pointer will be released. No need to set NULL. Also this
order is wrong, setting NULL after free().

bug 1215481

Change-Id: I7ee292200417c04a0b5541b4bdcef7cdb184e9b0
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/196940
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agotegra: kernel: voice call debug
ScottPeterson [Mon, 10 Dec 2012 16:27:37 +0000]
tegra: kernel: voice call debug

Changed KB_ROW7 gpio to PULL_UP for better headset
detection.

Added vdd_sys_audio regulator for speaker amp

Debugging voice call UL/DL loss during stress testing.

Change-Id: Ib1930ff693306621aef269f0e0ff27aee2ab450f
Signed-off-by: ScottPeterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/171212
(cherry picked from commit 8c53a45e1d82657720211b121d5f1221911d6654)

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I7374a4ce7fb8d720617b6f71314c17d3d70e97f6
Reviewed-on: http://git-master/r/196920
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoarm: tegra: clock: use raw_smp_processor_id() in traces
Sami Liedes [Thu, 31 Jan 2013 17:37:15 +0000]
arm: tegra: clock: use raw_smp_processor_id() in traces

The clock lock tracepoints take a processor id; however the locking
and unlocking are usually done in a preemptible context. Calling
smp_processor_id() in a preemptible context causes a warning with
CONFIG_DEBUG_PREEMPT.

Fix this by changing the calls to raw_smp_processor_id(), which merely
circumvents the warning. This means that the cpu ids in the trace
events are only indicative and should only be used for what they are
worth. However otherwise this is entirely harmless.

Change-Id: I35529b69b52d584b878ad73107076ed94faae9c0
Signed-off-by: Sami Liedes <sliedes@nvidia.com>
Reviewed-on: http://git-master/r/196054
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

5 years agoHACK: ARM: tegra: Disable AHB prefetch for SDMMC
Hiroshi Doyu [Tue, 29 Jan 2013 13:13:00 +0000]
HACK: ARM: tegra: Disable AHB prefetch for SDMMC

SDMMC needs to support IOMMU correctly with dma mapping API. Disable
AHB prefetcher until it's done.

bug 1215880

Change-Id: I36250e961fa8ad2896278aec8ac6d9e9b0132326
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/195122
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agomisc: nct1008: Apply hysteresis to only PASSIVE trip_points
Diwakar Tundlam [Thu, 31 Jan 2013 23:37:44 +0000]
misc: nct1008: Apply hysteresis to only PASSIVE trip_points

Applying hysteresis to ACTIVE trip point messes up EDP limiting.

Bug 1200202

Change-Id: Id723f2c2d094d7e1e72cee208b54afed64175c2a
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/196193
(cherry picked from commit a2806554ca9d260d2c15006f8519a1cf7e645207)
Reviewed-on: http://git-master/r/197100
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: soctherm: Adjust trip_temp for hysteresis
Diwakar Tundlam [Thu, 31 Jan 2013 23:12:58 +0000]
arm: tegra: soctherm: Adjust trip_temp for hysteresis

Apply hysteresis to PASSIVE trip points to avoid deadlock when thermal
governor stops polling but temp is above sensor lower temperature
threshold. Governor deadlock leads to a dangerous unthrottled runaway
rise in temperature.

Bug 1200202
Bug 1200077

Change-Id: Ie00677ff366104844ec65e27349f5e1734b414e8
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/196181
(cherry picked from commit 9d85fbefc7448e951c26480ecc7c2be041fd43ad)
Reviewed-on: http://git-master/r/197099
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: soctherm: mark some variables const as necessary
Diwakar Tundlam [Thu, 31 Jan 2013 08:34:00 +0000]
arm: tegra: soctherm: mark some variables const as necessary

Bug 1200077

Change-Id: Icf44e111230d5ddf861943ec19a8d9e77ed86efe
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/195907
(cherry picked from commit b70c83d0c933419f8e7f09f3139a275702c6b0d3)
Reviewed-on: http://git-master/r/197098
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: soctherm: round down trip temps to sensor precision
Diwakar Tundlam [Thu, 31 Jan 2013 08:12:57 +0000]
arm: tegra: soctherm: round down trip temps to sensor precision

Emit a warning whenever forced rounding down is done during init and
when setting trip_temp via sysfs.

Bug 1200077

Change-Id: I4ded4df19adb4192d51ab3ea6872ae0c052589af
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/195898
(cherry picked from commit 46f3be4f9154c2efda5026ee969f5dfbee369d53)
Reviewed-on: http://git-master/r/197097
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: Move all tj dependent thermals from nct to soc_therm
Diwakar Tundlam [Wed, 30 Jan 2013 00:44:32 +0000]
arm: tegra: Move all tj dependent thermals from nct to soc_therm

Functions moved are vdd_cpu, core edp. Raised shutdown limit for nct.
Added two higher temps for cpu_edp to support higher soc_therm temps.

Doing this only for Dalmore, Pluto, Ceres, Pismo.
No real changes to Roth.

Bug 1200075

Change-Id: I2b4ac4ba7cd933bd47c30ab2ad9eabb3a3da5fbe
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/195331
(cherry picked from commit 2af79db3c5763d3a0b6e78663ccf1ad6c04be134)
Reviewed-on: http://git-master/r/197096
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: soctherm: Implement fuse correction for therm_a/b
Diwakar Tundlam [Mon, 28 Jan 2013 22:37:23 +0000]
arm: tegra: soctherm: Implement fuse correction for therm_a/b

Bug 1200077

Change-Id: I664ad343eda227548b0398809c8a9b49fec7c754
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/193236
(cherry picked from commit 79fc519fd4c1c120475c264adcd92bd52e04afdd)
Reviewed-on: http://git-master/r/197095
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoarm: tegra: board changes to enable hw throttling in soctherm
Diwakar Tundlam [Thu, 17 Jan 2013 23:23:09 +0000]
arm: tegra: board changes to enable hw throttling in soctherm

Bug 1200075

Change-Id: I407de39f60a65b55cf45fda25469b56b4fd3fccf
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/192262
(cherry picked from commit 69db11fde6c5478cedc95fa9d041b3337bade5e5)
Reviewed-on: http://git-master/r/197094
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agothermal: soctherm: enable hardware thermal throttling config
Diwakar Tundlam [Thu, 17 Jan 2013 23:21:31 +0000]
thermal: soctherm: enable hardware thermal throttling config

Bug 1200075

Change-Id: I3f6c3f3e0eca1cead8e9958d9afb5af32053d74b
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/192261
(cherry picked from commit c0c5e900e5aabecc91a01e1fb074cbe4ad588a4b)
Reviewed-on: http://git-master/r/197093
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

5 years agoARM: tegra11: clock: Update direct access to CPU backup source
Alex Frid [Tue, 29 Jan 2013 20:49:42 +0000]
ARM: tegra11: clock: Update direct access to CPU backup source

Minimized locking calls in CPU backup source direct access API.

Change-Id: I483537ce55e360259d2fbfbf85b705b53fe42e55
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/195398
(cherry picked from commit 85da379e26fd01e14e4934a79a3286a72b1167d9)
Reviewed-on: http://git-master/r/196813
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Add CPU clock set parent abort message
Alex Frid [Tue, 22 Jan 2013 21:00:38 +0000]
ARM: tegra11: clock: Add CPU clock set parent abort message

Change-Id: I9fecef82634a53189f5054d9c30e7580997603a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/193175
(cherry picked from commit bb6bd2c6c5be76ebd3340003a17ac5675c18ef5a)
Reviewed-on: http://git-master/r/196812
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Force out-of-table shared bus max limit
Alex Frid [Fri, 25 Jan 2013 08:05:20 +0000]
ARM: tegra11: clock: Force out-of-table shared bus max limit

So far, rate cap set by shared bus user with SHARED_CEILING attribute
was not clipped to possible bus rates. Since final rounding on shared
bus is always in up direction, bus clock could run at rate above the
ceiling that does not exactly match one of available bus rates. This
is fixed now by rounding cap rate down to possible bus rate before
final shared rate is determined.

Change-Id: If1052b657b60f9a6e07b730f8a8c0f36b17fdbdd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/194845
(cherry picked from commit d6f3ddb423827893ea586c5668a56ead5deb87d2)
Reviewed-on: http://git-master/r/196811
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Disable dynamic cbus support
Alex Frid [Fri, 25 Jan 2013 06:12:33 +0000]
ARM: tegra11: clock: Disable dynamic cbus support

Disabled dynamic reload of c2bus and c3bus dvfs tables, since it is
no longer needed - all modules on each bus use the same table.

Change-Id: I7b2aa3a81a2bd9c00fc87219f391883521749765
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/194844
(cherry picked from commit dc279fea5da1dbd25682d02ef25fa3c50b1e08e4)
Reviewed-on: http://git-master/r/196810
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra11: clock: Don't propagate boot clock clean up
Alex Frid [Thu, 31 Jan 2013 05:27:50 +0000]
ARM: tegra11: clock: Don't propagate boot clock clean up

When disabling coupled gate clocks left on by boot-loader, but not
ref-counted during kernel initialization, do not propagate disable
operation to coupled parents.

Bug 1226948

Change-Id: I4b4e56138f46d08dd70be2ba3781c5845098bf22
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/195843
(cherry picked from commit d157d234ea5f5fc993c8002d40aee761118d937b)
Reviewed-on: http://git-master/r/196808
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

5 years agoARM: tegra11: clock: Update XUSB clocks initialization
Alex Frid [Fri, 11 Jan 2013 00:34:29 +0000]
ARM: tegra11: clock: Update XUSB clocks initialization

Bug 1167739

Change-Id: I3c625ce9c2038755e29c56049ed904cde99fd5e6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190440
Reviewed-on: http://git-master/r/196807
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>

5 years agoARM: tegra11: clock: Change PLLE input clock
Alex Frid [Thu, 10 Jan 2013 06:13:39 +0000]
ARM: tegra11: clock: Change PLLE input clock

Changed PLLE input clock from PLL_RE to oscillator.

Bug 1167739

Change-Id: I26e6c34174a5d57903d5732b4a89439a6e166ed6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190197
(cherry picked from commit c64aa96bff698c7ead92767a0de7484daad3431e)
Reviewed-on: http://git-master/r/196806
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>