From: Colin Cross Date: Wed, 24 Aug 2011 00:43:54 +0000 (-0700) Subject: ARM: tegra: sleep: flush tlbs when exiting wfi X-Git-Tag: daily-2014.03.25.0_l4t/l4t-r19.1~9791 X-Git-Url: https://nv-tegra.nvidia.com/r/gitweb?p=linux-3.10.git;a=commitdiff_plain;h=13e38640f16a557eb75599e7ede85264aaef1ff9 ARM: tegra: sleep: flush tlbs when exiting wfi tegra_sleep_wfi disables coherency to prepare for possibly resetting the cpu. If an interrupt is received, it exits wfi and re-enables coherency, but it was not flushing the tlbs or the branch predictor array, which could have been updated by broadcast tlb operations that were ignored. Flush the tlbs and branch predictor array when exiting. Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191 Signed-off-by: Colin Cross Rebase-Id: Re46c9045a33ad78789e7dee2788b470fd1071c83 --- diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S index d04a246df69..068806fac5f 100644 --- a/arch/arm/mach-tegra/sleep-t20.S +++ b/arch/arm/mach-tegra/sleep-t20.S @@ -180,6 +180,9 @@ ENTRY(tegra_sleep_wfi) mcr p15, 0, r11, c1, c0, 1 @ reenable coherency @ the cpu was running with coherency disabled, caches may be out of date + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 @ invalidate TLB + mcr p15, 0, r0, c7, c5, 6 @ flush BTAC #ifdef MULTI_CACHE ldr r10, =cpu_cache mov lr, pc