video: tegra: use correct params in edp code
Adeel Raza [Wed, 26 Jun 2013 22:52:53 +0000 (15:52 -0700)]
Use correct number of params for tegra_dc_sor_set_dp_linkctl(...).

Bug 1306371

Change-Id: Ib065176ff8b5d418c5f07b6ace1402d8aacfb15b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/242608
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

drivers/video/tegra/dc/dp.c

index 4a1212d..fb32b1d 100644 (file)
@@ -965,7 +965,7 @@ static int tegra_dc_dp_lt_clock_recovery(struct tegra_dc_dp_data *dp,
 
        /* Set pattern on the source side */
        tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_1,
-               cfg, false);
+               cfg);
 
        /* Now the sink side */
        ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
@@ -1067,7 +1067,7 @@ static int tegra_dc_dp_lt_channel_equalization(struct tegra_dc_dp_data *dp,
 
        /* Set pattern on the source side */
        tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_2,
-               cfg, true);
+               cfg);
 
        /* Now the sink side */
        CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_PATTERN_SET,