ARM: tegra: Use cbus for MSENC power sequence
Terje Bergstrom [Mon, 8 Oct 2012 05:09:32 +0000 (08:09 +0300)]
MSENC requires a low enough PLLC clock to be able to be turned on for
power un-gating. If 3D or other fast unit is active at the same time,
PLLC is set to too high rate and MSENC cannot be turned on.

Use the cbus clock to allow clock framework to set the PLL to correct
rate.

Bug 1060834

Change-Id: Id83c33b9a5f2f29466cc55243310642a5f53fd99
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/142190
(cherry picked from commit 94c16a960d7649bdb4b6369ae2a1cdd3fa369d71)
Reviewed-on: http://git-master/r/144889
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

Rebase-Id: R7cec7a0572098ff8e2805ecfedef399ce576d9cc

arch/arm/mach-tegra/powergate.c

index 6695ca7..5c1d15e 100644 (file)
@@ -216,7 +216,7 @@ static struct powergate_partition powergate_partition_info[TEGRA_NUM_POWERGATE]
                                        },
 #else
                                        {
-                                               {"msenc", CLK_AND_RST}
+                                               {"msenc.cbus", CLK_AND_RST}
                                        },
 #endif
                                },