tegra: host: gk20a driver use presilicon interface
Xue Dong [Mon, 14 Jan 2013 18:29:36 +0000 (10:29 -0800)]
Change-Id: I0bbd72d5f174fe780bc9644d1fe40bb98d304bda
Signed-off-by: Xue Dong <xdong@nvidia.com>
Reviewed-on: http://git-master/r/190978
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>

drivers/video/tegra/host/gk20a/gk20a.h
drivers/video/tegra/host/gk20a/gr_ctx_gk20a.c
drivers/video/tegra/host/gk20a/gr_gk20a.c
drivers/video/tegra/host/gk20a/priv_ring_gk20a.c

index 4810e1b..f910668 100644 (file)
@@ -35,7 +35,6 @@ struct gr_gk20a;
 struct sim_gk20a;
 
 #include <mach/hardware.h>
-
 #include "clk_gk20a.h"
 #include "fifo_gk20a.h"
 #include "gr_gk20a.h"
@@ -166,7 +165,7 @@ enum {
 #if defined (CONFIG_TEGRA_GK20A_PMU)
 static inline int support_gk20a_pmu(void)
 {
-       return ((tegra_revision != TEGRA_REVISION_QT) ? 1 : 0);
+       return tegra_platform_is_qt() ? 0 : 1;
 }
 #else
 static inline int support_gk20a_pmu(void){return 0;}
index 0e6e4e7..b914999 100644 (file)
@@ -327,7 +327,7 @@ done:
 
 int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr)
 {
-       if (tegra_revision == TEGRA_REVISION_SIM)
+       if (tegra_platform_is_linsim())
                return gr_gk20a_init_ctx_vars_sim(g, gr);
        else
                return gr_gk20a_init_ctx_vars_fw(g, gr);
index 34c8315..f100f72 100644 (file)
@@ -1332,7 +1332,7 @@ static int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
        /* gr_gk20a_ctx_zcull_setup(g, c, false); */
        gr_gk20a_ctx_pm_setup(g, c, false);
 
-       if (tegra_revision == TEGRA_REVISION_SIM) {
+       if (tegra_platform_is_linsim()) {
                u32 inst_base_ptr =
                        u64_lo32(c->inst_block.cpu_pa) >> ram_in_base_shift_v();
 
@@ -1373,7 +1373,7 @@ static int gr_gk20a_load_ctxsw_ucode(struct gk20a *g, struct gr_gk20a *gr)
 
        nvhost_dbg_fn("");
 
-       if (tegra_revision == TEGRA_REVISION_SIM) {
+       if (tegra_platform_is_linsim()) {
                gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7),
                        gr_fecs_ctxsw_mailbox_value_f(0xc0de7777));
                gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7),
@@ -3153,7 +3153,7 @@ static void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine)
                        "invalid elcg mode %d", mode);
        }
 
-       if (tegra_revision == TEGRA_REVISION_SIM) {
+       if (tegra_platform_is_linsim()) {
                gate_ctrl = set_field(gate_ctrl,
                        therm_gate_ctrl_eng_delay_after_m(),
                        therm_gate_ctrl_eng_delay_after_f(4));
index 16bbb40..cb5038b 100644 (file)
@@ -33,7 +33,7 @@ void gk20a_reset_priv_ring(struct gk20a *g)
        u32 pmc_en, decode_cfg, data;
        s32 retry = 200;
 
-       if (tegra_revision == TEGRA_REVISION_SIM)
+       if (tegra_platform_is_linsim())
                return;
 
        pmc_en = gk20a_readl(g, mc_enable_r());
@@ -90,7 +90,7 @@ void gk20a_priv_ring_isr(struct gk20a *g)
        u32 cmd;
        s32 retry = 100;
 
-       if (tegra_revision == TEGRA_REVISION_SIM)
+       if (tegra_platform_is_linsim())
                return;
 
        status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());