ARM: tegra: sdhci: set max clk to 200MHz for SDMMC3
Shreshtha Sahu [Wed, 21 May 2014 06:39:50 +0000 (11:39 +0530)]
This patch sets max clk limit to 200MHz for SDMMC3 for PM375.
Requesting 208MHz results in getting 204MHz from PLL_P and CRC
errors are seen.

Bug 1505798

Change-Id: I14825335fa5895ef2dde905f1e3cd568d2dafa62
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412542
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-sdhci.c

index 19420ed..80ea1e8 100644 (file)
@@ -448,6 +448,14 @@ int __init ardbeg_sdhci_init(void)
                board_info.board_id == BOARD_PM359)
                        tegra_sdhci_platform_data0.disable_clock_gate = 1;
 
+       /*
+        * FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375.
+        * Requesting 208MHz results in getting 204MHz from PLL_P
+        * and CRC errors are seen with same.
+        */
+       if (board_info.board_id == BOARD_PM375)
+               tegra_sdhci_platform_data2.max_clk_limit = 200000000;
+
        speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
        tegra_sdhci_platform_data0.cpu_speedo = speedo;
        tegra_sdhci_platform_data2.cpu_speedo = speedo;