ARM: tegra: Skip unnecessary L1 flush for all tegra chips
Bo Yan [Mon, 10 Dec 2012 18:32:13 +0000 (10:32 -0800)]
Change-Id: I52b7ae07c42f0f76b5e1e6d8564c9cb518c359a6
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169768
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

arch/arm/kernel/smp.c
arch/arm/kernel/suspend.c
arch/arm/mach-tegra/sleep-t20.S
arch/arm/mach-tegra/sleep-t30.S

index 0a93ea0..f9304a4 100644 (file)
@@ -184,7 +184,7 @@ int __cpuinit __cpu_disable(void)
         */
        percpu_timer_stop();
 
-#ifndef CONFIG_ARCH_TEGRA_11x_SOC
+#ifndef CONFIG_ARCH_TEGRA
        /*
         * Flush user cache and TLB mappings, and then remove this CPU
         * from the vm mask set of all processes.
index 7cf10e4..0f216b3 100644 (file)
@@ -28,7 +28,7 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
 
        cpu_do_suspend(ptr);
 
-#ifndef CONFIG_ARCH_TEGRA_11x_SOC
+#ifndef CONFIG_ARCH_TEGRA
        flush_cache_louis();
 #endif
 
index 3b50f3e..b189e57 100644 (file)
@@ -168,6 +168,9 @@ ENDPROC(tegra2_cpu_is_resettable_soon)
  * tegra2_tear_down_core in IRAM
  */
 ENTRY(tegra2_sleep_core_finish)
+       mov     r4, r0
+       bl      tegra_flush_cache
+       mov     r0, r4
        bl      tegra_cpu_exit_coherency
        mov32   r1, tegra2_tear_down_core
        mov32   r2, tegra2_iram_start
@@ -186,13 +189,7 @@ ENTRY(tegra2_finish_sleep_cpu_secondary)
        mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
 
        dsb
-#ifdef MULTI_CACHE
-       mov32   r10, cpu_cache
-       mov     lr, pc
-       ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
-#else
-       bl      __cpuc_flush_kern_all
-#endif
+       bl      tegra_flush_l1_cache
 
        bl      tegra_cpu_exit_coherency
 
index 1cd9636..d950ae8 100644 (file)
@@ -233,11 +233,9 @@ ENDPROC(tegra30_cpu_shutdown)
  * tegra3_tear_down_core in IRAM
  */
 ENTRY(tegra3_sleep_core_finish)
-#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
        mov     r4, r0
        bl      tegra_flush_cache
        mov     r0, r4
-#endif
        bl      tegra_cpu_exit_coherency
 
        /* preload all the address literals that are needed for the