ARM: tegra: t124: Set DDR mode's TRIM_VAL to 0
Naveen Kumar Arepalli [Wed, 16 Oct 2013 08:52:15 +0000 (13:52 +0530)]
-For eMMC change DDR mode's TRIM_VAL from 4 to 0
as per char team data.

Bug 1333552

Change-Id: Ia5d877be07de80dcfe55ca8f78528e8a6a6fa12c
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/299864
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-ardbeg-sdhci.c
arch/arm/mach-tegra/board-loki-sdhci.c

index c7c6314..f829947 100644 (file)
@@ -193,7 +193,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .is_8bit = 1,
        .tap_delay = 0x4,
        .trim_delay = 0x4,
-       .ddr_trim_delay = 0x4,
+       .ddr_trim_delay = 0x0,
        .mmc_data = {
                .built_in = 1,
                .ocr_mask = MMC_OCR_1V8_MASK,
index d93d786..b5ae1fd 100644 (file)
@@ -175,7 +175,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .is_8bit = 1,
        .tap_delay = 0x4,
        .trim_delay = 0x4,
-       .ddr_trim_delay = 0x4,
+       .ddr_trim_delay = 0x0,
        .mmc_data = {
                .built_in = 1,
                .ocr_mask = MMC_OCR_1V8_MASK,