video: tegra: dtv: Move swizzling into ioctl
Adam Jiang [Mon, 15 Apr 2013 09:21:09 +0000 (18:21 +0900)]
Move swizzling options into ioctl for providing a unique interface of
hardware configuration.

Bug 1061456
Bug 1258577

Change-Id: I6c9d9b171a170fbe9e9df78b4dac07347d63861e
(cherry picked from commit 25371c35ddf720fc2b975d5c20d81c32eec4ecf1)
(cherry picked from commit 8d408223cd6f26db34adb434ee54e2bf7a47b9e6)
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/224681
Reviewed-on: http://git-master/r/244470
Reviewed-on: http://git-master/r/256186
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/include/mach/dtv.h
drivers/media/video/tegra/tegra_dtv.c
include/media/tegra_dtv.h

index 31a54d0..4329276 100644 (file)
@@ -3,7 +3,7 @@
  *
  * Header file for describing resources of DTV module
  *
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Authors:
  *     Adam Jiang <chaoj@nvidia.com>
 /* DTV_MODE_0 */
 #define DTV_MODE_BYTE_SWIZZLE_SHIFT 6
 #define DTV_MODE_BYTE_SWIZZLE       (1 << DTV_MODE_BYTE_SWIZZLE_SHIFT)
+#define DTV_MODE_BYTE_SWIZZLE_MASK  1
 #define DTV_MODE_BIT_SWIZZLE_SHIFT  5
 #define DTV_MODE_BIT_SWIZZLE        (1 << DTV_MODE_BIT_SWIZZLE_SHIFT)
+#define DTV_MODE_BIT_SWIZZLE_MASK   1
 #define DTV_MODE_CLK_EDGE_SHIFT     4
 #define DTV_MODE_CLK_EDGE_MASK      1
 #define DTV_MODE_CLK_EDGE_NEG       (1 << DTV_MODE_CLK_EDGE_SHIFT)
index 8d20593..556ce60 100644 (file)
@@ -240,20 +240,25 @@ static inline void _dtv_set_attn_level(struct tegra_dtv_context *dtv_ctx)
 static inline void _dtv_set_hw_params(struct tegra_dtv_context *dtv_ctx)
 {
        u32 val = 0;
-       u32 reg;
+       u32 reg = 0;
        struct tegra_dtv_hw_config *cfg = &dtv_ctx->config;
 
-       val = (cfg->clk_edge << DTV_MODE_CLK_EDGE_SHIFT) |
+       /* program DTV_MODE */
+       val = (cfg->byte_swz_enabled << DTV_MODE_BYTE_SWIZZLE_SHIFT) |
+               (cfg->bit_swz_enabled << DTV_MODE_BIT_SWIZZLE_SHIFT) |
+               (cfg->clk_edge << DTV_MODE_CLK_EDGE_SHIFT) |
                (cfg->protocol_sel << DTV_MODE_PRTL_SEL_SHIFT) |
                (cfg->clk_mode << DTV_MODE_CLK_MODE_SHIFT);
        reg = tegra_dtv_readl(dtv_ctx, DTV_MODE);
-       reg &= ~(DTV_MODE_CLK_EDGE_MASK |
+       reg &= ~(DTV_MODE_BYTE_SWIZZLE_MASK |
+                DTV_MODE_BIT_SWIZZLE |
+                DTV_MODE_CLK_EDGE_MASK |
                 DTV_MODE_PRTL_SEL_MASK |
                 DTV_MODE_CLK_MODE_MASK);
        reg |= val;
        tegra_dtv_writel(dtv_ctx, reg, DTV_MODE);
 
-       val = 0;
+       /* program DTV_CTRL */
        reg = 0;
        val = (cfg->fec_size << DTV_CTRL_FEC_SIZE_SHIFT) |
                (cfg->body_size << DTV_CTRL_BODY_SIZE_SHIFT) |
index b06f667..cf34733 100644 (file)
@@ -126,8 +126,6 @@ enum {
 struct tegra_dtv_platform_data {
        unsigned int dma_buf_size;
        int clk_edge;
-       bool byte_swz_enabled;
-       bool bit_swz_enabled;
 };
 #endif /* __KERNEL__ */