video: tegra: dc: fix dc blending.
Kevin Huang [Mon, 1 Jul 2013 21:46:29 +0000 (14:46 -0700)]
Bug 1316102

Change-Id: I92832ca3ff1617b56071fc8a3338dade6fbcefba
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/244009
Reviewed-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>

drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_reg.h
drivers/video/tegra/dc/window.c

index 24b2ddf..95bf9a5 100644 (file)
@@ -629,17 +629,15 @@ static void _dump_regs(struct tegra_dc *dc, void *data,
                DUMP_REG(DC_WIN_V_INITIAL_DDA);
                DUMP_REG(DC_WIN_DDA_INCREMENT);
                DUMP_REG(DC_WIN_LINE_STRIDE);
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
                DUMP_REG(DC_WIN_BUF_STRIDE);
                DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 #endif
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
                DUMP_REG(DC_WIN_BLEND_NOKEY);
                DUMP_REG(DC_WIN_BLEND_1WIN);
                DUMP_REG(DC_WIN_BLEND_2WIN_X);
                DUMP_REG(DC_WIN_BLEND_2WIN_Y);
                DUMP_REG(DC_WIN_BLEND_3WIN_XY);
-#endif
                DUMP_REG(DC_WINBUF_START_ADDR);
                DUMP_REG(DC_WINBUF_START_ADDR_U);
                DUMP_REG(DC_WINBUF_START_ADDR_V);
index 1c0c6e9..0e2c571 100644 (file)
 
 #define DC_DISP_SERIAL_INTERFACE_OPTIONS       0x433
 #define DC_DISP_LCD_SPI_OPTIONS                        0x434
-
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
-
 #define DC_DISP_BORDER_COLOR                   0x435
-
-#endif
-
 #define DC_DISP_COLOR_KEY0_LOWER               0x436
 #define DC_DISP_COLOR_KEY0_UPPER               0x437
 #define DC_DISP_COLOR_KEY1_LOWER               0x438
 #define  GET_LINE_STRIDE(x)    ((x) & 0xffff)
 #define  GET_UV_LINE_STRIDE(x) (((x) >> 16) & 0xffff)
 
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
-
 #define DC_WINBUF_BLEND_LAYER_CONTROL          0x716
 #define  WIN_K1(x)                     (((x) & 0xff) << 8)
 #define  WIN_K2(x)                     (((x) & 0xff) << 16)
 #define  DC_WIN_BUFFER_ADDR_MODE_TILE          (1 << 0)
 #define  DC_WIN_BUFFER_ADDR_MODE_TILE_UV       (1 << 16)
 
-#endif
-
 #define DC_WIN_DV_CONTROL                      0x70e
-
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
-
 #define DC_WIN_BLEND_NOKEY                     0x70f
 #define DC_WIN_BLEND_1WIN                      0x710
 #define DC_WIN_BLEND_2WIN_X                    0x711
          (CKEY_ ## key | BLEND_CONTROL_ ## control |           \
           BLEND_WEIGHT0(weight0) | BLEND_WEIGHT1(weight1))
 
-#endif
-
 #if defined(CONFIG_TEGRA_DC_BLOCK_LINEAR)
 
 #define DC_WIN_BUFFER_SURFACE_KIND             0x80b
 #define DC_WINBUF_TD_UFLOW_STATUS              0x14a
 #endif
 
-#if defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
-
 #define DC_WINBUF_BLEND_LAYER_CONTROL          0x716
 #define  WIN_DEPTH(x)                  (((x) & 0xff) << 0)
 #define  WIN_K1(x)                     (((x) & 0xff) << 8)
 #define  WIN_ALPHA_1BIT_WEIGHT0(x)     (((x) & 0xff) << 0)
 #define  WIN_ALPHA_1BIT_WEIGHT1(x)     (((x) & 0xff) << 8)
 
-#endif
-
 
 #define DC_DISP_SD_CONTROL                     0x4c2
 #define  SD_ENABLE_NORMAL              (1 << 0)
 #define  WINH_CURS_SELECT(x)           (((x) & 0x1) << 28)
 #define  CURSOR_MODE_SELECT(x)         (((x) & 0x1) << 24)
 
-#if defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
-
 #define DC_DISP_BLEND_BACKGROUND_COLOR         0x4e4
 
 #endif
-
-#endif
index 7a7ca80..da0134e 100644 (file)
@@ -63,7 +63,6 @@ int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
        return 0;
 }
 
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
 static int get_topmost_window(u32 *depths, unsigned long *wins, int win_num)
 {
        int idx, best = -1;
@@ -156,12 +155,10 @@ static u32 blend_3win(int idx, unsigned long behind_mask,
                }
        }
 }
-#endif
 
 static void tegra_dc_blend_parallel(struct tegra_dc *dc,
                                struct tegra_dc_blend *blend)
 {
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
        int win_num = dc->gen1_blend_num;
        unsigned long mask = BIT(win_num) - 1;
 
@@ -180,14 +177,12 @@ static void tegra_dc_blend_parallel(struct tegra_dc *dc,
                tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags,
                                win_num), DC_WIN_BLEND_3WIN_XY);
        }
-#endif
        tegra_dc_io_end(dc);
 }
 
 static void tegra_dc_blend_sequential(struct tegra_dc *dc,
                                struct tegra_dc_blend *blend)
 {
-#if defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
        int idx;
        unsigned long mask = dc->valid_windows;
 
@@ -255,7 +250,6 @@ static void tegra_dc_blend_sequential(struct tegra_dc *dc,
                                        DC_WINBUF_BLEND_LAYER_CONTROL);
                }
        }
-#endif
        tegra_dc_io_end(dc);
 }
 
@@ -551,7 +545,7 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
                        tegra_dc_update_scaling(dc, win, Bpp, Bpp_bw,
                                                                scan_column);
 
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
+#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
                tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
                tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 #endif
@@ -705,7 +699,6 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
        }
 #endif
 
-#if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
                if (tegra_dc_feature_has_tiling(dc, win->idx)) {
                        if (WIN_IS_TILED(win))
                                tegra_dc_writel(dc,
@@ -718,7 +711,6 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
                                        DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
                                        DC_WIN_BUFFER_ADDR_MODE);
                }
-#endif
 
 #if defined(CONFIG_TEGRA_DC_BLOCK_LINEAR)
                if (tegra_dc_feature_has_blocklinear(dc, win->idx) ||