ARM: tegra11: clock: Fix SCLK input mux
Alex Frid [Thu, 17 Jan 2013 02:40:11 +0000 (18:40 -0800)]
Replaced secondary divider PLLP_OUT3 in system clock input mux
definition with main PLLP output to match h/w.

Change-Id: Icdf2de2bf79665bccbe9e68d12386e0b9738960f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191893
(cherry picked from commit c26c8139a29d4fc892deb5c4487486b43e7fac1f)
Reviewed-on: http://git-master/r/192656
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 543043e..e0e2765 100644 (file)
@@ -5875,7 +5875,7 @@ static struct clk_mux_sel mux_sclk[] = {
        { .input = &tegra_clk_m,        .value = 0},
        { .input = &tegra_pll_c_out1,   .value = 1},
        { .input = &tegra_pll_p_out4,   .value = 2},
-       { .input = &tegra_pll_p_out3,   .value = 3},
+       { .input = &tegra_pll_p,        .value = 3},
        { .input = &tegra_pll_p_out2,   .value = 4},
        /* { .input = &tegra_clk_d,     .value = 5}, - no use on tegra11x */
        { .input = &tegra_clk_32k,      .value = 6},