video: tegra: dc: add support for block linear format
Mark Stadler [Thu, 9 Aug 2012 02:17:36 +0000 (19:17 -0700)]
Change-Id: Icd8feba013b1d6d00b9c3b685b22f5feb7778ba4
Reviewed-on: http://git-master/r/113407
Tested-by: Xue Dong <xdong@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chao Xu <cxu@nvidia.com>
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Signed-off-by: Mark Stadler <mastadler@nvidia.com>

drivers/video/tegra/Kconfig
drivers/video/tegra/dc/dc_config.c
drivers/video/tegra/dc/dc_config.h
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dc_reg.h

index df6c068..75ea62f 100644 (file)
@@ -70,6 +70,11 @@ config TEGRA_DC_BLENDER_GEN2
     default n if ARCH_TEGRA_2x_SOC || ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
     default y
 
+config TEGRA_DC_BLOCK_LINEAR
+    bool
+    default y if ARCH_TEGRA_12x_SOC
+    default n
+
 config TEGRA_SD_GEN2
        bool
        default n if ARCH_TEGRA_2x_SOC || ARCH_TEGRA_3x_SOC
index 5fc6eec..39f8b2e 100644 (file)
@@ -210,7 +210,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 0, TEGRA_DC_FEATURE_FILTER_TYPE, {0, 0,} },
-       { 0, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 0, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 0, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 
        { 1, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_WIN_B,} },
@@ -219,7 +219,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 1, TEGRA_DC_FEATURE_FILTER_TYPE, {1, 1,} },
-       { 1, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 1, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 1, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 
        { 2, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_WIN_C,} },
@@ -227,7 +227,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_a[] = {
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 2, TEGRA_DC_FEATURE_FILTER_TYPE, {0, 1,} },
-       { 2, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 2, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 2, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 };
 
@@ -237,7 +237,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 0, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 0, TEGRA_DC_FEATURE_FILTER_TYPE, {0, 0,} },
-       { 0, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 0, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 0, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 
        { 1, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_WIN_B,} },
@@ -246,7 +246,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 1, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 1, TEGRA_DC_FEATURE_FILTER_TYPE, {1, 1,} },
-       { 1, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 1, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 1, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 
        { 2, TEGRA_DC_FEATURE_FORMATS, {TEGRA_WIN_FMT_WIN_C,} },
@@ -254,7 +254,7 @@ static struct tegra_dc_feature_entry t124_feature_entries_b[] = {
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SIZE, {4095, 16, 4095, 16,} },
        { 2, TEGRA_DC_FEATURE_MAXIMUM_SCALE, {2, 2, 2, 2,} },
        { 2, TEGRA_DC_FEATURE_FILTER_TYPE, {0, 1,} },
-       { 2, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1,} },
+       { 2, TEGRA_DC_FEATURE_LAYOUT_TYPE, {1, 1, 1,} },
        { 2, TEGRA_DC_FEATURE_INVERT_TYPE, {1, 1, 0,} },
 };
 
@@ -397,6 +397,9 @@ long *tegra_dc_parse_feature(struct tegra_dc *dc, int win_idx, int operation)
        case HAS_GEN2_BLEND:
                option = TEGRA_DC_FEATURE_BLEND_TYPE;
                break;
+       case HAS_BLOCKLINEAR:
+               option = TEGRA_DC_FEATURE_LAYOUT_TYPE;
+               break;
        default:
                return NULL;
        }
@@ -427,6 +430,13 @@ int tegra_dc_feature_has_tiling(struct tegra_dc *dc, int win_idx)
        return addr[TILED_LAYOUT];
 }
 
+int tegra_dc_feature_has_blocklinear(struct tegra_dc *dc, int win_idx)
+{
+       long *addr = tegra_dc_parse_feature(dc, win_idx, HAS_BLOCKLINEAR);
+
+       return addr[BLOCK_LINEAR];
+}
+
 int tegra_dc_feature_has_filter(struct tegra_dc *dc, int win_idx, int operation)
 {
        long *addr = tegra_dc_parse_feature(dc, win_idx, operation);
index 0ef076c..160b1df 100644 (file)
 /* Define the offset for TEGRA_DC_FEATURE_LAYOUT_TYPE. */
 #define PITCHED_LAYOUT 0
 #define TILED_LAYOUT   1
+#define BLOCK_LINEAR   2
 
 /* Define the offset for TEGRA_DC_FEATURE_BLEND_TYPE. */
 #define BLEND_GENERATION       0
@@ -123,6 +124,7 @@ enum {
        HAS_GEN2_BLEND,
        GET_WIN_FORMATS,
        GET_WIN_SIZE,
+       HAS_BLOCKLINEAR,
 };
 
 enum tegra_dc_feature_option {
@@ -149,6 +151,7 @@ struct tegra_dc_feature {
 
 int tegra_dc_feature_has_scaling(struct tegra_dc *dc, int win_idx);
 int tegra_dc_feature_has_tiling(struct tegra_dc *dc, int win_idx);
+int tegra_dc_feature_has_blocklinear(struct tegra_dc *dc, int win_idx);
 int tegra_dc_feature_has_filter(struct tegra_dc *dc, int win_idx, int operation);
 int tegra_dc_feature_is_gen2_blender(struct tegra_dc *dc, int win_idx);
 
index 7197b38..7e5cece 100644 (file)
@@ -23,6 +23,7 @@
 #include "dc_priv_defs.h"
 #ifndef CREATE_TRACE_POINTS
 # include <trace/events/display.h>
+#define WIN_IS_BLOCKLINEAR(win)        ((win)->flags & TEGRA_WIN_FLAG_BLOCKLINEAR)
 #endif
 #include <mach/powergate.h>
 #include <video/tegra_dc_ext.h>
index dbfede3..263ea50 100644 (file)
 
 #endif
 
+#if defined(CONFIG_TEGRA_DC_BLOCK_LINEAR)
+
+#define DC_WIN_BUFFER_SURFACE_KIND             0xdcb
+#define DC_WIN_BUFFER_SURFACE_PITCH            (0 << 0)
+#define DC_WIN_BUFFER_SURFACE_TILED            (1 << 0)
+#define DC_WIN_BUFFER_SURFACE_BL_16B2          (1 << 1)
+
+#endif
 
 #define DC_WIN_HP_FETCH_CONTROL                        0x714