ARM: tegra: remove t14x support
Bo Yan [Fri, 7 Nov 2014 20:22:41 +0000 (12:22 -0800)]
Change-Id: Ib121404db493e07c0d2e8c1cf79536404e6849cb
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/598835
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/headsmp.S
arch/arm/mach-tegra/hotplug.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/sleep-t30.S

index 497387f..9869ecc 100644 (file)
@@ -120,14 +120,10 @@ cpu_not_secure:
        mov32   r0, TEGRA_ARM_PERIF_BASE
        ldr     r1, [r0]
        orr     r1, r1, #1
-#ifdef CONFIG_ARCH_TEGRA_14x_SOC
-       orr     r1, r1, #8
-#endif
        str     r1, [r0]
 #endif /* CONFIG_HAVE_ARM_SCU */
 
 #ifdef CONFIG_CACHE_L2X0
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        cmp     r12, #1                 @ secure firmware present?
        beq     cpu_resume
 
@@ -142,7 +138,7 @@ cpu_not_secure:
 #if defined(CONFIG_ARCH_TEGRA_2x_SOC)
        mov32   r0, 0x331                       /* tag latency */
        mov32   r1, 0x441                       /* data latency */
-#elif defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
+#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
        mov32   r0, TEGRA_FLOW_CTRL_BASE + 0x2c /* FLOW_CTRL_CLUSTER_CONTROL */
        mov32   r2, RESET_DATA_PHYS
@@ -156,14 +152,10 @@ cpu_not_secure:
        mov32   r0, #0x770                      /* tag latency */
        mov32   r1, #0x770                      /* data latency */
 #endif /* ?CONFIG_TEGRA_SILICON_PLATFORM */
-#endif /* CONFIG_ARCH_TEGRA_3x_SOC || CONFIG_ARCH_TEGRA_14x_SOC */
+#endif /* CONFIG_ARCH_TEGRA_3x_SOC */
        str     r0, [r3, #L2X0_TAG_LATENCY_CTRL]
        str     r1, [r3, #L2X0_DATA_LATENCY_CTRL]
-#ifdef CONFIG_ARCH_TEGRA_14x_SOC
-       mov32   r0, 0x40000007  /* Enable double line fill */
-#else
        mov     r0, #7
-#endif
        str     r0, [r3, #L2X0_PREFETCH_CTRL]
        mov     r0, #3
        str     r0, [r3, #L2X0_POWER_CTRL]
@@ -180,7 +172,6 @@ cpu_not_secure:
        str     r2, [r3, #L2X0_AUX_CTRL]
        mov     r2, #1
        str     r2, [r3, #L2X0_CTRL]
-#endif /* CONFIG_ARCH_TEGRA_14x_SOC */
 #endif /* CONFIG_CACHE_L2X0 */
 no_l2_init:
        b       cpu_resume
index 20f5f21..081b995 100644 (file)
@@ -2,7 +2,7 @@
  *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
- *  Copyright (C) 2010-2013 NVIDIA Corporation. All rights reserved.
+ *  Copyright (C) 2010-2014 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -69,13 +69,8 @@ void __init tegra20_hotplug_init(void)
 }
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_12x_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_14x_SOC)
 extern void tegra30_hotplug_shutdown(void);
 void __init tegra30_hotplug_init(void)
 {
        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
-#endif
index 3164152..c2f536e 100644 (file)
@@ -83,9 +83,6 @@
 #include "sleep.h"
 #include <linux/platform/tegra/dvfs.h>
 #include <linux/platform/tegra/cpu-tegra.h>
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-#include "tegra14_scratch.h"
-#endif
 
 struct suspend_context {
        /*
@@ -123,9 +120,6 @@ static unsigned long iram_save_size;
 static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
 static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-static void __iomem *tert_ictlr = IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE);
-#endif
 static int tegra_last_pclk;
 static u64 resume_time;
 static u64 resume_entry_time;
@@ -133,15 +127,7 @@ static u64 suspend_time;
 static u64 suspend_entry_time;
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-static void update_pmc_registers(unsigned long rate);
-#endif
-
 struct suspend_context tegra_sctx;
-#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && defined(CONFIG_ARCH_TEGRA_14x_SOC)
-extern struct device *get_se_device(void);
-extern int se_suspend(struct device *dev, bool pooling);
-#endif
 
 bool tegra_is_dpd_mode;
 
@@ -164,7 +150,7 @@ bool tegra_is_dpd_mode;
 #define PMC_DPAD_ORIDE         0x1C
 #define PMC_WAKE_DELAY         0xe0
 #define PMC_DPD_SAMPLE         0x20
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
 #define PMC_DPD_ENABLE         0x24
 #endif
 #define PMC_IO_DPD_REQ          0x1B8
@@ -884,7 +870,6 @@ unsigned int tegra_idle_power_down_last(unsigned int sleep_time,
                flush_cache_all();
                outer_disable();
        }
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        if (!tegra_cpu_is_secure()) {
                tegra_resume_l2_init = 1;
                __cpuc_flush_dcache_area(&tegra_resume_l2_init,
@@ -893,56 +878,21 @@ unsigned int tegra_idle_power_down_last(unsigned int sleep_time,
                          __pa(&tegra_resume_l2_init) + sizeof(unsigned long));
        }
 #endif
-#endif
 
        /* T148: Check for mem_req and mem_req_soon only if it is
         * MC clock stop state.
         */
        if (flags & TEGRA_POWER_STOP_MC_CLK) {
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-               u32 val;
-
-               /* Check if mem_req or mem_req_soon is asserted or if voice
-                * call is active call, if yes then we skip SDRAM
-                * self-refresh and just do CPU power-gating.
-                */
-               val = readl(pmc + PMC_IPC_STS);
-               if ((val & (PMC_IPC_STS_MEM_REQ | PMC_IPC_STS_MEM_REQ_SOON)) ||
-                       tegra_is_voice_call_active()) {
-
-                       /* Reset LP1 and MC clock mask if we skipping SDRAM
-                        * self-refresh.
-                        */
-                       *iram_cpu_lp1_mask = 0;
-                       *iram_mc_clk_mask = 0;
-                       writel(0, pmc + PMC_SCRATCH41);
-
-                       tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
-               } else {
-                       /* Clear mem_sts since SDRAM will not be accessible
-                        * to BBC in this state.
-                        */
-                       val = PMC_IPC_CLR_MEM_STS;
-                       writel(val, pmc + PMC_IPC_CLR);
-
-                       tegra_stop_mc_clk(PHYS_OFFSET - PAGE_OFFSET);
-               }
-#else
                /* If it is not T148 then we do not have to
                 * check mem_req and mem_req_soon.
                 */
                tegra_stop_mc_clk(PHYS_OFFSET - PAGE_OFFSET);
-#endif
        } else {
                tegra_sleep_cpu(PHYS_OFFSET - PAGE_OFFSET);
        }
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       tegra_init_cache(true);
-#else
        if (tegra_cpu_is_secure())
                tegra_init_cache(false);
-#endif
 
 #if defined(CONFIG_TRUSTED_FOUNDATIONS)
 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
@@ -1046,7 +996,7 @@ static void tegra_common_resume(void)
        void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_12x_SOC)
        /* Clear DPD Enable */
        writel(0x0, pmc + PMC_DPD_ENABLE);
 #endif
@@ -1234,34 +1184,6 @@ static void tegra_suspend_check_pwr_stats(void)
        return;
 }
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-/* This is the opposite of the LP1BB related PMC setup that occurs
- * during suspend.
- */
-static void tegra_disable_lp1bb_interrupt(void)
-{
-       unsigned reg;
-       /* mem_req = 0 was set as an interrupt during LP1BB entry.
-        * It has to be disabled now
-        */
-       reg = readl(pmc + PMC_CTRL2);
-       reg &= ~(PMC_CTRL2_WAKE_DET_EN);
-       pmc_32kwritel(reg, PMC_CTRL2);
-
-       /* Program mem_req NOT to be a wake event */
-       reg = readl(pmc + PMC_WAKE2_MASK);
-       reg &= ~(PMC_WAKE2_BB_MEM_REQ);
-       pmc_32kwritel(reg, PMC_WAKE2_MASK);
-
-       reg = PMC_WAKE2_BB_MEM_REQ;
-       pmc_32kwritel(reg, PMC_WAKE2_STATUS);
-
-       /* Set up the LIC to NOT accept pmc_wake events as interrupts */
-       reg = TRI_ICTLR_PMC_WAKE_INT;
-       writel(reg, tert_ictlr + TRI_ICTLR_CPU_IER_CLR);
-}
-#endif
-
 static void tegra_suspend_powergate_control(int partid, bool turn_off)
 {
        if (turn_off)
@@ -1276,9 +1198,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
        u32 scratch37 = 0xDEADBEEF;
        u32 reg;
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       u32 enter_state = 0;
-#endif
        bool tegra_suspend_vde_powergated = false;
 
        if (WARN_ON(mode <= TEGRA_SUSPEND_NONE ||
@@ -1287,10 +1206,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
                goto fail;
        }
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       update_pmc_registers(tegra_lp1bb_emc_min_rate_get());
-#endif
-
        if (tegra_is_voice_call_active()) {
                /* backup the current value of scratch37 */
                scratch37 = readl(pmc + PMC_SCRATCH37);
@@ -1326,10 +1241,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
 
        local_fiq_disable();
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       tegra_smp_save_power_mask();
-#endif
-
        trace_cpu_suspend(CPU_SUSPEND_START, tegra_rtc_read_ms());
 
        if (mode == TEGRA_SUSPEND_LP0) {
@@ -1349,9 +1260,7 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
                        tegra_smp_clear_power_mask();
        }
 
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        if (mode == TEGRA_SUSPEND_LP1)
-#endif
                *iram_cpu_lp1_mask = 1;
 
        suspend_cpu_complex(flags);
@@ -1384,19 +1293,6 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
 
        tegra_init_cache(true);
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       reg = readl(pmc + PMC_LP_STATE_SCRATCH_REG);
-       enter_state = (reg >> PMC_LP_STATE_BIT_OFFSET) & PMC_LP_STATE_BIT_MASK;
-       /* If we actually had entered in either LP1 or LP1BB,
-        * restore power mask and disable mem_req interrupt PMC
-        */
-       if (enter_state) {
-               pr_debug("Exited state is LP1/LP1BB\n");
-               tegra_disable_lp1bb_interrupt();
-               tegra_smp_restore_power_mask();
-       }
-#endif
-
        if (tegra_cpu_is_secure()) {
 #ifndef CONFIG_ARCH_TEGRA_11x_SOC
                trace_smc_wake(tegra_resume_smc_entry_time, NVSEC_SMC_START);
@@ -1426,9 +1322,7 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
                tegra_tsc_wait_for_resume();
        }
 
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        if (mode == TEGRA_SUSPEND_LP1)
-#endif
                *iram_cpu_lp1_mask = 0;
 
        /* if scratch37 was clobbered during LP1, restore it */
@@ -1930,56 +1824,6 @@ unsigned long tegra_lp1bb_emc_min_rate_get(void)
        return pdata->lp1bb_emc_rate_min;
 }
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-static inline bool pmc_write_check(int index, int bit_position)
-{
-       if (pmc_write_bitmap[index] & (1 << bit_position))
-               return true;
-       else
-               return false;
-}
-
-static void update_pmc_registers(unsigned long rate)
-{
-       u32 i, j;
-       int instance = 1;
-
-       /* FIXME: convert rate to instance */
-
-       /* Based on index, we select that block of scratches */
-       u32 base2 = (tegra_wb0_params_address + (instance - 1) *
-               tegra_wb0_params_block_size);
-       void __iomem *base = ioremap(base2, tegra_wb0_params_block_size);
-
-#define copy_dram_to_pmc(index, bit)   \
-       pmc_32kwritel(readl(base + PMC_REGISTER_OFFSET(index, bit)), \
-               PMC_REGISTER_OFFSET(index, bit) + PMC_SCRATCH0)
-
-
-       /* Iterate through the bitmap, and copy those registers
-        * which are marked in the bitmap
-        */
-       for (i = 0, j = 0; j < ARRAY_SIZE(pmc_write_bitmap);) {
-               if (pmc_write_bitmap[j] == 0) {
-                       j++;
-                       i = 0;
-                       continue;
-               }
-
-               if (pmc_write_check(j, i))
-                       copy_dram_to_pmc(j, i);
-
-               if (++i > (sizeof(pmc_write_bitmap[0]) * 8)) {
-                       i = 0;
-                       j++;
-               }
-       }
-
-#undef copy_dram_to_pmc
-       iounmap(base);
-}
-#endif
-
 #ifdef CONFIG_ARM_ARCH_TIMER
 
 static u32 tsc_suspend_start;
index 2bb5b01..5a98dea 100644 (file)
@@ -608,8 +608,7 @@ resume_lp1:
        /* Restore the Core voltage back to high */
        set_voltage r1, r4, r3, r0, lp1_register_core_highvolt
 
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        add     r5, pc, #tegra3_sdram_pad_save-(.+8)    @ r5 --> saved data
 #endif
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
@@ -654,22 +653,8 @@ powerup_l2_done:
        str     r0, [r2, #PMC_REMOVE_CLAMPING_CMD]
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-
-       /* If we are waking up from LP1, unconditionally continue
-        * resume.
-        */
-       mov32   r4, TEGRA_PMC_BASE
-       ldr     r0, [r4, #PMC_LP_STATE_SCRATCH_REG]
-       mov     r0, r0, lsr #PMC_LP_STATE_BIT_OFFSET
-       and     r0, r0, #PMC_LP_STATE_BIT_MASK
-       cmp     r0, #PMC_LP_STATE_LP1BB
-       beq     self_refresh_skip
-#endif
-
 emc_exit_selfrefresh:
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        mov32   r0, TEGRA_EMC_BASE              @ r0 reserved for emc base
        add     r5, pc, #tegra3_sdram_pad_save-(.+8)    @ r5 --> saved data
 #endif
@@ -770,7 +755,7 @@ emc_wait_audo_cal_onetime:
        mov     r1, #0
        str     r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
        mov     r1, #1
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
        str     r1, [r0, #EMC_NOP]
        str     r1, [r0, #EMC_NOP]
 #endif
@@ -850,22 +835,12 @@ zcal_done:
        bne     exit_self_refresh
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       /* In the LP1 case, we need to set the Memory status from
-        * AP to BB, so that memory transactions can take place
-        */
-       mov32   r4, TEGRA_PMC_BASE
-       mov     r1, #PMC_IPC_SET_MEM_STS
-       str     r1, [r4, #PMC_IPC_SET]
-self_refresh_skip:
-#endif
        mov32   r0, TEGRA_PMC_BASE
        ldr     r0, [r0, #PMC_SCRATCH41]
        mov     pc, r0
 ENDPROC(tegra3_lp1_reset)
 
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        .align  L1_CACHE_SHIFT
        .type   tegra3_sdram_pad_save, %object
 tegra3_sdram_pad_save:
@@ -946,140 +921,11 @@ lp1_register_core_highvolt:
 pllm_state:
        .word   0
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-lp_enter_state:
-       .word   0
-#endif
-
 /* tegra3_tear_down_core
  *
  * LP0 entry check conditions w.r.t BB take place here
  */
 tegra3_tear_down_core:
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       /* Checking for BB-idle or Paging case */
-       ldr     r0, [r4, #PMC_IPC_STS]
-       tst     r0, #PMC_IPC_STS_MEM_REQ | PMC_IPC_STS_MEM_REQ_SOON
-       bne     lp1bb_entry
-
-       /* Write PMC_IPC_CLR[mem_sts] = 1 */
-       mov     r1, #PMC_IPC_CLR_MEM_STS
-       str     r1, [r4, #PMC_IPC_CLR]
-
-       /* Clear FLOW_IPC_STS[AP2BB_MSC_STS[0]] */
-       ldr     r1, [r6, #FLOW_IPC_STS]
-       bic     r1, #FLOW_IPC_STS_AP2BB_MSC_STS_0
-       str     r1, [r6, #FLOW_IPC_STS]
-
-       b       tegra3_lp0_tear_down_core
-
-/* lp1bb_entry
- * Set up mem_req active low to be a wake event.
- * Configure the EVP reset vector.
- * Set up LIC to accept pmc wake events as interrupts.
- * Clear previously set warmboot and side_effect bits
- * Invoke remaining LP routines.
- */
-lp1bb_entry:
-       bl      tegra148_lp1bb_clear_warmboot_flag
-       mov     r0, #PMC_LP_STATE_LP1BB
-       str     r0, lp_enter_state
-       bl      tegra148_set_lp_state
-       bl      tegra148_set_mem_req_interrupt
-       bl      tegra3_save_config
-       bl      tegra3_cpu_clk32k
-       b       tegra3_enter_sleep
-
-/* Based on LP state being entered, sets mem_req=0
- * or mem_req=1 as a wake interrupt
- */
-tegra148_set_mem_req_interrupt:
-       /* Clear the PMC_CTRL2_WAKE_DET_EN bit */
-       ldr     r0, [r4, #PMC_CTRL2]
-       bic     r0, r0, #PMC_CTRL2_WAKE_DET_EN
-       str     r0, [r4, #PMC_CTRL2]
-
-       /* Program the wake_level2 registers */
-       ldr     r0, [r4, #PMC_WAKE2_LEVEL]
-       ldr     r1, lp_enter_state
-       cmp     r1, #PMC_LP_STATE_LP1BB
-       biceq   r0, r0, #PMC_WAKE2_BB_MEM_REQ
-       orrne   r0, r0, #PMC_WAKE2_BB_MEM_REQ
-       str     r0, [r4, #PMC_WAKE2_LEVEL]
-
-       /* Wait for 1ms for write to take effect */
-       mov32   r7, TEGRA_TMRUS_BASE
-       wait_for_us r1, r7, r9
-       add r1, r1, #100
-       wait_until r1, r7, r9
-
-       /* Program the auto_wake_lvl regsiters */
-       ldr     r0, [r4, #PMC_AUTO_WAKE_LVL]
-       orr     r0, r0, #1
-       str     r0, [r4, #PMC_AUTO_WAKE_LVL]
-
-       /* Wait for 1ms for write to take effect */
-       mov32   r7, TEGRA_TMRUS_BASE
-       wait_for_us r1, r7, r9
-       add r1, r1, #100
-       wait_until r1, r7, r9
-
-       /* Configure mem_req active low to be wake event */
-       ldr     r0, [r4, #PMC_WAKE2_MASK]
-       orr     r0, r0, #PMC_WAKE2_BB_MEM_REQ
-       str     r0, [r4, #PMC_WAKE2_MASK]
-
-       ldr     r0, [r4, #PMC_CTRL2]
-       orr     r0, r0, #PMC_CTRL2_WAKE_DET_EN
-       str     r0, [r4, #PMC_CTRL2]
-
-       /* Set up the LIC to accept pmc_wake events as interrupts */
-       ldr     r8, =TEGRA_TERTIARY_ICTLR_BASE
-       ldr     r0, =TRI_ICTLR_PMC_WAKE_INT
-       str     r0, [r8, #TRI_ICTLR_CPU_IER_SET]
-       mov     pc, lr
-
-/*
- * tegra148_lp1bb_clear_warmboot_flag
- * Clears side effect bit in case it was set during
- * suspend entry. Also clears Warmboot0 flag.
- */
-tegra148_lp1bb_clear_warmboot_flag:
-       ldr     r0, [r4, #PMC_SCRATCH0]
-       bic     r0, r0, #1
-       str     r0, [r4, #PMC_SCRATCH0]
-       ldr     r0, [r4, #PMC_CTRL]
-       bic     r0, r0, #PMC_CTRL_SIDE_EFFECT_LP0
-       str     r0, [r4, #PMC_CTRL]
-       mov     pc, lr
-
-/* Based on value of lp_enter_state, update LP state
- * scratch register
- */
-tegra148_set_lp_state:
-       ldr     r0, lp_enter_state
-       mov     r0, r0, lsl #PMC_LP_STATE_BIT_OFFSET
-       ldr     r1, [r4, #PMC_LP_STATE_SCRATCH_REG]
-       mov     r2, #PMC_LP_STATE_BIT_MASK
-       bic     r1, r2, lsl #PMC_LP_STATE_BIT_OFFSET
-       orr     r1, r0
-       str     r1, [r4, #PMC_LP_STATE_SCRATCH_REG]
-       mov     pc, lr
-
-/* tegra3_lp0_tear_down_core
- *
- * copied into and executed from IRAM
- * puts memory in self-refresh for LP0 and LP1
- */
-tegra3_lp0_tear_down_core:
-       ldr     r0, [r4, #PMC_CTRL]
-       tst     r0, #PMC_CTRL_SIDE_EFFECT_LP0
-       moveq   r0, #PMC_LP_STATE_LP1
-       movne   r0, #PMC_LP_STATE_LP0
-       str     r0, lp_enter_state
-       bleq    tegra148_set_mem_req_interrupt
-       bl      tegra148_set_lp_state
-#endif
        bl      tegra3_save_config
        bl      tegra3_sdram_self_refresh
        bl      tegra3_cpu_clk32k
@@ -1150,12 +996,6 @@ tegra3_cpu_clk32k:
        str r1, [r4, #PMC_SCRATCH1_ECO]
 #endif
 
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       ldr r1, [r4, #PMC_POR_DPD_CTRL]
-       orr r1, r1, #0x47
-       str r1, [r4, #PMC_POR_DPD_CTRL]
-#endif
-
        mov     pc, lr
 
 lp1_clocks_prepare:
@@ -1191,37 +1031,14 @@ lp1_clocks_prepare:
        add     r1, r1, #2
        wait_until r1, r7, r9
 
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        /* disable PLLM via PMC in LP1 */
        ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
        bic     r0, r0, #(1 << 12)
        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
-#endif
 
        ldr     r11, [r4, #PMC_SCRATCH37]       @ load the LP1 flags
        tst     r11, #TEGRA_POWER_LP1_AUDIO     @ check if voice call is going on
-#if !defined(CONFIG_ARCH_TEGRA_14x_SOC)
        bne     powerdown_pll_cx                @ if yes, do not turn off pll-p/pll-a
-#else
-       /*
-         * BB needs PLLP and EMC on voice call/LP1BB. EMC may be clocked by
-         * PLLC so we need to check the EMC source PLL to determine whether
-         * PLLC can be turned OFF
-         */
-       bne     lp1bb_emc_source_check
-       ldr     r0, lp_enter_state
-       cmp     r0, #PMC_LP_STATE_LP1BB         @ check if we're entering LP1BB
-       bne     powerdown_pll_pacx              @ if not, turn off plls p/a/c/x
-lp1bb_emc_source_check:
-       /* find source pll of EMC */
-       ldr     r0, [r5, #CLK_RESET_CLK_SOURCE_EMC]
-       mov     r0, r0, lsr #0x1d
-       cmp     r0, #0x1                        @ EMC clocked by PLLC_OUT0?
-       beq     powerdown_pll_x                 @ if yes, just turn off pll-x
-       cmp     r0, #0x7                        @ EMC clocked by PLLC_UD?
-       beq     powerdown_pll_x                 @ if yes, just turn off pll-x
-       b       powerdown_pll_cx                @ if not, turn off pll-c/pll-x
-#endif
 powerdown_pll_pacx:
        ldr     r0, [r6, #FLOW_CONTROL_CLUSTER_CONTROL]
        tst     r0, #1
@@ -1288,8 +1105,7 @@ tegra3_enter_sleep:
        orr     r0, r0, #FLOW_CTRL_CSR_ENABLE
        str     r0, [r6, r2]
 
-#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC) \
-       || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        tst     r0, #FLOW_CTRL_IMMEDIATE_WAKE
        movne   r0, #FLOW_CTRL_WAITEVENT
        moveq   r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
@@ -1337,8 +1153,7 @@ halted:
 
 tegra3_save_config:
 
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        adr     r2, tegra3_sdram_pad_address
        adr     r8, tegra3_sdram_pad_save
 #endif
@@ -1362,8 +1177,7 @@ padsave_done:
        mov     pc, lr
 
 tegra3_sdram_self_refresh:
-#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        mov32   r0, TEGRA_EMC_BASE              @ r0 reserved for emc base
 #endif
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
@@ -1383,8 +1197,7 @@ enter_self_refresh:
        str     r1, [r0, #EMC_AUTO_CAL_INTERVAL]
        ldr     r1, [r0, #EMC_CFG]
        bic     r1, r1, #(1<<28)
-#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        bic     r1, r1, #(1<<29)
 #endif
        str     r1, [r0, #EMC_CFG]              @ disable DYN_SELF_REF
@@ -1427,8 +1240,7 @@ emcself:
 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
        orr     r1, r1, #7                      @ set E_NO_VTTGEN
 #endif
-#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
-defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
        orr     r1, r1, #0x3f                   @ set E_NO_VTTGEN
 #endif
        str     r1, [r0, #EMC_XM2VTTGENPADCTRL2]
@@ -1497,15 +1309,6 @@ dram_sr_wait4:
        mov     pc, lr
 
 pmc_io_dpd_skip:
-#if defined(CONFIG_ARCH_TEGRA_14x_SOC)
-       /*
-        * Make sure the BGBIAS pads are not in DPD so that when the system
-        * comes out of LP0 at max EMC frequency we can read memory.
-        */
-       ldr     r1, =PMC_IO_DPD2_REQ_CODE_DPD_OFF
-       orr     r1, r1, #PMC_IO_DPD2_REQ_DISC_BIAS
-       str     r1, [r4, #PMC_IO_DPD2_REQ]
-#endif
        dsb
        mov     pc, lr