pcie: host: tegra: WAR for RAW violations
Jay Agarwal [Tue, 14 Oct 2014 06:02:07 +0000 (11:02 +0530)]
Some of reads transaction getting before write
has completed resulting in RAW violation. This
WAR avoids this situation.

Bug 1345350

Change-Id: I56728d00326b193be26ccb4fe68787ebd8a2623d
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/365301
(cherry picked from commit a706735e3c50a70dfee4a3d11378d3a1872a71d7)
Reviewed-on: https://git-master.nvidia.com/r/1595945
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Mantravadi Karthik <mkarthik@nvidia.com>

drivers/pci/host/pci-tegra.c

index 371dc91..7c8b714 100644 (file)
 
 #define RP_VEND_XP                                             0x00000F00
 #define RP_VEND_XP_DL_UP                                       (1 << 30)
+#define RP_VEND_XP_UPDATE_FC_THRESHOLD                         (0xFF << 18)
 
 #define RP_LINK_CONTROL_STATUS                                 0x00000090
 
 #define NV_PCIE2_RP_INTR_BCR                                   0x0000003C
 #define NV_PCIE2_RP_INTR_BCR_INTR_LINE                         (0xFF << 0)
 
+#define NV_PCIE2_RP_PRIV_XP_DL                                 0x00000494
+#define PCIE2_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD                 (0x1FF << 1)
+
+#define NV_PCIE2_RP_RX_HDR_LIMIT                               0x00000E00
+#define PCIE2_RP_RX_HDR_LIMIT_PW_MASK                          (0xFF00)
+#define PCIE2_RP_RX_HDR_LIMIT_PW                               (0x0E << 8)
+
 #define NV_PCIE2_RP_PRIV_MISC                                  0x00000FE0
 #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT                  (0xE << 0)
 #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT                  (0xF << 0)
@@ -1486,6 +1494,19 @@ static void tegra_pcie_apply_sw_war(int index, bool enum_done)
                data = rp_readl(NV_PCIE2_RP_INTR_BCR, index);
                data |= NV_PCIE2_RP_INTR_BCR_INTR_LINE;
                rp_writel(data, NV_PCIE2_RP_INTR_BCR, index);
+               /* WAR for RAW violation on T124/T132 platforms */
+               data = rp_readl(NV_PCIE2_RP_RX_HDR_LIMIT, index);
+               data &= ~PCIE2_RP_RX_HDR_LIMIT_PW_MASK;
+               data |= PCIE2_RP_RX_HDR_LIMIT_PW;
+               rp_writel(data, NV_PCIE2_RP_RX_HDR_LIMIT, index);
+
+               data = rp_readl(NV_PCIE2_RP_PRIV_XP_DL, index);
+               data |= PCIE2_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD;
+               rp_writel(data, NV_PCIE2_RP_PRIV_XP_DL, index);
+
+               data = rp_readl(RP_VEND_XP, index);
+               data |= RP_VEND_XP_UPDATE_FC_THRESHOLD;
+               rp_writel(data, RP_VEND_XP, index);
        }
 }