ARM: Disallow DCC writes from secondary processors
Scott Williams [Mon, 20 Dec 2010 23:40:35 +0000 (15:40 -0800)]
An attempt to access the DCC console from secondary processors will
result in those processors hanging because the JTAG debugger can only
communicate with one core at a time. Allow DCC output only from CPU 0.

Useful for bringup, not necessarily for upstream

Original-Change-Id: I9118555438f5b72b16a2dfccd5b6f98860505d6d
Reviewed-on: http://git-master/r/13876
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Change-Id: I36bb0351e0899f4ad8732fe784623f7eea57dff5

Rebase-Id: R32383c2b0268f8111444b7b75c4fa3d2b3ddbaef

arch/arm/kernel/debug.S

index 14f7c3b..ec88705 100644 (file)
@@ -78,6 +78,11 @@ hexbuf:              .space 16
 #ifndef CONFIG_DEBUG_SEMIHOSTING
 
 ENTRY(printascii)
+#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP)
+               mrc     p15, 0, r3, c0, c0, 5
+               ands    r3, r3, #3
+               movne   pc, lr
+#endif
                addruart_current r3, r1, r2
                b       2f
 1:             waituart r2, r3
@@ -94,6 +99,11 @@ ENTRY(printascii)
 ENDPROC(printascii)
 
 ENTRY(printch)
+#if defined(CONFIG_DEBUG_ICEDCC) && defined(CONFIG_SMP)
+               mrc     p15, 0, r3, c0, c0, 5
+               ands    r3, r3, #3
+               movne   pc, lr
+#endif
                addruart_current r3, r1, r2
                mov     r1, r0
                mov     r0, #0