arm: tegra: Enable cpu power gate, rail gate during LP1
Krishna Reddy [Wed, 26 Sep 2012 00:28:20 +0000 (17:28 -0700)]
Change-Id: I1d72d354e5a83d0355ada65dcda01d842bc8b592
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/138760
(cherry picked from commit bb0dea85a32905e5c3f29c94bdb2ed3d2a164db8)
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/147609
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: Rf30183321c8553141220afe4326cb0e4869cf148

arch/arm/mach-tegra/pm.c

index 62e7ce9..b10e8e7 100644 (file)
@@ -963,8 +963,8 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
        suspend_cpu_complex(flags);
 
 #if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE)
-       /* In case of LP0, program external power gating accordinly */
-       if (mode == TEGRA_SUSPEND_LP0) {
+       /* In case of LP0/1, program external power gating accordinly */
+       if (mode == TEGRA_SUSPEND_LP0 || mode == TEGRA_SUSPEND_LP1) {
                reg = readl(FLOW_CTRL_CPU_CSR(0));
                if (is_lp_cluster())
                        reg |= FLOW_CTRL_CSR_ENABLE_EXT_NCPU; /* Non CPU */