ARM: tegra: sdhci: Remove base_clk from plat data
Pavan Kunapuli [Wed, 26 Jun 2013 12:56:00 +0000 (17:56 +0530)]
Base clock frequency is fixed for the controller and need not be
programmed. Removed base_clk entries from platform data for dalmore,
pluto and macallan platforms.

Bug 1314985

Change-Id: I70dc71589e19bad96e3e1523fab9af5f6e4b7e94
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/242434
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>

arch/arm/mach-tegra/board-dalmore-sdhci.c
arch/arm/mach-tegra/board-macallan-sdhci.c
arch/arm/mach-tegra/board-pluto-sdhci.c

index c92295f..b7a1365 100644 (file)
@@ -111,7 +111,6 @@ struct tegra_sdhci_platform_data dalmore_tegra_sdhci_platform_data0 = {
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
-       .base_clk = 208000000,
 };
 
 static struct resource sdhci_resource0[] = {
index 9711fca..324da3d 100644 (file)
@@ -90,7 +90,6 @@ struct tegra_sdhci_platform_data macallan_tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
-       .base_clk = 208000000,
 };
 
 #ifndef CONFIG_USE_OF
index 7b7882c..85ec395 100644 (file)
@@ -116,7 +116,6 @@ struct tegra_sdhci_platform_data pluto_tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
-       .base_clk = 208000000,
        .uhs_mask = MMC_UHS_MASK_DDR50,
 };