ARM: tegra: clock: ignore timeout warnings on pll_d/d2
Kevin Huang [Wed, 17 Apr 2013 01:44:25 +0000 (18:44 -0700)]
Due to a hardware bug, plld/d2 lock bit cannot be asserted
during DSI unpower-gating. The lock bit can only be locked
after clamping of DSI is removed. It triggers false alarm
when plld/d2 is enabled. Ignore these warnigs when DIS
partition is still clamped.

Bug 1257086
Bug 1258312

Change-Id: I499efa0086dd677df70295efab26f7f8b3045a60
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/220017
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 82e2aad..e8531d6 100644 (file)
@@ -36,6 +36,7 @@
 #include <mach/edp.h>
 #include <mach/hardware.h>
 #include <mach/mc.h>
+#include <mach/powergate.h>
 
 #include "clock.h"
 #include "fuse.h"
@@ -1867,6 +1868,9 @@ static int tegra11_pll_clk_wait_for_lock(
                pr_debug("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
                         c->name, lock_reg, val);
                return 0;
+       } else if ((c->flags & PLLD) &&
+                       tegra_powergate_check_clamping(TEGRA_POWERGATE_DISA)) {
+               pr_debug("Waiting for %s lock.\n", c->name);
        } else {
                pr_err("Timed out waiting for %s lock bit ([0x%x] = 0x%x)\n",
                       c->name, lock_reg, val);