ARM: tegra12: power: Re-direct GPU rail gating control
Alex Frid [Tue, 10 Sep 2013 04:29:47 +0000 (21:29 -0700)]
Replaced direct access to regulator APIs during GPU rail-gating with
dvfs in-band rail control to avoid usage conflict between dvfs and
power gating code.

Bug 1364240
Bug 1318046

Change-Id: Icf5f92bc358f1e701b176054427ffeb308bcabe7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/272357
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/powergate-t12x.c
arch/arm/mach-tegra/tegra12_dvfs.c

index 089a925..0a242c7 100644 (file)
@@ -22,6 +22,7 @@
 #include "powergate-priv.h"
 #include "powergate-ops-txx.h"
 #include "powergate-ops-t1xx.h"
+#include "dvfs.h"
 
 enum mc_client {
        MC_CLIENT_AFI           = 0,
@@ -247,7 +248,7 @@ static struct powergate_partition_info tegra12x_powergate_partition_info[] = {
 
 static DEFINE_SPINLOCK(tegra12x_powergate_lock);
 
-static struct regulator *gpu_reg;
+static struct dvfs_rail *gpu_rail;
 
 #define HOTRESET_READ_COUNT    5
 static bool tegra12x_stable_hotreset_check(u32 stat_reg, u32 *stat)
@@ -389,8 +390,8 @@ static int tegra12x_gpu_powergate(int id, struct powergate_partition_info *pg_in
 
        udelay(10);
 
-       if (gpu_reg && tegra_powergate_is_powered(id)) {
-               ret = regulator_disable(gpu_reg);
+       if (gpu_rail && tegra_powergate_is_powered(id)) {
+               ret = tegra_dvfs_rail_power_down(gpu_rail);
                if (ret)
                        goto err_power_off;
        } else
@@ -408,18 +409,18 @@ static int tegra12x_gpu_unpowergate(int id,
 {
        int ret = 0;
 
-       if (!gpu_reg) {
-               gpu_reg = regulator_get(NULL, "vdd_gpu");
-               if (IS_ERR_OR_NULL(gpu_reg)) {
+       if (!gpu_rail) {
+               gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu");
+               if (IS_ERR_OR_NULL(gpu_rail)) {
                        WARN(1, "No GPU regulator?\n");
                        goto err_power;
                }
+       } else {
+               ret = tegra_dvfs_rail_power_up(gpu_rail);
+               if (ret)
+                       goto err_power;
        }
 
-       ret = regulator_enable(gpu_reg);
-       if (ret)
-               goto err_power;
-
        /* If first clk_ptr is null, fill clk info for the partition */
        if (!pg_info->clk_info[0].clk_ptr)
                get_clk_info(pg_info);
@@ -619,8 +620,8 @@ bool tegra12x_powergate_is_powered(int id)
        u32 status = 0;
 
        if (TEGRA_IS_GPU_POWERGATE_ID(id)) {
-               if (gpu_reg)
-                       return regulator_is_enabled(gpu_reg);
+               if (gpu_rail)
+                       return tegra_dvfs_is_rail_up(gpu_rail);
        } else {
                status = pmc_read(PWRGATE_STATUS) & (1 << id);
                return !!status;
index 37ce095..9d56b73 100644 (file)
@@ -84,6 +84,7 @@ static struct dvfs_rail tegra12_dvfs_rail_vdd_gpu = {
        .max_millivolts = 1350,
        .min_millivolts = 700,
        .step = VDD_SAFE_STEP,
+       .in_band_pm = true,
        .vmin_cdev = &gpu_vmin_cdev,
        .alignment = {
                .step_uv = 10000, /* 10mV */