ARM: tegra: power: Fix Tegra2 power timer rate
Alex Frid [Sun, 19 Feb 2012 08:24:18 +0000 (00:24 -0800)]
Commit cb0428145196ed7a75861c78d28f46b6bc8d2320 implemented LP0
state entry with fast CPU and system bus clocks only for Tegra3,
but changed power timers rate calculation in the common Tegra2
and Tegra3 path. Fixing it now.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 9e66d6adf6ab1fe06eee63baf0f1f684715d1ae2)

Change-Id: Iac276f048fed4edbee318cadddb862e45ba851c6
Reviewed-on: http://git-master/r/86550
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R58e05290ae8c359a5be22271961bae2152ab3966

arch/arm/mach-tegra/pm.c

index 55311f8..ad91c9c 100644 (file)
@@ -691,7 +691,9 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
 
        switch (mode) {
        case TEGRA_SUSPEND_LP0:
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
                rate = clk_get_rate_all_locked(tegra_pclk);
+#endif
                if (pdata->combined_req) {
                        reg |= TEGRA_POWER_PWRREQ_OE;
                        reg &= ~TEGRA_POWER_CPU_PWRREQ_OE;