mmc: tegra: Fix parent clk configuration
Pavan Kunapuli [Fri, 28 Mar 2014 11:43:24 +0000 (16:43 +0530)]
Do not ignore parent clk setting and parent clock source flag
update for any case. For eMMC, in resume, without pll_c as clk
source, 200MHz cannot be set in HS200 mode set.

Bug 1480583

Reviewed-on: http://git-master/r/389704
(cherry picked from commit b9b0cb1541d66ba2450a680666c3fe962b4f71df)

Change-Id: I7898a57871cd16de49142a6534a998bef0c43529
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/395205
(cherry picked from commit 720c60aef1859b9c0d913c131203e02e6af4c3e6)
Reviewed-on: http://git-master/r/412607
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>

drivers/mmc/host/sdhci-tegra.c

index df32e42..5c4c6fe 100644 (file)
@@ -1301,13 +1301,12 @@ static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
        if ((pll_c_freq > desired_rate) && (pll_p_freq > desired_rate)) {
                if (pll_p_freq <= pll_c_freq) {
                        desired_rate = pll_p_freq;
-                       parent_clk = pll_p;
+                       pll_c_freq = 0;
                } else {
                        desired_rate = pll_c_freq;
-                       parent_clk = pll_c;
+                       pll_p_freq = 0;
                }
                rc = clk_set_rate(pltfm_host->clk, desired_rate);
-               goto set_clk_parent;
        }
 
        if (pll_c_freq > pll_p_freq) {
@@ -1323,7 +1322,6 @@ static void tegra_sdhci_clock_set_parent(struct sdhci_host *host,
        } else
                return;
 
-set_clk_parent:
        rc = clk_set_parent(pltfm_host->clk, parent_clk);
        if (rc)
                pr_err("%s: failed to set pll parent clock %d\n",